CN109841519B - 形成氮化物半导体器件的方法 - Google Patents

形成氮化物半导体器件的方法 Download PDF

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CN109841519B
CN109841519B CN201811397529.6A CN201811397529A CN109841519B CN 109841519 B CN109841519 B CN 109841519B CN 201811397529 A CN201811397529 A CN 201811397529A CN 109841519 B CN109841519 B CN 109841519B
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CN109841519A (zh
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吉田智洋
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Sumitomo Electric Industries Ltd
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Abstract

本发明披露了一种形成氮化物半导体器件的方法。该方法包括如下步骤：(a)在半导体堆叠体上形成绝缘膜，该绝缘膜包括第一氮化硅(SiN)膜、氧化硅(SiO2)膜和第二SiN膜；(b)在绝缘膜中形成开口；(c)将SiO2膜中的开口扩大；(d)通过利用绝缘膜作为掩模，在半导体堆叠体中形成凹槽；(e)在第二SiN膜上沉积构成掺杂区域的氮化物半导体材料，同时在凹槽内选择性地生长掺杂区域；以及(f)通过去除SiO2膜和第二SiN膜，从而去除沉积于第二SiN膜上的氮化物半导体材料。

Description

形成氮化物半导体器件的方法
相关申请的交叉引用
本申请基于并要求2017年11月24日提交的在先日本专利申请No.2017-225868的优先权，该专利申请的全部内容以引用方式并入本文。
技术领域
本发明涉及形成氮化物半导体器件的方法，具体而言，涉及选择性地生长源极和漏极的掺杂区域的方法。
背景技术
日本专利申请公开No.JP2008-227432A披露了一种形成氮化物半导体器件的方法，其中该方法选择性地生长n+接触区，以使得源极和漏极发生欧姆接触，然后对选择性生长的n+区进行化学机械研磨(CMP)。
在氮化物半导体器件的制造方法领域中，在形成于半导体层的凹槽中选择性地生长用于欧姆接触的掺杂区域是公知技术。例如，在具有主要由氮化物半导体材料制成的高电子迁移率晶体管(HEMT)类型的器件中，为了降低不可避免地在沟道(其形成于沟道层与阻挡层之间的界面处)与源极和漏极之间产生的通路电阻，首先形成深度到达沟道的凹槽，然后选择性地在该凹槽内形成掺杂区域或掺杂半导体层。源极和漏极不仅可降低其对于掺杂区域的接触电阻，而且还可降低由电极至沟道的通路电阻。
然而，半导体层的选择性生长、尤其是氮化物半导体层的选择性生长有时会伴随表面中的毛刺，尤其是生长层的外围的表面中的毛刺。对于选择性地生长半导体层的区域、尤其是该区域的外周，因为该区域的外部被掩模覆盖并且此处几乎没有原料被消耗，因此由该区域的外部提供了过多的原料。因此，该区域外周中的选择性生长的半导体层趋向于形成小丘，这些小丘有时会造成半导体器件的失效。例如，小丘形成波动，这有时会降低沉积于其上的绝缘膜的紧密性或附着性，或者当器件设置有具有T状截面的栅极时，在T形栅极与掺杂区域中的小丘之间发生短路的可能性增加。
发明内容
本发明的一个方面涉及形成氮化物半导体器件的方法。该方法包括如下步骤：(a)在半导体堆叠体上形成绝缘膜，其中从半导体堆叠体侧起，绝缘膜包括第一氮化硅(SiN)膜、氧化硅(SiO2)膜和第二SiN膜；(b)在绝缘膜中形成开口，以暴露半导体堆叠体的表面；(c)将SiO2膜中的开口扩大；(d)在半导体堆叠体中形成凹槽；(e)在该凹槽内生长掺杂区域，其中掺杂区域由氮化物材料制成，并且使氮化物材料同时沉积在第二SiN膜上；以及(f)通过利用酸溶液除去SiO2膜和第二SiN膜，从而除去位于第二SiN膜上的氮化物材料。
附图说明
图1为通过根据本发明实施方案的方法形成的高电子迁移率晶体管(HEMT)类型的半导体器件的截面视图；
图2A至图2C为图1所示HEMT在根据本发明实施方案的方法的各步骤中的截面视图；
图3A至图3C为图1所示HEMT在图2C所示步骤之后的所述方法的各步骤中的截面视图；
图4A至图4C为图1所示HEMT在图3C所示步骤之后的所述方法的各步骤中的截面视图；并且
图5A和图5B为图1所示HEMT在图4C所示步骤之后的所述方法的各步骤中的截面视图。
具体实施方式
接下来，将参照附图描述根据本发明的一些实施方案。然而，本发明并不局限于这些实施方案，而是具有由随附权利要求限定的范围，并且包括在权利要求和与之相当的范围内的所有改变和修改。此外，在附图描述中，相同或类似的数字和符号表示相同或类似的元素，并且不再赘述。
图1为由根据本发明实施方案的方法形成的氮化物半导体器件的截面图，其中半导体器件1A为高电子迁移率晶体管(HEMT)类型。HEMT 1A包括衬底10、半导体堆叠体18、氮化硅(SiN)膜21、以及源极31、漏极32和栅极33。自衬底10侧起，半导体堆叠体18包括缓冲层11、沟道层12、阻挡层13和盖层14，其中沟道层12和阻挡层13可在沟道层12中在这二者之间的界面处诱导产生二维电子气(2DEG)。2DEG可为HEMT 1A的沟道。
所制备的用于在其上外延生长半导体层的衬底10可由氮化镓(GaN)、碳化硅(SiC)、蓝宝石(Al2O3)、硅(Si)和/或金刚石(C)制成。衬底10可具有主平面，半导体层11至14在该主平面上外延生长。设置缓冲层11(其生长于衬底10上)是为了在沟道层12形成与衬底10(如SiC、Al2O3、Si等)间的异质界面时，提高沟道层12和阻挡层13的质量。缓冲层11可由一种氮化物半导体材料、通常是氮化铝(AlN)制成。
沟道层12(其外延生长于缓冲层11上)在与阻挡层13间的界面处形成2DEG，其中2DEG成为HEMT 1A的沟道，在该沟道内，电流由漏极32流向源极31。沟道层12可由氮化镓(GaN)制成，其厚度为0.2μm至2.0μm。
阻挡层13(其外延生长于沟道层12上)可由带隙能量大于沟道层12的带隙能量的氮化物半导体材料制成。确切地说，阻挡层13的电子亲和性小于沟道层12的电子亲和性，其中电子亲和性定义为由原子核中提取一个电子并将电子移动至无穷远所需的能量。具体而言，阻挡层13可由氮化铝镓(AlGaN)、氮化铟镓(InAlN)和氮化铟铝镓(InAlGaN)中的一种材料制成。本实施方案提供了厚度为5nm至30nm的由AlGaN制成的阻挡层13。
盖层14(其外延生长于阻挡层13上)也可由氮化物半导体材料制成，其厚度为(例如)1nm，优选小于5nm。本实施方案提供了由GaN或n型GaN制成的盖层14。HEMT 1A可省略盖层14。
HEMT 1A还具有埋于半导体堆叠体18内的掺杂区域15和16。具体而言，掺杂区域15和16填充凹槽18a和18b，凹槽18a和18b形成于半导体堆叠体18的表面，并且凹槽18a和18b的底部穿过盖层14和阻挡层13并到达沟道层12。凹槽18a和18b各自的底部通过沟道层12形成，这意味着填埋凹槽18a和18b的掺杂区域15和16与沟道层12以及沟道层12和阻挡层13间的界面(即，HEMT 1A的沟道)接触。
设置掺杂区域15和16是为了降低源极31和漏极32与沟道间的通路电阻，掺杂区域15和16的掺杂密度为1.0×1018～1.0×1020cm-3，其远高于沟道层12和阻挡层13的掺杂密度。掺杂区域15和16可由氮化镓(GaN)、氮化铝镓(AlGaN)等制成，其表面从半导体堆叠体18中露出，源极31和漏极32形成于该表面上。源极31和漏极32分别与掺杂区域15和16形成欧姆接触。与电极31和32与阻挡层13和/或沟道层12接触而掺杂区域15和16未介于其之间的布置方式相比，分别与掺杂区域15和16直接接触的源极31和漏极32可降低其接触电阻。盖层14和阻挡层13之间形成异质势垒，该异质势垒充当了载流子由电极31和32向沟道传输的势垒。掺杂区域15和16之间的距离大于0.5μm且小于3.0μm，通常为约1.0μm。掺杂区域15和16间的距离较短时，可降低HEMT 1A的通路电阻，并提高其高频性能。
可通过使钛(Ti)和铝(Al)的堆叠金属合金化从而形成源极31和漏极32，其中可用钽(Ta)取代Ti。堆叠金属还可在Al上具有另一层Ti或Ta。本实施方案的HEMT 1A具有形成于掺杂区域15和16上的源极31和漏极32，但是源极31和漏极32并未覆盖全部的掺杂区域15和16。即，电极31和32留下了掺杂区域15和16的外周区域，该外周区域并未与电极31和32重叠。
覆盖半导体堆叠体18的SiN膜21具有开口21a至21c，这些开口21a至21c分别对应于源极31、漏极32和栅极33。即，掺杂区域15和16填充开口21a和21b，并且其顶部水平面高于SiN膜21的顶部水平面。此外，掺杂区域15和16各自的外周区域在SiN膜21上延伸。开口21c的宽度决定了HEMT 1A的栅极长度。
设置于源极31和漏极32之间的栅极33的截面呈T字状，其垂直柱填充SiN膜21中的开口21c，并且垂直柱的底部与半导体堆叠体18接触。栅极33中的垂直柱与位于半导体堆叠体18的顶部的盖层14接触，但是栅极33中的垂直柱可与阻挡层13接触。栅极33可具有另一种堆叠金属，即镍(Ni)和金(Au)的堆叠金属，其中Ni与半导体堆叠体18接触以与之形成肖特基接触。在可供替代的实施方案中，Ni可替换为铂(Pt)。
接下来，将参照图2A至图2C、图3A至图3C、图4A至图4C、图5A和图5B来描述形成HEMT 1A的方法，其中这些附图通过HEMT 1A的各截面图示出了HEMT 1A形成方法中的步骤。
首先，如图2A所示，利用(例如)金属有机化学气相沉积(MOCVD)技术，通过依次进行层的外延生长从而在衬底10上形成半导体堆叠体18。具体而言，在衬底10上生长AlN缓冲层11，在AlN缓冲层11上生长GaN沟道层12，在GaN沟道层12上生长AlGaN或InAlN阻挡层13，并且在阻挡层上生长n型GaN盖层14。通过MOCVD技术进行的层11至14的外延生长使用了三甲基铝(TMA)和三甲基镓(TMG)作为III族元素(即，Al和Ga)的原料；同时，外延生长使用氨(NH3)作为氮N的原料。当阻挡层由InAlN制成时，外延生长可使用三甲基铟(TMI)作为In的原料。
随后，三重(tri-fold)绝缘膜覆盖半导体堆叠体18，其中自半导体堆叠体18一侧起，绝缘膜包括SiN膜21(其为第一SiN膜)、氧化硅(SiO2)膜22和另一SiN膜23(其为第二SiN膜)。第一SiN膜21优选致密且牢固，以在掺杂区域15和16的生长过程中的高温下保护半导体堆叠体18。在半导体堆叠体18的生长之后，本实施方案随后继续通过(例如)低压化学气相沉积(LPCVD)技术和/或MOCVD技术作为原位(in-situ)方法形成第一SiN膜21。LPCVD技术可利用原料气体单硅烷(SiH4)和氨(NH3)在800℃至900℃的温度下形成第一SiN膜21。
可通过常压(ordinal pressure)化学气相沉积技术(该技术有时也称为热CVD或等离子辅助CVD(p-CVD))和/或溅射来形成SiO2膜22。SiO2膜22的厚度远大于第一SiN膜21的厚度，例如，SiO2膜22的厚度为100nm至400nm，通常为200nm。第二SiN膜23(其也可以通过热CVD、p-CVD和/或溅射形成)的厚度为40nm至50nm，通常为40nm。
随后，如图2C所示，在第二SiN膜23上制备具有开口Ra和Rb的图案化的光刻胶R。具体而言，通过依次进行如下光刻，即利用光刻胶旋涂第二SiN膜23、进行曝光、并最终使光刻胶显影，从而在第二SiN膜23上形成具有开口Ra和Rb的图案化光刻胶。开口Ra和Rb对应于凹槽18a和18b，并且这两个开口Ra和Rb的尺寸基本彼此相等。
随后，如图3A所示，通过干法蚀刻(例如反应性离子蚀刻(RIE))在第二SiN膜23、SiO2膜22和第一SiN膜21中形成开口20a和20b，其中开口20a和20b完全贯穿这些绝缘膜21至23。RIE可使用六氟化硫(SF6)、四氟甲烷(CF4)、三氟甲烷(CHF3)、六氟丙烯(C3F6)和六氟乙烷(C2F6)中的一种反应性气体。因为这种氟化物可选择性地蚀刻含硅(Si)的材料，而不蚀刻氮化物半导体材料；使用氟化物的RIE可蚀刻绝缘膜21至23，但是很难或几乎不可能蚀刻半导体堆叠体18。此外，RIE可形成开口20a和20b，其各条边几乎垂直于衬底10的主表面。氮化物半导体堆叠体18的顶面暴露于开口20a和20b中。
随后，如图3B所示，该方法通过利用绝缘膜21至23作为蚀刻掩模，并使用含氯(Cl)的反应性气体对半导体堆叠体18进行蚀刻，从而在半导体堆叠体18中的由开口20a和20b露出的部分中形成凹槽18a和18b。与氟化物不同的是，含Cl的反应性气体可选择性地蚀刻半导体堆叠体18中的氮化物半导体材料，而不蚀刻含Si的绝缘膜21至23。本发明方法的RIE完全蚀刻开口20a和20b内的盖层14和阻挡层13，但是部分蚀刻沟道层12；即，凹槽18a和18b各自的底部到达沟道层12。由于在沟道层12和阻挡层13之间的界面处形成有2DEG，确切地说，是在沟道层12中的其与阻挡层13间的界面处形成有2DEG，因此，凹槽18a和18b在其各自的侧壁中暴露出了2DEG的边缘或末端，这意味着将要形成于凹槽18a和18b中的掺杂区域15和16可与2DEG的边缘直接接触，这降低了由电极31和32至2DEG的通路电阻。
随后，如图3C所示，该方法选择性地将SiO2膜22中的开口20a和20b扩大；即，该方法使SiO2膜22的边缘相对于第一SiN膜21和第二SiN膜23的边缘回缩。缓冲氢氟(HF)酸可选择性地蚀刻SiO2膜22，而不蚀刻第一SiN膜21和第二SiN膜23。SiO2膜22可相对于SiN膜21和23回缩100nm至200nm。沉积于SiO2膜22上的第二SiN膜23形成了长度为100nm至200nm的悬臂(overhang)。由于SiO2膜22相对于SiN膜21和23的边缘回缩，因此掺杂区域15和16优选在其之间形成至少0.5μm的间隙。窄于0.5μm的间隙可能会将需要保留在掺杂区域15和16之间的SiO2膜22除去。
所述方法在形成开口20a和20b之后，但在将SiO2膜22中的开口20a和20b扩大之前蚀刻半导体堆叠体18，以形成凹槽18a和18b。在可替代的方式中，该方法可在将SiO2膜22中的开口20a和20b扩大的步骤之后形成凹槽18a和18b。即，可在形成开口20a和20b之后进行形成凹槽18a和18b的步骤，而与将SiO2膜22中的开口扩大的步骤无关。这种工序也可在绝缘膜22和23中形成悬臂，并在半导体堆叠体18中形成凹槽18a和18b。
随后，除去位于第二SiN膜23上的图案化光刻胶R。此外，光刻胶R的去除步骤并不局限于形成凹槽18a和18b之后的工序。可在形成开口20a和20b之后的任何步骤中除去图案化光刻胶R。
随后，如图4B所示，通过使用(例如)MOCVD、分子束外延(MBE)等，从而在凹槽18a和18b内选择性地生长掺杂区域15和16。掺杂区域15和16可由硅(Si)掺杂的n+型GaN或n+型AlGaN制成。当使用MOCVD进行掺杂区域15和16的再生长时，MOCVD可使用单硅烷(SiH4)作为掺杂Si的原材料。第一SiN膜21的厚度为至少5nm，优选5nm至20nm，同时，SiO2膜22的厚度优选大于掺杂区域15和16的厚度。本实施方案使掺杂区域15和16再生长至其厚度为至少100nm。由于SiO2膜22的边缘相对于第一SiN膜21和第二SiN膜23的边缘回缩，因此掺杂区域15和16不仅可在凹槽18a和18b内再生长，而且还在第一SiN膜21上的开口20a和20b的外周区域中再生长。
再生长通常在(例如)800℃至1000℃的温度下进行，当衬底10上存在氧化物材料时，这加速了再生长层的氧化。在本实施方案中，由SiO2制成的第二绝缘膜更靠近半导体堆叠体18。然而，第一SiN膜21介于SiO2膜22和半导体堆叠体18之间，这防止了半导体堆叠体18的表面氧化。此外，第一SiN膜21的形成与半导体堆叠体18的生长是连续的，不会使半导体堆叠体暴露于大气中，或者SiN膜21通过LPCVD技术形成；因此，在掺杂区域15和16的再生长过程中的高温下，第一SiN膜21是稳定的。第一SiN膜21的沉积温度优选高于掺杂区域15和16的再生长温度，并且第一SiN膜21的厚度优选为至少5nm，以抑制或基本抑制半导体堆叠体18的表面因SiO2膜22中所含的氧而氧化。掺杂区域15和16的再生长同时在第二SiN膜23上沉积氮化物材料，其中该氮化物材料为掺杂区域15和16的原料。由于氮化物材料难以在非结晶材料(如第二SiN膜23)上以单晶形式生长；因此第二SiN膜23上的氮化物材料17为多晶，或者有时为原子簇。
随后，如图4C所示，该方法通过除去SiO2膜，从而除去了在掺杂区域15和16的再生长过程中沉积于第二SiN膜23上的氮化物材料17。具体而言，缓冲氢氟(HF)酸可选择性地除去SiO2膜22，而不会除去第一SiN膜21和第二SiN膜23。缓冲氢氟酸对SiO2膜和SiN膜的蚀刻速度分别为200nm/分钟至300nm/分钟和0.3nm/分钟以下。因此，选择性地蚀刻SiO2膜22而不蚀刻SiN膜21和23容易进行。此外，通过除去或溶解SiO2膜22，可除去第二SiN膜23连同其上的氮化物材料17，这被称为剥离技术。
在可供替代的方式中，可在上述剥离方法中选择性地除去SiO2膜之后，除去SiN膜21，这留下了位于半导体堆叠体18上的掺杂区域15和16，并且暴露了半导体堆叠体18的全部表面。随后，另一SiN膜可覆盖半导体堆叠体18和掺杂区域15和16的全部表面。
由于第二SiN膜23形成了相对于SiO2膜22的悬臂，因此沉积于第二SiN膜23上的氮化物材料17不与掺杂区域15和16接触。即，第二SiN膜23中的悬臂可在氮化物材料17和掺杂区域15和16之间形成间隙，从而能够使蚀刻剂(缓冲氢氟(HF)酸)可靠地与SiO2膜22接触，并加速对SiO2膜22的蚀刻。此外，第二SiN膜23中的悬臂、或者回缩的SiO2膜22可抑制在凹槽18a和18b的外周区域(即，掺杂区域15和16的外周区域)中不均匀供给用于掺杂区域15和16的再生长的原材料，这可有效防止在掺杂区域15和16的外周区域中形成毛刺或小丘。
为了确保在再生长过程中形成悬臂，优选如此形成第二SiN膜23，使得在扩大开口20a和20b(其通过图3A所示步骤的干法蚀刻形成)之后，第二SiN膜23留下的厚度为至少20nm。通过确保在第二SiN膜23中保留悬臂，可有效地使掺杂区域15和16与沉积在第二SiN膜23上的氮化物材料17隔离。
掺杂区域15和16的厚度优选小于SiO2膜22的厚度，以防止沉积于第二SiN膜23上的氮化物材料17与掺杂区域15和16连接在一起，或者掺杂区域15和16的顶部水平面优选低于SiO2膜22的顶部水平面，这可确保掺杂区域15和16与沉积在第二SiN膜23上的氮化物材料17隔离。
随后，该方法分别在掺杂区域15和16上形成源极31和漏极32。具体而言，该方法在掺杂区域15和16上堆叠金属钛(Ti)、铝(Al)和另一层钛(Ti)，其中可将Ti替换为钽(Ta)。可利用金属蒸发进行这些金属的堆叠。然后，在500℃至600℃的温度下使堆叠金属合金化，其中本实施方案在550℃的温度下使堆叠金属Ta/Al/Ta合金化。
然后，如图5B所示，在源极31和漏极32之间，在半导体堆叠体18上形成栅极33。该方法首先通过常规光刻或电子束曝光在第一SiN膜21上制备图案化光刻胶(图中未示出)，然后利用图案化光刻胶作为蚀刻掩模对第一SiN膜21进行蚀刻，从而形成栅极开口21c，该栅极开口21c使半导体堆叠体18暴露出来。随后，常规技术(如金属蒸发)在半导体堆叠体18以及图案化光刻胶上堆叠金属(例如)镍(Ni)、钯(Pd)和金(Au)Ni/Pd/Au。可通过用溶剂将图案化光刻胶溶解，从而去除沉积于图案化光刻胶上的残余金属，这通常称为剥离技术。如图5B所示，栅极可具有T状截面，其中字母T的水平条可与掺杂区域15和16重叠。这种方式是通过外周区域不存在小丘的掺杂区域15和16实现的。通过缩小T形栅极33与掺杂区域15和16之间的间隙，可有效降低由源极31和漏极32至沟道的通路电阻。
因此，完成了根据本发明的HEMT 1A的形成方法。HEMT 1A可进一步具有由(例如)氮化硅(SiN)制成的绝缘膜，以覆盖第一SiN膜21、源极31、漏极32和栅极33的整个表面，其中该SiN膜通常称为钝化膜，以通过电学和机械的方式覆盖并保护HEMT 1A。通过在钝化膜中形成开口，可形成各电极31至33的互连(interconnections)，从而通过钝化膜中的相应开口与电极接触。
根据本实施方案的HEMT 1A的形成方法通过利用在第二SiN膜23中相对于SiO2膜22所形成的悬臂，从而有效且可靠地使沉积于第二SiN膜23上的氮化物材料17与在凹槽18a和18b中选择性地生长的掺杂区域15和16分隔开。第二SiN膜23中的悬臂可有效防止选择性地生长的掺杂区域15和16在其外周区域中形成小丘。不存在小丘的掺杂区域15和16可形成与之更为靠近的栅极33，这降低了由源极31和漏极32至沟道的通路电阻，而不会使HEMT 1A的耐压性劣化。
此外，外周区域未形成小丘的掺杂区域15和16可增强绝缘膜(即，覆盖掺杂区域15和16以及电极31至33的钝化膜)的附着性或致密性。上述现有专利文献中所披露的方法使用了用于半导体层的再生长的掩模，其中该掩模仅由SiO2制成。然而，在掺杂区域15和16的再生长过程中，SiO2膜中所含的氧可能会使半导体堆叠体的表面氧化。改进的方法将由SiN制成的掩模用于再生长，该SiN膜暴露于再生长的高温下并被硬化，这使得难以或几乎不可能通过氢氟酸除去硬化的SiN膜。根据本发明的方法可针对半导体层中将要选择性生长掺杂区域的表面的氧化的课题以及除去用于选择性生长的掩模的简易性提供一种解决方案。
尽管已经出于示例的目的描述了本发明的具体实施方案，但是各种改变和修改对于本领域技术人员而言是显而易见的。例如，所述实施方案关注于HEMT类型的半导体器件。然而，将双层绝缘掩模用于选择性生长的根据本发明的方法可应用于其他类型的半导体器件，或者应用于使半导体层再生长的方法。因此，所有这种改变和修改落入本发明的精神和范围内，并且随附权利要求旨在包括所有这些改变和修改。

Claims (12)

1.一种形成氮化物半导体器件的方法，所述方法包括如下步骤：
在半导体堆叠体的顶面上形成绝缘膜，自所述半导体堆叠体的所述顶面起，该绝缘膜包括第一氮化硅SiN膜、氧化硅SiO2膜和第二SiN膜；
在所述绝缘膜中形成开口以暴露所述半导体堆叠体的所述顶面；
将形成于所述SiO2膜中的所述开口扩大；
通过利用所述绝缘膜作为蚀刻掩模，在所述半导体堆叠体中形成凹槽；
在所述凹槽内生长由氮化物半导体材料制成的掺杂区域，所述掺杂区域的生长使得所述氮化物半导体材料沉积于所述第二SiN膜上；以及
通过去除所述SiO2膜，从而去除所述第二SiN膜和沉积于所述第二SiN膜上的所述氮化物半导体材料。
2.根据权利要求1所述的方法，
其中形成绝缘膜的步骤形成了厚度为至少5nm的所述第一SiN膜和厚度为至少100nm的所述SiO2膜。
3.根据权利要求2所述的方法，
其中形成绝缘膜的步骤形成了厚度为40nm至50nm的所述第二SiN膜。
4.根据权利要求1所述的方法，
其中在将所述SiO2膜中的所述开口扩大的步骤中，使所述开口中的所述SiO2膜的边缘相对于所述开口中的所述第二SiN膜的边缘回缩100nm至200nm。
5.根据权利要求1所述的方法，
其中生长掺杂区域的步骤中所生长的氮化物半导体层的厚度小于所述SiO2膜的厚度。
6.根据权利要求1所述的方法，
其中形成绝缘膜的步骤通过低压化学气相沉积(LPCVD)法在800℃至900℃的温度下形成所述第一SiN膜。
7.根据权利要求1所述的方法，
其中形成绝缘膜的步骤在形成所述半导体堆叠体之后进行，以在生长所述半导体堆叠体的炉内形成所述第一SiN膜，而不使所述半导体堆叠体暴露于大气中。
8.根据权利要求1所述的方法，
其中在所述半导体堆叠体中形成凹槽的步骤在将所述SiO2膜中的所述开口扩大的步骤之前进行。
9.根据权利要求1所述的方法，
其中在所述半导体堆叠体中形成凹槽的步骤在将所述SiO2膜中的所述开口扩大的步骤之后进行。
10.根据权利要求1所述的方法，
还包括在形成绝缘膜的步骤之前，在衬底上生长氮化物半导体层的步骤，自所述衬底的顶面起，所述氮化物半导体层包括缓冲层、氮化镓GaN沟道层、和氮化铝镓AlGaN阻挡层，
其中这样进行形成凹槽的步骤，使得所述凹槽的底部到达所述沟道层。
11.根据权利要求10所述的方法，
其中生长所述氮化物半导体层的步骤还在所述阻挡层上生长n型氮化镓盖层。
12.根据权利要求10所述的方法，
其中生长掺杂区域的步骤掺杂n型杂质，该n型杂质的密度大于所述沟道层和所述阻挡层中的杂质的密度。
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