TW202410461A - 高電子遷移率電晶體及其製作方法 - Google Patents

高電子遷移率電晶體及其製作方法 Download PDF

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TW202410461A
TW202410461A TW111131884A TW111131884A TW202410461A TW 202410461 A TW202410461 A TW 202410461A TW 111131884 A TW111131884 A TW 111131884A TW 111131884 A TW111131884 A TW 111131884A TW 202410461 A TW202410461 A TW 202410461A
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gate electrode
layer
type semiconductor
electron mobility
high electron
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葉治東
張祐嘉
陳柏瑜
王允俊
李瑞池
廖文榮
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聯華電子股份有限公司
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Priority to TW111131884A priority Critical patent/TW202410461A/zh
Priority to CN202211108116.8A priority patent/CN117672849A/zh
Priority to US17/951,119 priority patent/US20240071758A1/en
Priority to EP22204107.1A priority patent/EP4328976A1/en
Publication of TW202410461A publication Critical patent/TW202410461A/zh

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Abstract

本發明揭露一種製作高電子遷移率電晶體(high electron mobility transistor, HEMT)的方法，其主要先形成一緩衝層於基底上，然後形成一阻障層於該緩衝層上，形成一P型半導體層於該阻障層上，形成一閘極電極層於該P型半導體層上，再圖案化該閘極電極層以形成一閘極電極，其中該閘極電極包含一傾斜側壁。

Description

高電子遷移率電晶體及其製作方法
本發明是關於一種高電子遷移率電晶體及其製作方法。
以氮化鎵基材料(GaN-based materials)為基礎的高電子遷移率電晶體具有於電子、機械以及化學等特性上之眾多優點，例如寬能隙、高崩潰電壓、高電子遷移率、大彈性模數(elastic modulus)、高壓電與壓阻係數(high piezoelectric and piezoresistive coefficients)等與化學鈍性。上述優點使氮化鎵基材料可用於如高亮度發光二極體、功率開關元件、調節器、電池保護器、面板顯示驅動器、通訊元件等應用之元件的製作。
本發明一實施例揭露一種製作高電子遷移率電晶體(high electron mobility transistor, HEMT)的方法，其主要先形成一緩衝層於基底上，然後形成一阻障層於該緩衝層上，形成一P型半導體層於該阻障層上，形成一閘極電極層於該P型半導體層上，再圖案化該閘極電極層以形成一閘極電極，其中該閘極電極包含一傾斜側壁。
請參照第1圖至第4圖，第1圖至第4圖為本發明一實施例製作高電子遷移率電晶體之方法示意圖。如第1圖所示，首先提供一基底12，例如一由矽、碳化矽或氧化鋁(或可稱藍寶石)所構成的基底，其中基底12可為單層基底、多層基底、梯度基底或上述之組合。依據本發明其他實施例基底12又可包含一矽覆絕緣(silicon-on-insulator, SOI)基底。
然後於基底12表面形成一選擇性核晶層(nucleation layer)(圖未示)以及一緩衝層14。在一實施例中，核晶層較佳包含氮化鋁而緩衝層14包含III-V族半導體例如氮化鎵，其厚度可藉於0.5微米至10微米之間。在一實施例中，可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於基底12上形成緩衝層14。
接著可選擇性於緩衝層14表面形成一非刻意摻雜(unintentionally doped)緩衝層(圖未示)。在本實施例中，非刻意摻雜緩衝層較佳包含III-V族半導體，例如氮化鎵或更具體而言非刻意摻雜氮化鎵。在一實施例中，可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於緩衝層14上形成非刻意摻雜緩衝層。
隨後形成一阻障層16於非刻意摻雜緩衝層或緩衝層14表面。在本實施例中阻障層16較佳包含III-V族半導體例如N型氮化鋁鎵(Al xGa 1-xN)，其中0＜x＜1，阻障層16較佳包含一由磊晶成長製程所形成之磊晶層，且阻障層16可包含矽或鍺之摻質。如同上述形成緩衝層14的方式，可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於緩衝層14上形成阻障層16。
接著依序形成一P型半導體層18、一閘極電極層20、一硬遮罩22以及一圖案化遮罩24如圖案化光阻於阻障層16上。在一實施例中，P型半導體層18較佳包含P型氮化鎵，且可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於阻障層16表面形成P型半導體層18。
依據本發明一實施例，閘極電極層20較佳由蕭特基金屬所構成，其中閘極電極層20可包含金、銀、鉑、鈦、鋁、鎢、鈀或其組合。在一些實施例中，可利用電鍍製程、濺鍍製程、電阻加熱蒸鍍製程、電子束蒸鍍製程、物理氣相沉積(physical vapor deposition, PVD)製程、化學氣相沉積製程(chemical vapor deposition, CVD)製程、或上述組合於P型半導體層18上形成導電材料作為閘極電極層20。另外硬遮罩22較佳包含介電材料例如但不侷限於氮化矽。
請繼續參照如第2圖至第4圖，第2圖至第4圖揭露本發明一實施例利用微影暨蝕刻圖案化閘極電極層20以形成閘極電極26之方法示意圖。如第2圖至第3圖所示，首先利用圖案化遮罩24為遮罩進行一蝕刻製程去除部分硬遮罩22以及部分閘極電極層20將閘極電極層20圖案化形成閘極電極26，其中本階段所進行的蝕刻製程較佳利用含氟氣體例如四氟化碳(CF 4)或六氟化硫(SF 6)來依序續去除部分硬遮罩22以及部分閘極電極層20的時候含氟氣體較佳與P型半導體層18反應並形成副產物(byproduct)28於P型半導體層18表面。由於副產物28較佳為含氟氣體與P型半導體層18反應而形成，因此其組成較佳為鎵(Ga)為主要成分的副產物28。
如第3圖所示，隨著蝕刻製程中的含氟氣體向下去除部分P型半導體層18，副產物28會覆蓋於被圖案化的P型半導體層18頂表面與側壁，例如閘極電極26兩側的P型半導體層18頂表面以及閘極電極26正下方的P型半導體層18側壁。值得注意的是，隨著副產物28持續增加，原本覆蓋於閘極電極26正下方P型半導體層18側壁的副產物28會向上堆積並沿著箭頭方向侵蝕P型半導體層28正上方的閘極電極26側壁，使閘極電極26側壁略為內縮並形成傾斜側壁30。
從結構上來看，整個閘極電極26在此階段較佳呈現梯形或更具體而言倒梯形的剖面，且閘極電極26底表面或底表面寬度較佳小於閘極電極26頂表面或頂表面寬度。另外傾斜側壁30與P型半導體層18頂表面之間的夾角可藉於30-70度或最佳40-60度之間。又需注意的是，隨著副產物28侵蝕閘極電極26側壁形成傾斜側壁30後原本堆積並推進至閘極電極26側壁的副產物28較佳在傾斜側壁30形成後同時消耗完畢。換句話說，經副產物28侵蝕閘極電極26形成傾斜側壁30後較佳無任何副產物28殘留於閘極電極26的側壁表面。
如第4圖所示，迨前述含氟氣體將P型半導體層18完全圖案化並暴露出兩側的阻障層16之後可再進行另一蝕刻製程完全去除剩餘的副產物28、圖案化遮罩24以及硬遮罩22並暴露出閘極電極26頂表面。之後可選擇性形成一保護層32於阻障層16上，去除閘極電極26兩側的部分保護層32形成二凹槽(圖未示)，再分別形成源極電極34與汲極電極36於閘極電極26兩側。
本實施例中的保護層32雖以單層結構為例，但不侷限於此，又可依據產品需求形成單層或單層以上例如雙層或三層的保護層32，其中保護層32可包含氧化矽、氮化矽、或氧化鋁等介電材料。另外在本實施例中，源極電極34以及汲極電極36較佳由金屬所構成，且相較於閘極電極26由蕭特基金屬所構成，源極電極34與汲極電極36較佳由歐姆接觸金屬所構成。依據本發明一實施例，閘極電極26、源極電極34及汲極電極36可各自包含金、銀、鉑、鈦、鋁、鎢、鈀或其組合。在一些實施例中，可利用電鍍製程、濺鍍製程、電阻加熱蒸鍍製程、電子束蒸鍍製程、物理氣相沉積(physical vapor deposition, PVD)製程、化學氣相沉積製程(chemical vapor deposition, CVD)製程、或上述組合於上述凹槽內形成導電材料，然後再利用單次或多次蝕刻將電極材料圖案化以形成源極電極34以及汲極電極36。至此即完成本發明一實施例之一高電子遷移率電晶體的製作。
一般而言，現行高電子遷移率電晶體中在高前向閘極偏壓(high forward gate bias)的運作下閘極電極的蕭特基金屬與下方P型半導體層之間通常會產生電荷差(potential difference)，此外在P型半導體層側壁也容易因邊際電場(fringing field)效應形成反向通道造成漏電流。為了改善此問題本發明主要利用含氟氣體圖案化閘極電極以及P型半導體層，並藉由P型半導體層側壁上副產物的堆疊來侵蝕閘極電極形成傾斜側壁。依據本發明之較佳實施例，利用此手段將閘極電極修整為約略倒梯形的形狀可有效抑制閘極電極側壁發生的漏電流並改善高溫閘極偏壓(high temperature gate bias)的狀況。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:緩衝層 16:阻障層 18:P型半導體層 20:閘極電極層 22:硬遮罩 24:圖案化遮罩 26:閘極電極 28:副產物 30:傾斜側壁 32:保護層 34:源極電極 36:汲極電極
第1圖至第4圖為本發明一實施例製作高電子遷移率電晶體之方法示意圖。
12:基底
14:緩衝層
16:阻障層
18:P型半導體層
20:閘極電極層
22:硬遮罩
24:圖案化遮罩
26:閘極電極
28:副產物
30:傾斜側壁
32:保護層
34:源極電極
36:汲極電極

Claims (14)

  1. 一種製作高電子遷移率電晶體(high electron mobility transistor, HEMT)的方法，其特徵在於，包含： 形成一緩衝層於一基底上； 形成一阻障層於該緩衝層上； 形成一P型半導體層於該阻障層上； 形成一閘極電極層於該P型半導體層上；以及 圖案化該閘極電極層以形成一閘極電極，其中該閘極電極包含一傾斜側壁。
  2. 如申請專利範圍第1項所述之方法，另包含： 進行一蝕刻製程去除部分該閘極電極層以形成一副產物於該P型半導體層表面並形成該傾斜側壁； 去除該副產物；以及 形成一源極電極以及一汲極電極於該閘極電極兩側。
  3. 如申請專利範圍第2項所述之方法，其中該蝕刻製程包含氟。
  4. 如申請專利範圍第1項所述之方法，其中該閘極電極包含梯形。
  5. 如申請專利範圍第1項所述之方法，其中該閘極電極底表面小於該閘極電極頂表面。
  6. 如申請專利範圍第1項所述之方法，其中該緩衝層包含氮化鎵(GaN)。
  7. 如申請專利範圍第1項所述之方法，其中該阻障層包含氮化鋁鎵(Al xGa 1-xN)。
  8. 如申請專利範圍第1項所述之方法，其中該P型半導體層包含P型氮化鎵。
  9. 一種高電子遷移率電晶體(high electron mobility transistor, HEMT)，其特徵在於，包含： 一緩衝層設於一基底上； 一阻障層設於該緩衝層上； 一P型半導體層設於該阻障層上；以及 一閘極電極設於該P型半導體層上，其中該閘極電極包含一傾斜側壁。
  10. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該閘極電極包含梯形。
  11. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該閘極電極底表面小於該閘極電極頂表面。
  12. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該緩衝層包含氮化鎵(GaN)。
  13. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該阻障層包含氮化鋁鎵(Al xGa 1-xN)。
  14. 如申請專利範圍第9項所述之高電子遷移率電晶體，其中該P型半導體層包含P型氮化鎵。
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