CN117672849A - 高电子迁移率晶体管及其制作方法 - Google Patents

高电子迁移率晶体管及其制作方法 Download PDF

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CN117672849A
CN117672849A CN202211108116.8A CN202211108116A CN117672849A CN 117672849 A CN117672849 A CN 117672849A CN 202211108116 A CN202211108116 A CN 202211108116A CN 117672849 A CN117672849 A CN 117672849A
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gate electrode
layer
type semiconductor
semiconductor layer
electron mobility
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叶治东
张祐嘉
陈柏瑜
王允俊
李瑞池
廖文荣
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United Microelectronics Corp
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Abstract

本发明公开一种高电子迁移率晶体管及其制作方法，其中该制作高电子迁移率晶体管(high electron mobility transistor,HEMT)的方法，主要包括先形成一缓冲层于基底上，然后形成一阻障层于该缓冲层上，形成一P型半导体层于该阻障层上，形成一栅极电极层于该P型半导体层上，再图案化该栅极电极层以形成一栅极电极，其中该栅极电极包含一倾斜侧壁。

Description

高电子迁移率晶体管及其制作方法
技术领域
本发明涉及一种高电子迁移率晶体管及其制作方法。
背景技术
以氮化镓基材料(GaN-based materials)为基础的高电子迁移率晶体管具有于电子、机械以及化学等特性上的众多优点，例如宽能隙、高击穿电压、高电子迁移率、大弹性模数(elastic modulus)、高压电与压阻系数(high piezoelectric and piezoresistivecoefficients)等与化学钝性。上述优点使氮化镓基材料可用于如高亮度发光二极管、功率开关元件、调节器、电池保护器、面板显示驱动器、通信元件等应用的元件的制作。
发明内容
本发明一实施例揭露一种制作高电子迁移率晶体管(high electron mobilitytransistor,HEMT)的方法，其主要先形成一缓冲层于基底上，然后形成一阻障层于该缓冲层上，形成一P型半导体层于该阻障层上，形成一栅极电极层于该P型半导体层上，再图案化该栅极电极层以形成一栅极电极，其中该栅极电极包含一倾斜侧壁。
附图说明
图1至图4为本发明一实施例制作高电子迁移率晶体管的方法示意图。
符号说明
12:基底
14:缓冲层
16:阻障层
18:P型半导体层
20:栅极电极层
22:硬掩模
24:图案化掩模
26:栅极电极
28:副产物
30:倾斜侧壁
32:保护层
34:源极电极
36漏极电极
具体实施方式
请参照图1至图4，图1至图4为本发明一实施例制作高电子迁移率晶体管的方法示意图。如图1所示，首先提供一基底12，例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底，其中基底12可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底12又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。
然后于基底12表面形成一选择性核晶层(nucleation layer)(图未示)以及一缓冲层14。在一实施例中，核晶层较佳包含氮化铝而缓冲层14包含III-V族半导体例如氮化镓，其厚度可介于0.5微米至10微米之间。在一实施例中，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapordeposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于基底12上形成缓冲层14。
接着可选择性于缓冲层14表面形成一非刻意掺杂(unintentionally doped)缓冲层(图未示)。在本实施例中，非刻意掺杂缓冲层较佳包含III-V族半导体，例如氮化镓或更具体而言非刻意掺杂氮化镓。在一实施例中，可利用分子束外延制作工艺(molecular-beamepitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于缓冲层14上形成非刻意掺杂缓冲层。
随后形成一阻障层16于非刻意掺杂缓冲层或缓冲层14表面。在本实施例中阻障层16较佳包含III-V族半导体例如N型氮化铝镓(AlxGa1-xN)，其中0<x<1，阻障层16较佳包含一由外延成长制作工艺所形成的外延层，且阻障层16可包含硅或锗的掺质。如同上述形成缓冲层14的方式，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phaseepitaxy,HVPE)制作工艺或上述组合于缓冲层14上形成阻障层16。
接着依序形成一P型半导体层18、一栅极电极层20、一硬掩模22以及一图案化掩模24如图案化光致抗蚀剂于阻障层16上。在一实施例中，P型半导体层18较佳包含P型氮化镓，且可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metalorganic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapordeposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于阻障层16表面形成P型半导体层18。
依据本发明一实施例，栅极电极层20较佳由萧特基金属所构成，其中栅极电极层20可包含金、银、铂、钛、铝、钨、钯或其组合。在一些实施例中，可利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapordeposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于P型半导体层18上形成导电材料作为栅极电极层20。另外硬掩模22较佳包含介电材料例如但不局限于氮化硅。
请继续参照如图2至图4，图2至图4揭露本发明一实施例利用光刻及蚀刻图案化栅极电极层20以形成栅极电极26的方法示意图。如图2至图3所示，首先利用图案化掩模24为掩模进行一蚀刻制作工艺去除部分硬掩模22以及部分栅极电极层20将栅极电极层20图案化形成栅极电极26，其中本阶段所进行的蚀刻制作工艺较佳利用含氟气体例如四氟化碳(CF4)或六氟化硫(SF6)来依序续去除部分硬掩模22以及部分栅极电极层20的时候含氟气体较佳与P型半导体层18反应并形成副产物(byproduct)28于P型半导体层18表面。由于副产物28较佳为含氟气体与P型半导体层18反应而形成，因此其组成较佳为镓(Ga)为主要成分的副产物28。
如图3所示，随着蚀刻制作工艺中的含氟气体向下去除部分P型半导体层18，副产物28会覆盖于被图案化的P型半导体层18顶表面与侧壁，例如栅极电极26两侧的P型半导体层18顶表面以及栅极电极26正下方的P型半导体层18侧壁。值得注意的是，随着副产物28持续增加，原本覆盖于栅极电极26正下方P型半导体层18侧壁的副产物28会向上堆积并沿着箭头方向侵蚀P型半导体层28正上方的栅极电极26侧壁，使栅极电极26侧壁略为内缩并形成倾斜侧壁30。
从结构上来看，整个栅极电极26在此阶段较佳呈现梯形或更具体而言倒梯形的剖面，且栅极电极26底表面或底表面宽度较佳小于栅极电极26顶表面或顶表面宽度。另外倾斜侧壁30与P型半导体层18顶表面之间的夹角可介于30度～70度或最佳40度～60度之间。又需注意的是，随着副产物28侵蚀栅极电极26侧壁形成倾斜侧壁30后原本堆积并推进至栅极电极26侧壁的副产物28较佳在倾斜侧壁30形成后同时消耗完毕。换句话说，经副产物28侵蚀栅极电极26形成倾斜侧壁30后较佳无任何副产物28残留于栅极电极26的侧壁表面。
如图4所示，迨前述含氟气体将P型半导体层18完全图案化并暴露出两侧的阻障层16之后可再进行另一蚀刻制作工艺完全去除剩余的副产物28、图案化掩模24以及硬掩模22并暴露出栅极电极26顶表面。之后可选择性形成一保护层32于阻障层16上，去除栅极电极26两侧的部分保护层32形成两个凹槽(图未示)，再分别形成源极电极34与漏极电极36于栅极电极26两侧。
本实施例中的保护层32虽以单层结构为例，但不局限于此，又可依据产品需求形成单层或单层以上例如双层或三层的保护层32，其中保护层32可包含氧化硅、氮化硅、或氧化铝等介电材料。另外在本实施例中，源极电极34以及漏极电极36较佳由金属所构成，且相较于栅极电极26由萧特基金属所构成，源极电极34与漏极电极36较佳由欧姆接触金属所构成。依据本发明一实施例，栅极电极26、源极电极34及漏极电极36可各自包含金、银、铂、钛、铝、钨、钯或其组合。在一些实施例中，可利用电镀制作工艺、溅镀制作工艺、电阻加热蒸镀制作工艺、电子束蒸镀制作工艺、物理气相沉积(physical vapor deposition,PVD)制作工艺、化学气相沉积制作工艺(chemical vapor deposition,CVD)制作工艺、或上述组合于上述凹槽内形成导电材料，然后再利用单次或多次蚀刻将电极材料图案化以形成源极电极34以及漏极电极36。至此即完成本发明一实施例的一高电子迁移率晶体管的制作。
一般而言，现行高电子迁移率晶体管中在高前向栅极偏压(high forward gatebias)的运作下栅极电极的萧特基金属与下方P型半导体层之间通常会产生电荷差(potential difference)，此外在P型半导体层侧壁也容易因边际电场(fringing field)效应形成反向沟道造成漏电流。为了改善此问题本发明主要利用含氟气体图案化栅极电极以及P型半导体层，并通过P型半导体层侧壁上副产物的堆叠来侵蚀栅极电极形成倾斜侧壁。依据本发明的优选实施例，利用此手段将栅极电极修整为约略倒梯形的形状可有效抑制栅极电极侧壁发生的漏电流并改善高温栅极偏压(high temperature gate bias)的状况。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (14)

1.一种制作高电子迁移率晶体管(high electron mobility transistor,HEMT)的方法，其特征在于，包含：
形成缓冲层于基底上；
形成阻障层于该缓冲层上；
形成P型半导体层于该阻障层上；
形成栅极电极层于该P型半导体层上；以及
图案化该栅极电极层以形成栅极电极，其中该栅极电极包含倾斜侧壁。
2.如权利要求1所述的方法，还包含：
进行蚀刻制作工艺去除部分该栅极电极层以形成副产物于该P型半导体层表面并形成该倾斜侧壁；
去除该副产物；以及
形成源极电极以及漏极电极于该栅极电极两侧。
3.如权利要求2所述的方法，其中该蚀刻制作工艺包含氟。
4.如权利要求1所述的方法，其中该栅极电极包含梯形。
5.如权利要求1所述的方法，其中该栅极电极底表面小于该栅极电极顶表面。
6.如权利要求1所述的方法，其中该缓冲层包含氮化镓(GaN)。
7.如权利要求1所述的方法，其中该阻障层包含氮化铝镓(AlxGa1-xN)。
8.如权利要求1所述的方法，其中该P型半导体层包含P型氮化镓。
9.一种高电子迁移率晶体管(high electron mobility transistor,HEMT)，其特征在于，包含：
缓冲层，设于基底上；
阻障层，设于该缓冲层上；
P型半导体层，设于该阻障层上；以及
栅极电极，设于该P型半导体层上，其中该栅极电极包含倾斜侧壁。
10.如权利要求9所述的高电子迁移率晶体管，其中该栅极电极包含梯形。
11.如权利要求9所述的高电子迁移率晶体管，其中该栅极电极底表面小于该栅极电极顶表面。
12.如权利要求9所述的高电子迁移率晶体管，其中该缓冲层包含氮化镓(GaN)。
13.如权利要求9所述的高电子迁移率晶体管，其中该阻障层包含氮化铝镓(AlxGa1-xN)。
14.如权利要求9所述的高电子迁移率晶体管，其中该P型半导体层包含P型氮化镓。
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