WO2012145871A1 - 用于保持热预算稳定的加热方法 - Google Patents

用于保持热预算稳定的加热方法 Download PDF

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Publication number
WO2012145871A1
WO2012145871A1 PCT/CN2011/001313 CN2011001313W WO2012145871A1 WO 2012145871 A1 WO2012145871 A1 WO 2012145871A1 CN 2011001313 W CN2011001313 W CN 2011001313W WO 2012145871 A1 WO2012145871 A1 WO 2012145871A1
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time
temperature
thermal budget
main process
heating method
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PCT/CN2011/001313
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English (en)
French (fr)
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李春龙
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中国科学院微电子研究所
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Priority to US13/379,242 priority Critical patent/US8926321B2/en
Publication of WO2012145871A1 publication Critical patent/WO2012145871A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a heating method for maintaining thermal budget stability. Background technique
  • the most thermal energy is derived from the heating step, such as thermal oxidation, thermal annealing, thermal diffusion, vacuum evaporation, CVD, etc., since all heating steps are typically high temperature, long heat treatments.
  • the heating process it is sometimes necessary to adjust the main process time to ensure a certain film thickness on the target.
  • thermal oxidation for the (100) crystal plane of Si, when dry oxygen oxidation is performed at a temperature of 800 ° C, when the water vapor content in the oxidant atmosphere is less than 1 ppm, the thickness of the oxide layer obtained by oxidation for 700 minutes is 300 A. Getting a thicker oxide layer takes longer and is generally linear, so it also means more thermal budget to some extent.
  • the main process is almost always the highest temperature processing step.
  • the main process is, for example, oxidation
  • the temperature varies from 800 to 1300 ° C
  • the heat treatment time is usually on the order of ten minutes, hours or ten hours.
  • the thermal annealing time is usually On the order of minutes or seconds, for low-dose damage of Sb+ implanted in Si, annealing at 300 °C can substantially eliminate defects.
  • the CVD time is usually on the order of minutes and the temperature varies from 300 to 750 °C.
  • the main process takes a long time in each step of heating in the furnace. It can be seen that thermal oxidation is the most representative of the high temperature and long process, which largely determines the thermal budget of the semiconductor process. Therefore, changing the processing time of the main process will ultimately result in a significant change in the thermal budget of the device.
  • the subsequent further processing of the wafer may cause the overall thermal energy of the wafer to exceed the need to maintain the stability of the device, that is, when the thermal budget suddenly increases, if the subsequent processing fails to flow out according to the thermal budget, it is sufficiently redundant. If it is, the device may cause the device to fail due to the out-of-control diffusion due to exceeding the total thermal budget.
  • the present invention provides a heating method for maintaining a thermal budget stabilization, comprising: raising a temperature to raise a temperature in a reaction furnace from a first temperature to a second temperature;
  • Cooling down reducing the temperature in the reaction furnace from the second temperature to the first temperature
  • the method is characterized in that the sum of the first time and the second time is a fixed constant.
  • the main process is thermal oxidation to form an oxide film.
  • the fixing constant is determined according to the main process film thickness control.
  • the first time T1 and the second time T2 can be adjusted.
  • ⁇ 1+ ⁇ 2 ( 1+ ⁇ ) ⁇
  • TO is the arithmetic mean of the time spent in the main process of different batches
  • ⁇ is the ratio of the maximum value of the time-consuming change of the main process of different batches to TO.
  • ⁇ is less than or equal to 10%.
  • the virtual process step is annealing in a ⁇ 2 atmosphere.
  • the heating process optimization method of the present invention by inserting a dummy process after the main process, the total time of the entire heating process is kept constant, which is advantageous for maintaining the thermal budget stability. Further beneficial to the stability of device performance.
  • Figure 1 is a schematic view of various conventional heating processes
  • FIGS. 2A and 2B are schematic diagrams showing the relationship between the time and temperature of the main process in the heating process before and after optimization according to the present invention. detailed description
  • Fig. 1 is a schematic view showing an example of a conventional heating process.
  • the horizontal axis represents time, specifically, the time taken for each step of the entire heating process
  • the vertical axis represents the temperature in the reactor, and the unit is °C.
  • FIG. 1 is only a schematic diagram, and the time occupied by each step is not strictly shown in proportion.
  • the specific start and end times of each step can be referred to Table 1.
  • the usual overall heating process involves the following several steps.
  • Step S01 preparation, usually represents the beginning of the heating process flow, that is, the time origin or zero point, and the timing is 0 hours, 0 minutes, and 0 seconds; at this time, the temperature in the reaction furnace is the remaining temperature in the furnace after the heat treatment of the previous batch, which is called The first temperature, the constant first temperature in the furnace in the embodiment of the present invention is, for example, 600 °C.
  • Step S02 Waiting, at this time, the control system connected to the furnace is started, waiting for input of the process parameters, generally takes 1 minute, that is, step S02 ends at 0 hours 01 minutes 0 seconds.
  • Step S03 preloading, at this time, the furnace door is opened, and the conveying device such as the robot arm sequentially takes out the wafer cassette containing the wafer to be processed from the conveyor belt and transfers it to the boat in the furnace, depending on the number of wafers and the machine.
  • step S03 in the embodiment of the present invention takes 20 minutes, that is, step 03 ends at 0. Hours 21 minutes and 0 seconds.
  • Step S04 checking, the control system detects whether the furnace door or the furnace cover is completely closed by a detecting device (such as a mechanical, electromagnetic, optical, etc.) disposed at the furnace door.
  • the detection process takes 10 seconds, that is, step S04. End at 0 hours, 21 minutes and 10 seconds.
  • Step S05 stable, due to the opening of the furnace door during loading, there is a certain disturbance in the furnace atmosphere and temperature, and step S05 is used to wait for the furnace environment to reach equilibrium again, which takes 15 minutes, that is, step S05 ends at 0 hours 36 minutes 10 second.
  • step S06 the temperature is raised.
  • the furnace temperature control system controls the heating environment of the electromagnetic coupling coil to heat the furnace environment according to the instruction input during the waiting operation in step S02, and the heating rate is, for example, 5 ° C/min, to reach the required second.
  • the heating is stopped after the temperature, and the second temperature is, for example, 920 ° C, which takes 64 minutes, that is, the step S06 ends at 1 hour, 40 minutes and 10 seconds.
  • Step S07 recovery, because heating is inevitably uneven and causing disturbance in the furnace airflow, step S07 waits for the furnace to reach equilibrium again, and at the same time, the rotation mechanism of the wafer boat in the furnace is turned on to ensure processing in all directions of the wafer during heat treatment at a later time. Evenly, step S07 takes 15 minutes, that is, step S07 ends at 1 hour 55 minutes and 10 seconds.
  • step S08 the ignition is performed, and pure oxygen or water vapor is introduced to be used as an oxygen supply material for forming silicon oxide.
  • the time consumption can be determined by the flow rate and the flow rate, for example, 1 minute, that is, the step S08 ends at 1 hour 56 minutes 10 seconds.
  • step S09 the main process, for example, thermal oxidation, can be adjusted according to the thickness of the film to be formed.
  • the film formed in the embodiment of the present invention takes, for example, 15 minutes, that is, the step S09 ends at 2 hours. In 10 seconds.
  • Step S 10 turn off the flame, turn off the inflow of pure oxygen or water vapor, and take 1 minute, ending at 2 hours, 12 minutes and 10 seconds.
  • Step S 1 1 after the o 2 is cleared, the vacuum pump is turned on to participate in the extraction of oxygen or water vapor from the furnace body. It takes 5 minutes and ends at 2 hours, 17 minutes and 10 seconds.
  • Step S12 N 2 is purged, and a chemical inert gas such as N 2 or Ar that does not react with the wafer under the process conditions is introduced to further discharge the residual reaction gas in the furnace, and the inert gas introduced at the same time is also favorable for later operation.
  • a chemical inert gas such as N 2 or Ar that does not react with the wafer under the process conditions is introduced to further discharge the residual reaction gas in the furnace, and the inert gas introduced at the same time is also favorable for later operation. Cooling treatment, because the high vacuum environment lacks gas medium heat conduction, its heat-reduction process will be very long, step S12 takes 15 minutes, ends at 2 hours, 32 minutes and 10 seconds.
  • Step S13 cooling, at this time, the furnace cooling system is turned on, and the temperature in the furnace is gradually reduced back to the initial first temperature of 600 ° C by a refrigerant medium circulation, convection or natural cooling, and the cooling speed is 2 ° C / min, It takes 160 minutes and step 12 ends at 5 hours, 12 minutes and 10 seconds.
  • Step S14 the rotation is stopped, and the rotation of the boat is stopped after the heat treatment is completed, which takes 3 minutes and ends at 5 hours, 15 minutes and 10 seconds.
  • Step S15 unloading, transporting the processed wafer in the wafer boat back to the wafer cassette by the robot arm, which is opposite to the preloading sequence, and takes the same time for 20 minutes and ends at 5 hours, 35 minutes and 10 seconds.
  • Step S16, End the control system is turned off or on standby until the next batch of wafer processing, the end process takes 5 seconds, and the entire process ends at 5 hours, 35 minutes, and 15 seconds.
  • the main process step S09 is usually adjustable.
  • the main process step S09 can be changed from a short time indicated by a solid line to a longer time indicated by a broken line, and the order of magnitude is usually a dozen. Minutes, in some cases even hours or ten hours, the resulting thermal budget changes significantly.
  • the film thicknesses of different batches may be different, or the film thickness may be the same but the material gas and temperature control may float to cause a corresponding change in processing time.
  • the time consumption of the main process S09 in different batches may fluctuate around a certain value TO, TO is called the main process time-consuming reference value, TO can be the arithmetic mean of the time consumption of these different main processes, the maximum value of the up and down floating and TO
  • the ratio can be written as ⁇ , which is referred to as the main process time adjustment factor in the present invention. Therefore, for different devices and manufacturing processes, the main process time needs to be adjusted frequently. This will cause the time of the entire heating process to change frequently, and the corresponding thermal budget will also change significantly, which is not conducive to rational optimization of process time.
  • the core of this patent is the stability of the thermal budget to maintain a specific process step. If the thermal budget is stable at the IC design stage, the thermal budget of the entire device is stable.
  • the present invention inserts a virtual process step after the main process in the heating process flow, that is, the main process S09 is split into two steps of S9A and S9B, referring to FIG. Step S9A is still used for the original main process, such as thermal oxidation.
  • the specific time of the first time T1 of the step S9A is adjusted according to the film formation speed and the required thickness. Specifically, the main process time-consuming reference value ⁇ 0 is 15 minutes, and the main process time adjustment factor ⁇ is generally less than or equal to 10%.
  • Step S9B is a virtual process step, or a pseudo process step, which is intended to control the thermal budget of the current process, that is, the total time in the furnace.
  • the specific processing can vary depending on the device configuration. Specifically, for example, an annealing step performed in an atmosphere of 1 2 , that is, a nitrogen gas is introduced into the furnace and maintained at a high temperature of the main process S9A for a certain period of time, at which time annealing assists in eliminating defects, which are filled with nitrogen gas. It does not react with the substrate silicon and thus does not cause additional device problems.
  • the virtual process step S 9 B takes the second time T2, and the specific time of T2 is determined according to the total thermal budget of the heating process and the main process time T1, that is, after T1 and T2 is a fixed constant T, the constant T is determined by the main process.
  • the film thickness control requirements are determined.
  • T1 and T2 can be determined according to the main process film thickness control requirements.
  • ⁇ 0 and ⁇ can be reasonably adjusted according to different film thicknesses and film formation rates, as long as the sum of T1 and ⁇ 2 is constant.
  • the sum of T1 and ⁇ 2 can be reasonably adjusted by the inserted virtual process step S9B and thus the entire heating process time can be determined (the remaining high temperature steps such as S06, S07, S08, S10, S11, S12, S13)
  • the time of each step is fixed for the fixed device, so that it can maintain a constant value when the main process time changes, for the subsequent thermal budget. Convenience.
  • the remaining steps are the same as those shown in Figure 1 and Table 1, and will not be described again.
  • the heating process optimization method of the present invention by inserting a dummy process after the main process, the total time of the entire heating process is kept constant, which is advantageous for maintaining the thermal budget stability, and further contributing to the stability of the device performance.

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Abstract

本发明公开了一种用于保持热预算稳定的加热方法，通过在主工序后插入一个虚拟工序，使得整个加热工艺的总时间保持不变，有利于保持热预算稳定，进一步有利于器件性能维持稳定。

Description

用于保持热预算稳定的加热方法 本申请要求了 2011年 4月 25日提交的、 申请号为 201110104354.7、 发明名称为"用于保持热预算稳定的加热方法"的中国专利申请的优先 权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件制造方法， 特别是涉及一种用于保持 热预算稳定的加热方法。 背景技术
在摩尔定律的推动下， 过去十多年来半导体工业发展非常迅速。 随着更多复杂工艺技术的开发， 对半导体制造而言， 工艺热预算的良 好控制变得越来越重要。 例如， 集成电路进入深亚微米以及纳米级之 后， 特征尺寸持续缩小， 而离子注入或扩散形成的掺杂区内的杂质离 子可能在多次热处理过程中累积获得足够的能量脱离衬底材盾的束缚 而扩散到相隔距离已减小的相邻区域内， 这往往会导致器件失效。
在半导体制造工序期间， 最多的热能来源于加热步骤， 例如热氧 化、 热退火、 热扩散、 真空蒸发、 CVD等等， 因为所有的加热步骤通 常是高温长时间的加热处理。 但是对于加热工序而言， 有时需要调整 主工艺时间以确保目标物上一定的薄膜厚度。 例如对于热氧化而言， 对于 Si的（ 100 )晶面， 在 800°C温度下进行干氧氧化时， 当氧化剂气氛 中水汽含量小于 lppm时， 氧化 700分钟得到的氧化层厚度为 300A, 要 得到更厚的氧化层则需要更长的时间， 大体上呈线性关系， 因此一定 程度上也意味着更多的热预算。
重要的是， 主工艺几乎总是温度最高的处理步骤。 例如对于制备 氧化硅而言， 主工艺例如是氧化， 温度从 800至 1300°C不等， 加热处理 时间通常是十几分钟、 小时或十数小时的量级。 而热退火时间通常是 分钟或秒量级， 对于注入 Si中 Sb+的低剂量损伤， 300°C退火即可基本 消除缺陷。 CVD时间通常是分钟量级， 温度从 300至 750°C不等。 此外， 在炉内加热的各个步骤工序中， 主工艺耗时较长。 由此可见， 热氧化 最能代表高温长时间的主工艺， 很大程度上决定了半导体工艺的热预 算。 因此， 改变主工艺的处理时间将最终显著导致器件热预算的变化。
进一步地， 热预算变化较大时， 后续对于晶片的进一步处理可能 使得晶片总体承受的热能超出保持器件稳定性的需要， 也即热预算突 增时， 若后续处理未能依照热预算流出足够冗余， 则可能造成器件因 超过总热预算而使得扩散失控最终导致器件失效。
总而言之， 需要一种能保持热预算稳定的加热工序优化方法， 以 便降低制造成本、 节省工艺时间。 发明内容
由上所述， 本发明的目的在于提供一种保持热预算稳定的加热工 序优化方法。
本发明提供了一种用于保持热预算稳定的加热方法， 包括： 升温， 将反应炉内的温度从第一温度上升至第二温度；
主工序步骤， 用于对晶片处理形成薄膜， 占用第一时间 T1 ;
虚拟工艺步骤， 占用第二时间 T2;
降温， 将反应炉内的温度从第二温度下降至第一温度；
其特征在于， 所述第一时间和第二时间之和为一固定常数。
其中， 所述主工序为热氧化形成氧化膜。 其中， 所述固定常数依 据主工序成膜厚度控制而确定。 其中， 能够调整所述第一时间 T1和第 二时间 T2。 其中， Τ1+Τ2 = ( 1+α ) χΤΟ , TO为不同批次的主工序耗时 的算术平均值， α为不同批次的主工序耗时变化最大值与 TO的比率。 其 中， α小于等于 10 %。 其中， 所述虚拟工艺步骤为在 Ν2氛围下退火。
依照本发明的加热工序优化方法， 通过在主工序后插入一个虚拟 工序， 使得整个加热工艺的总时间保持不变， 有利于保持热预算稳定， 进一步有利于器件性能维持稳定。
本发明所述目的， 以及在此未列出的其他目的， 在本申请独立权 利要求的范围内得以满足。 本发明的实施例限定在独立权利要求中， 具体特征限定在其从属权利要求中。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1为现有的加热各个工序示意图； 以及
图 2A及图 2B为依照本发明的优化前后的加热工序的主工序时间- 温度关系示意图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了保持热预算稳定的加热工序优化方法。 需要指出的是， 类似的附图标记表示类似的结构， 本申请中所用的术 语"第一"、 "第二"、 "上"、 "下"等等可用于修饰各种制造工序。 这些修 饰除非特别说明并非暗示所修饰制造工序的空间、 次序或层级关系。
图 1为现有的加热工序实例示意图。 其中， 横轴表示时间， 具体而 言代表整个加热工序各个步骤所耗费的时间， 纵轴表示反应炉内温度， 单位为 °C。 需要说明的是， 图 1仅为示意图， 各个步骤所占时间并未严 格按照比例显示， 具体的各步骤开始以及结束时间可参照表 1。
通常的整个加热工序包括以下若干步骤。
步骤 S01， 准备， 通常代表加热工序流程的开始， 也即时间原点或 零点， 计时为 0小时 0分钟 0秒； 此时反应炉内温度为上一批次热处理过 后的炉内剩余温度， 称为第一温度， 本发明所举实施例中炉内恒定的 第一温度例如为 600°C。
步骤 S02, 等待， 此时与炉相连的控制系统启动， 等待输入工艺参 数， 一般耗时 1分钟， 也即步骤 S02结束于 0小时 01分 0秒。 步骤 S03， 预装载， 此时炉门打开， 机械臂等输送装置将包含待处 理晶片的晶片盒从传送带上依次取出， 转运到炉内的晶舟上， 这一过 程取决于晶片数量以及机械操作时间， 对于每分钟能将晶片输送 100mm的机械系统而言（也即输送系统的吞吐能力为 1 OOmm/min ) , 本 发明实施例中步骤 S03耗时 20分钟， 也即步骤 03结束于 0小时 21分 0秒。
步骤 S04 , 检查， 控制系统通过设置在炉门处的检测装置（例如机 械、 电磁、 光学等传感器） 来检测炉门或炉盖是否完全关闭， 这一检 测过程耗时 10秒， 也即步骤 S04结束于 0小时 21分 10秒。
步骤 S05 , 稳定， 由于装载时炉门开启， 炉内气氛和温度存在一定 扰动， 步骤 S05用于等待使得炉内环境再次达到平衡， 耗时 15分钟， 也 即步骤 S05结束于 0小时 36分 10秒。
步骤 S06， 升温， 此时炉温控制系统依据步骤 S02等待时输入的指 令控制例如为电磁耦合线圈的加热装置对炉内环境加热， 升温速度例 如为 5 °C/min，达到所需的第二温度后停止加热，第二温度例如为 920°C， 耗时 64分钟， 也即步骤 S06结束于 1小时 40分 10秒。
步骤 S07,恢复，由于加热难免具有不均勾性和造成炉内气流扰动， 步骤 S07等待以便炉内再次达到平衡， 同时开启炉内晶舟的旋转机制， 保证稍后热处理时晶片各个方向上处理均匀， 步骤 S07耗时 15分钟， 也 即步骤 S07结束于 1小时 55分 10秒。
步骤 S08 , 点火， 此时通入纯氧或水汽， 用作形成氧化硅的供氧原 料， 耗时具体可由流量和流速决定， 例如 1分钟， 也即步骤 S08结束于 1 小时 56分 10秒。
步骤 S09, 主工序， 例如是热氧化， 所耗时间依据要形成的薄膜厚 度决定而可调整， 本发明实施例所形成的薄膜例如需要耗时 15分钟， 也即步骤 S09结束于 2小时 1 1分 10秒。
步骤 S 10， 熄火， 关闭纯氧或水汽的流入， 耗时 1分钟， 结束于 2 小时 12分 10秒。
步骤 S 1 1 , 后期 o2清除， 开启真空泵将参与氧气或水汽抽出炉体， 耗时 5分钟， 结束于 2小时 17分 10秒。
步骤 S12， N2清除， 通入 N2或 Ar等在此工艺条件下不与晶片反应 的化学惰性气体以进一步排出炉内残余反应气体， 同时通入的惰性气 体也有利于稍后要进行的降温处理， 因为高真空环境若缺乏气体媒介 导热， 其降热过程将是十分漫长的， 步骤 S12耗时 15分钟， 结束于 2小 时 32分 10秒。
步骤 S13, 降温， 此时炉体冷却系统开启， 采用制冷媒介循环、 对 流或者自然冷却等方法逐步使得炉内温度降回至初始的第一温度 600 °C, 降温速度为 2°C/min, 耗时 160分钟， 步骤 12结束于 5小时 12分 10 秒。
步骤 S14, 关停旋转， 热处理完成之后晶舟转动停止， 耗时 3分钟， 结束于 5小时 15分 10秒。
步骤 S15, 卸载，借由机械臂将晶舟中处理完成的晶片输送回晶片 盒中， 与预装载顺序相反， 耗时相同均为 20分钟， 结束于 5小时 35分 10 秒。
步骤 S16， 结束， 控制系统关闭或待机， 直至下一批次晶片处理， 结束过程耗时 5秒， 整个工艺流程结束于 5小时 35分 15秒。
以上各个步骤的时序关系如下表 1:
步骤名称 步骤耗时（时:分:秒） 工艺流程时间（时:分:秒） 准备 0:00:00 0:00:00
等待 0:01:00 0:01:00
预装载 0:20:00 0:21:00
检查 0:00:10 0:21:10
稳定 0:15:00 0:36:10
^t 、、曰 0:64:00 1:40:10
恢复 0:15:00 1:55:10
点火 0:01:00 1:56:10
主工序 （氧化） 0:15:00 2:11:10
熄火 0:01:00 2:12:10 后期 02清除 0:05:00 2 17: 10
N2清除 0: 15:00 2 32: 10
降温 1 :40:00 5 12: 10
停止旋转 0:03:00 5 15: 10
卸载 0:20:00 5 35: 10
结束 0:00:05 5 35: 15
由以上描述和图 1、 表 1可知， 通常的加热工序中， 主工序步骤 S09 通常是可调的。 例如， 参照图 2A， 依据要形成的薄膜材质、 厚度以及 工艺条件决定， 主工序步骤 S09耗时可从实线所示的较短时间变化到虚 线所示的较长时间， 其数量级通常是十几分钟， 某些情况下甚至需要 几小时或十几小时， 由此带来的热预算变化显著。 具体地， 不同批次 的成膜厚度可能不同， 或者成膜厚度相同但是原料气、 温度控制存在 浮动而使得处理时间相应改变。 不同批次下主工序 S09的耗时可能围绕 某一数值 TO上下浮动， TO称为主工序耗时基准值， TO可以是这些不同 主工序耗时的算术平均值， 上下浮动的最大值与 TO的比率可以记做 α， 在本发明中称为主工序时间调整因子。 因此， 对于不同的器件和制造 工艺而言， 需要经常调整主工序时间， 这样会使得整个加热工序的时 间经常变化， 相应的热预算也显著变化， 不利于合理优化工艺处理时 间。
本专利的核心是保持某一具体工艺处理步骤的热预算的稳定。 如 果在集成电路设计阶段， 每一步热预算都稳定了， 整个器件的热预算 也就稳定了。 为此， 本发明在加热工序流程中主工序之后插入一个虚 拟工艺步骤， 也即将主工序 S09拆分为 S9A和 S9B两个步骤， 参照图 2Β。 步骤 S9A仍用于原定的主工序， 例如热氧化， 按照图 1和表 1的实施例所 述，步骤 S9A耗时第一时间 T1的具体时间依据薄膜形成速度以及所需厚 度合理调整。 具体地， 前述主工序耗时基准值 Τ0为 15分钟， 主工序时 间调整因子 α—般小于等于 10 %。 步骤 S9B为虚拟工艺步骤， 或称伪工 艺步骤， 其用意在于控制本次加工的热预算也即在炉内的总时间， 其 具体的处理可以按照不同的器件构造而不同。 具体地， 例如为在 1^2氛 围下进行的退火步骤，也即向炉内通入氮气并维持在主工序 S9A的高温 下一定时间， 此时退火有助于消除缺陷， 其充入的氮气又不与衬底硅 反应因而不会造成额外的器件问题。 虛拟工艺步骤 S 9 B耗时第二时间 T2 , T2的具体时间依照加热工序总热预算以及主工序耗时 T1来确定， 也即 T1与 T2之后为一固定常数 T, 该常数 T由主工序成膜厚度控制要求 来决定。
可以按照主工序成膜厚度控制要求来决定 T1与 T2。 具体地， 主工 序耗时 T1和虚拟工艺耗时 Τ2满足以下条件： Τ1 +Τ2 = ( 1 +α ) χΤΟ , 其 中 TO为主工序耗时基准值， 可以是不同主工序耗时的算术平均值； α为 主工序时间调整因子， 可以是 T1相对于 TO上下浮动的最大值与 TO的比 率， 一般 α小于等于 10 %。 当主工序耗时基准值 TO为 15分钟、 主工序时 间调整因子 α为 10 %时，如果某一批次的主工序耗时 T1缩短为 14.5分钟， 则虚拟工艺耗时 Τ2为 2分钟， 如果另一批次的主工序耗时 T1增长为 16 分钟， 则虚拟工艺耗时 Τ2为 0.5分钟， 诸如此类。
此外， Τ0与 α可以按照不同的成膜厚度、 成膜速率来合理调整， 只 要能满足 T1与 Τ2之和为恒定值即可。
如此， 可以通过插入的虚拟工艺步驟 S9B来合理调整 T1与 Τ2之和 并由此确定整个加热工序时间 （其余的高温各个步骤例如 S06、 S07、 S08、 S 10、 S l l、 S 12、 S 13依照反应炉进气排气以及加热器设置而定， 对于固定的装置而言各个步骤的耗时是一定的） ， 使其当主工序时间 变化时仍能保持为一定恒定值， 为后续的热预算提供便利。 其余步骤 与图 1以及表 1所示相同， 不再遨述。
依照本发明的加热工序优化方法， 通过在主工序后插入一个虚拟 工序， 使得整个加热工艺的总时间保持不变， 有利于保持热预算稳定， 进一步有利于器件性能维持稳定。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对工艺流程做出各种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 工艺流程方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种用于保持热预算稳定的加热方法， 包括：
升温， 将反应炉内的温度从第一温度上升至第二温度；
主工序步骤， 用于对晶片处理形成薄膜， 占用第一时间 T1 ;
虚拟工艺步骤， 占用第二时间 T2;
降温， 将反应炉内的温度从第二温度下降至第一温度；
其特征在于， 所述第一时间和第二时间之和为一固定常数。
2. 如权利要求 1所述的用于保持热预算稳定的加热方法， 其中， 所述主工序为热氧化形成氧化膜。
3. 如权利要求 1所述的用于保持热预算稳定的加热方法， 其中， 所述固定常数依据主工序成膜厚度控制而确定。
4. 如权利要求 3所述的用于保持热预算稳定的加热方法， 其中， 能够调整所述第一时间 T 1和第二时间 T 2。
5. 如权利要求 4所述的用于保持热预算稳定的加热方法， 其中， Τ1+Τ2 = ( 1+α ) χΤΟ , TO为不同批次的主工序耗时的算术平均值， α为 不同批次的主工序耗时变化最大值与 TO的比率。
6. 如权利要求 5所述的用于保持热预算稳定的加热方法， 其中， α 小于等于 10 % 。
7. 如权利要求 1所述的用于保持热预算稳定的加热方法， 其中， 所述虚拟工艺步骤为在 Ν2氛围下退火。
PCT/CN2011/001313 2011-04-25 2011-08-09 用于保持热预算稳定的加热方法 WO2012145871A1 (zh)

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US6265261B1 (en) * 1999-09-15 2001-07-24 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method therefor in which a netride layer in a capacitor is formed in a shortened time period
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