WO2012137781A1 - 半導体積層体及びその製造方法、並びに半導体素子 - Google Patents

半導体積層体及びその製造方法、並びに半導体素子 Download PDF

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WO2012137781A1
WO2012137781A1 PCT/JP2012/059090 JP2012059090W WO2012137781A1 WO 2012137781 A1 WO2012137781 A1 WO 2012137781A1 JP 2012059090 W JP2012059090 W JP 2012059090W WO 2012137781 A1 WO2012137781 A1 WO 2012137781A1
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semiconductor
layer
buffer layer
aln buffer
substrate
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PCT/JP2012/059090
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English (en)
French (fr)
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慎九郎 佐藤
倉又　朗人
嘉克 森島
飯塚　和幸
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株式会社タムラ製作所
株式会社光波
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Application filed by 株式会社タムラ製作所, 株式会社光波 filed Critical 株式会社タムラ製作所
Priority to KR20137029387A priority Critical patent/KR20140030180A/ko
Priority to DE201211001618 priority patent/DE112012001618T5/de
Priority to JP2013508883A priority patent/JP5596222B2/ja
Priority to US14/110,417 priority patent/US9153648B2/en
Priority to CN201280016886.8A priority patent/CN103503148A/zh
Publication of WO2012137781A1 publication Critical patent/WO2012137781A1/ja

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    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a semiconductor laminate, a manufacturing method thereof, and a semiconductor element.
  • Patent Document 1 a semiconductor element including a semiconductor laminate including a Ga 2 O 3 substrate, an AlN buffer layer, and a GaN layer is known (see, for example, Patent Document 1).
  • the AlN buffer layer is formed to a thickness of 10 to 30 nm by growing an AlN crystal on a Ga 2 O 3 substrate.
  • the GaN layer is formed by growing a GaN crystal on the AlN buffer layer, and contains Si as a donor.
  • an object of the present invention is to provide a semiconductor laminate having a low electrical resistance in the thickness direction, a method for manufacturing the same, and a semiconductor element including the semiconductor laminate.
  • One embodiment of the present invention provides a semiconductor stacked body of [1] to [9], a [10] semiconductor element, and a method of manufacturing a semiconductor stacked body of [11] to [13] in order to achieve the above object. To do.
  • a Ga 2 O 3 substrate whose main surface is a plane on which oxygen is arranged in a hexagonal lattice, an AlN buffer layer on the Ga 2 O 3 substrate, and a nitride semiconductor layer on the AlN buffer layer Semiconductor stack.
  • a Ga 2 O 3 substrate whose main surface is a plane on which oxygen is arranged in a hexagonal lattice, an AlN buffer layer on the Ga 2 O 3 substrate, and a nitride semiconductor layer on the AlN buffer layer
  • a semiconductor element including a semiconductor stacked body and energized in a thickness direction of the semiconductor stacked body.
  • a step of forming an AlN buffer layer by epitaxially growing an AlN crystal under a temperature condition of 500 ° C. or less on a Ga 2 O 3 substrate whose main surface is a plane on which oxygen is arranged in a hexagonal lattice, and the AlN buffer layer And a step of growing a nitride semiconductor crystal thereon to form a nitride semiconductor layer.
  • the present invention it is possible to provide a semiconductor stacked body having a low electrical resistance in the thickness direction, a method for manufacturing the same, and a semiconductor element including the semiconductor stacked body.
  • a semiconductor stacked body having a low electrical resistance in the thickness direction which is composed of a Ga 2 O 3 substrate, an AlN buffer layer, and a nitride semiconductor layer such as a GaN layer.
  • the inventors have formed an AlN buffer layer by epitaxially growing an AlN crystal on a Ga 2 O 3 substrate having a specific surface as a main surface, so that even if the AlN buffer layer is thin, the surface is specular. It has been found that nitride semiconductor crystals such as GaN crystals can be epitaxially grown. By reducing the thickness of the AlN buffer layer, the electrical resistance in the thickness direction of the semiconductor stacked body can be greatly reduced.
  • a high-performance semiconductor element can be formed by using a semiconductor stacked body having a low electric resistance in the thickness direction.
  • FIG. 1A is a cross-sectional view of the semiconductor stacked body according to the first embodiment.
  • the semiconductor stacked body 1 includes a Ga 2 O 3 substrate 2, an AlN buffer layer 3, and a nitride semiconductor layer 4.
  • the Ga 2 O 3 substrate 2 is made of ⁇ -Ga 2 O 3 single crystal.
  • the Ga 2 O 3 substrate 2 is a substrate whose principal surface is a surface in which oxygen is arranged in a hexagonal lattice, that is, any one of (101), ( ⁇ 201), (301), and (3-10). .
  • the AlN buffer layer 3 is thin (for example, 10 nm or less)
  • a nitride semiconductor crystal having a flat surface can be grown on the AlN buffer layer 3 to form the nitride semiconductor layer 4.
  • the main surface of the Ga 2 O 3 substrate 2 is more preferably (101).
  • the GaN crystal epitaxially grown on the AlN buffer layer grows in a hexagonal hillock shape.
  • the crystal surface does not become a mirror surface.
  • the AlN buffer layer 3 is formed by epitaxially growing an AlN crystal on the Ga 2 O 3 substrate 2 by MOCVD (Metal Organic Chemical Vapor Deposition) method or the like.
  • the growth temperature of the AlN crystal is 350 to 600 ° C., and particularly preferably 380 to 500 ° C.
  • the thickness of the AlN buffer layer 3 is 1 to 5 nm (1 nm or more and 5 nm or less), more preferably 2 to 3 nm.
  • a nitride semiconductor crystal such as a GaN crystal constituting the nitride semiconductor layer 4 grows in a hexagonal hillock shape, and the surface does not become a mirror surface.
  • the electrical resistance in the thickness direction of the semiconductor stacked body 1 increases.
  • the thickness is 2 to 3 nm, the electrical resistance in the thickness direction of the semiconductor stacked body 1 is low, and the surface of the nitride semiconductor crystal grown on the AlN buffer layer 3 becomes a mirror surface relatively easily.
  • the crystal quality of the nitride semiconductor layer 4 is improved as the thickness of the AlN buffer layer 3 is reduced.
  • the nitride semiconductor layer 4 having a sufficient crystal quality can be formed.
  • the nitride semiconductor layer 4 is formed by epitaxially growing a nitride semiconductor crystal such as a GaN crystal on the AlN buffer layer 3 while adding a conductivity type impurity such as Si on the AlN buffer layer 3 by MOCVD or the like.
  • a nitride semiconductor crystal such as a GaN crystal
  • the growth temperature is, for example, 800 to 1100 ° C.
  • the thickness of the nitride semiconductor layer 4 is 2 ⁇ m, for example.
  • the Si concentration of the nitride semiconductor layer 4 is, for example, 2 ⁇ 10 18 / cm 3 .
  • the nitride semiconductor layer 4 of the semiconductor stacked body 1 may include a Si high concentration region 4a in the vicinity of the surface on the AlN buffer layer 3 side.
  • the electrical resistance in the thickness direction of the semiconductor stacked body 1 can be further reduced.
  • the Si high concentration region 4 a is formed by increasing the amount of Si added in the initial stage of growth of the nitride semiconductor crystal on the AlN buffer layer 3.
  • the Si concentration in the high Si concentration region 4a is higher than the Si concentration in the other regions 4b.
  • the Si concentration in the Si high concentration region 4a is 5 ⁇ 10 18 / cm 3 or more, and particularly preferably 1 ⁇ 10 19 / cm 3 or more.
  • the thickness of the Si high concentration region 4a is preferably 2 nm or more.
  • FIG. 2 is a cross-sectional view of a vertical FET, which is a semiconductor element according to the second embodiment.
  • the vertical FET 10 includes a semiconductor laminate 1 including a Ga 2 O 3 substrate 2, an AlN buffer layer 3, and an n + -GaN layer 15 that is a nitride semiconductor layer, and a surface of the n + -GaN layer 15 (in FIG. 2).
  • the GaN-based vertical FET 14 formed on the upper surface), the gate electrode 11 and the source electrode 12 formed on the GaN-based vertical FET 14, and the surface of the Ga 2 O 3 substrate 2 (the lower side in FIG. 2)
  • a drain electrode 13 formed on the surface).
  • the vertical FET 10 is an example of a vertical FET that can be formed using the semiconductor stacked body 1.
  • a vertical FET having a MIS (Metal Insulator Semiconductor) gate structure including the semiconductor multilayer body 1 of the first embodiment will be described.
  • FIG. 3 is a cross-sectional view of a vertical FET which is a semiconductor element according to the third embodiment.
  • the vertical FET 20 includes a semiconductor laminate 1 including a Ga 2 O 3 substrate 2, an AlN buffer layer 3, and a nitride semiconductor layer 4, and a p formed by introducing a p-type impurity into the nitride semiconductor layer 4. + Region 25, Al 0.2 Ga 0.8 N layer 26 formed on the surface of nitride semiconductor layer 4 (upper surface in FIG.
  • n + region 27 formed by introducing an n-type impurity such as Si into the gate electrode 21, a gate electrode 21 formed on the Al 0.2 Ga 0.8 N layer 26 via a gate insulating film 24, and n Source electrode 22 connected to + region 27 and p + region 25 and drain electrode 23 formed on the surface of Ga 2 O 3 substrate 2 (the lower surface in FIG. 3).
  • the thickness of the nitride semiconductor layer 4 is 6 ⁇ m, and the Si concentration is 1 ⁇ 10 18 / cm 3 .
  • the thickness of the p + region 25 is 1 ⁇ m, and the concentration of the p-type impurity is 1 ⁇ 10 18 / cm 3 .
  • the Al 0.2 Ga 0.8 N layer 26 does not contain impurities.
  • the source electrode 22 and the drain electrode 23 are made of a laminate of a Ti film and an Al film, for example.
  • the gate electrode 21 and the gate insulating film 24 are made of, for example, Al and SiO 2 , respectively.
  • the vertical FET 20 is an example of a vertical FET having a MIS gate structure that can be formed using the semiconductor stacked body 1.
  • FIG. 4 is a cross-sectional view of a vertical FET, which is a semiconductor element according to the fourth embodiment.
  • the vertical FET 30 is stacked on the semiconductor stacked body 1 including the Ga 2 O 3 substrate 2, the AlN buffer layer 3, and the nitride semiconductor layer 4, and the surface of the nitride semiconductor layer 4 (upper surface in FIG. 4).
  • a drain electrode 33 formed on the surface (the lower surface in FIG. 4).
  • the thickness of the nitride semiconductor layer 4 is 6 ⁇ m, and the Si concentration is 1 ⁇ 10 16 / cm 3 .
  • the thickness of the p + -GaN layer 34 is 1 ⁇ m, and the concentration of the p-type impurity is 1 ⁇ 10 18 / cm 3 .
  • the thickness of the n + -GaN layer 35 is 200 nm, and the concentration of the n-type impurity is 1 ⁇ 10 18 / cm 3 .
  • the GaN layer 36 does not contain impurities and has a thickness of, for example, 100 nm.
  • the Al 0.2 Ga 0.8 N layer 37 does not contain impurities and has a thickness of, for example, 30 nm.
  • the source electrode 32 and the drain electrode 33 are made of, for example, a laminate of a Ti film and an Al film.
  • the gate electrode 31 is made of, for example, a stacked body of a Ni film and an Au film.
  • the vertical FET 30 is an example of a vertical FET having a Schottky gate structure that can be formed using the semiconductor stacked body 1.
  • FIG. 5 is a cross-sectional view of a vertical FET, which is a semiconductor element according to the fifth embodiment.
  • the vertical FET 40 is formed on the semiconductor stacked body 1 including the Ga 2 O 3 substrate 2, the AlN buffer layer 3, and the nitride semiconductor layer 4, and the surface of the nitride semiconductor layer 4 (upper surface in FIG. 5). and n - and -GaN layer 44, n - a gate electrode 41 formed on the flat portion of the -GaN layer 44, n - formed through the n + -InAlGaN contact layer 45 on the convex portion of the -GaN layer 44 Source electrode 42 and a drain electrode 43 formed on the surface of Ga 2 O 3 substrate 2 (the lower surface in FIG. 5).
  • the thickness of the nitride semiconductor layer 4 is 6 ⁇ m, and the Si concentration is 1 ⁇ 10 18 / cm 3 .
  • the thickness of the flat portion of the n ⁇ -GaN layer 44 is 3 ⁇ m, and the concentration of the n-type impurity is 1 ⁇ 10 16 / cm 3 .
  • the source electrode 42 is made of, for example, WSi.
  • the drain electrode 43 is made of, for example, a laminate of a Ti film and an Al film.
  • the gate electrode 41 is made of, for example, PdSi.
  • the vertical FET 40 is an example of a vertical FET having a Schottky gate structure that can be formed using the semiconductor stacked body 1.
  • HBT heterojunction bipolar transistor
  • FIG. 6 is a cross-sectional view of an HBT that is a semiconductor element according to the sixth embodiment.
  • the HBT 50 includes a semiconductor stacked body 1 including a Ga 2 O 3 substrate 2, an AlN buffer layer 3, and a nitride semiconductor layer 4, and n stacked on the surface of the nitride semiconductor layer 4 (upper surface in FIG. 6).
  • n is stacked on p + -GaN layer 55 + -Al 0.1 Ga 0.9 n layer 56 and n + -GaN layer 57, p + Formed on the base electrode 51 formed on the ⁇ GaN layer 55, the emitter electrode 52 formed on the n + -GaN layer 57, and the surface of Ga 2 O 3 substrate 2 (the lower surface in FIG. 6).
  • Collector electrode 53 is
  • the thickness of the nitride semiconductor layer 4 is 4 ⁇ m, and the Si concentration is 1 ⁇ 10 18 / cm 3 .
  • the thickness of the n ⁇ -GaN layer 54 is 2 ⁇ m and the concentration of the n-type impurity is 1 ⁇ 10 16 / cm 3 .
  • the thickness of the p + -GaN layer 55 is 100 nm, and the concentration of the p-type impurity is 1 ⁇ 10 18 / cm 3 .
  • the thickness of the n + -Al 0.1 Ga 0.9 N layer 56 is 500 nm, and the concentration of n-type impurities is 1 ⁇ 10 18 / cm 3 .
  • the thickness of the n + -GaN layer 57 is 1 ⁇ m, and the concentration of the n-type impurity is 1 ⁇ 10 18 / cm 3 .
  • the emitter electrode 52 is made of, for example, a laminate of a Ti film and an Al film.
  • the collector electrode 53 is made of, for example, a laminate of a Ti film and an Au film.
  • the base electrode 51 is made of, for example, a stacked body of a Ni film and an Au film.
  • the HBT 50 is an example of a heterojunction bipolar transistor that can be formed using the semiconductor stacked body 1.
  • a Schottky barrier diode (SBD) including the semiconductor multilayer body 1 of the first embodiment will be described.
  • FIG. 7 is a cross-sectional view of an SBD that is a semiconductor element according to the seventh embodiment.
  • the SBD 60 is formed on the semiconductor stacked body 1 including the Ga 2 O 3 substrate 2, the AlN buffer layer 3, and the nitride semiconductor layer 4, and the surface of the nitride semiconductor layer 4 (upper surface in FIG. 7).
  • the thickness of the nitride semiconductor layer 4 is 6 ⁇ m, and the Si concentration is 1 ⁇ 10 18 / cm 3 .
  • the thickness of the n ⁇ -GaN layer 63 is 7 ⁇ m, and the concentration of the n-type impurity is 1 ⁇ 10 16 / cm 3 .
  • the anode electrode 61 is made of, for example, Au.
  • the cathode electrode 62 is made of, for example, a laminate of a Ti film and an Au film.
  • the SBD 60 is an example of a Schottky barrier diode that can be formed using the semiconductor stacked body 1.
  • LED light emitting diode
  • FIG. 8 is a cross-sectional view of an LED which is a semiconductor element according to the eighth embodiment.
  • the LED 70 emits light that is stacked on the semiconductor stacked body 1 including the Ga 2 O 3 substrate 2, the AlN buffer layer 3, and the nitride semiconductor layer 4, and on the surface of the nitride semiconductor layer 4 (upper surface in FIG. 8).
  • an n-electrode 72 formed on the substrate is stacked on the semiconductor stacked body 1 including the Ga 2 O 3 substrate 2, the AlN buffer layer 3, and the nitride semiconductor layer 4, and on the surface of the nitride semiconductor layer 4 (upper surface in FIG. 8).
  • the thickness of the nitride semiconductor layer 4 is 5 ⁇ m, and the Si concentration is 1 ⁇ 10 18 / cm 3 .
  • the nitride semiconductor layer 4 functions as an n-type cladding layer.
  • the light emitting layer 73 includes three pairs of multiple quantum well structures composed of a GaN crystal having a thickness of 8 nm and an InGaN crystal having a thickness of 2 nm.
  • the p-type cladding layer 74 is made of a GaN crystal having an Mg concentration of 5.0 ⁇ 10 19 / cm 3 and has a thickness of 150 nm.
  • the p-type contact layer 75 is made of a GaN crystal having an Mg concentration of 1.5 ⁇ 10 20 / cm 3 and has a thickness of 10 nm.
  • the LED 70 is an example of a light emitting diode that can be formed using the semiconductor laminate 1.
  • a surface on which oxygen is arranged in a hexagonal lattice that is, a surface having any one of (101), ( ⁇ 201), (301), and (3-10) as a main surface.
  • the Si high concentration region 4 a having a Si concentration of 5 ⁇ 10 18 / cm 3 or more in the nitride semiconductor layer 4 can be further reduced. It can. This is considered to be due to the fact that by forming the Si high concentration region 4a having a high Si concentration, electrons tunnel through the potential barrier at the heterointerface, and current flows easily.
  • the electrical resistance in the thickness direction of the semiconductor stacked body can be further reduced.
  • a high-performance vertical semiconductor is formed. An element can be obtained.
  • the semiconductor laminate 1 according to the present embodiment was evaluated.
  • Example 1 a plurality of different semiconductor stacked bodies 1 are formed within the range of 0.5 to 32 nm in thickness of the AlN buffer layer 3, and the thickness of the AlN buffer layer 3 and the thickness direction of the semiconductor stacked body 1 are The relationship of electrical resistance was investigated.
  • the formation process of each semiconductor laminated body 1 is as follows.
  • the Ga 2 O 3 substrate 2 whose main surface is (101) was subjected to organic cleaning and acid cleaning, and then placed in an MOCVD apparatus.
  • the surface of the substrate was nitrided in an ammonia (NH 3 ) atmosphere diluted with nitrogen at a substrate temperature of 550 ° C.
  • the substrate temperature was set to 450 ° C., and trimethylaluminum (TMA) and NH 3 were allowed to flow into the furnace to grow AlN crystals, thereby forming an AlN buffer layer 3 which is a low-temperature AlN buffer layer.
  • TMA trimethylaluminum
  • NH 3 trimethylaluminum
  • the furnace atmosphere is switched to hydrogen, and trimethylgallium (TMG), NH 3 and monosilane (MtSiH 3 ) are flowed into the furnace, and the Si concentration is 2.0 ⁇ 10 18 /
  • TMG trimethylgallium
  • NH 3 trimethylgallium
  • MtSiH 3 monosilane
  • the Si concentration is 2.0 ⁇ 10 18 /
  • a GaN crystal of cm 3 was grown to form a nitride semiconductor layer 4 having a thickness of 2 ⁇ m.
  • electrodes were formed on the surfaces of the Ga 2 O 3 substrate 2 and the nitride semiconductor layer 4 manufactured by the above steps. Then, a voltage was applied between the electrodes, and a voltage drop when the current density was 220 A / cm 2 was measured.
  • FIG. 9 is a graph showing the relationship between the thickness of the AlN buffer layer and the voltage drop when the current density is 220 A / cm 2 .
  • the thinner the thickness of the AlN buffer layer 3 is the smaller the voltage drop is, that is, the electric resistance in the thickness direction of the semiconductor stacked body 1 is lower.
  • the voltage drop is as small as 0.5V.
  • the voltage drop is 0.6 V or less, a high-performance semiconductor element can be manufactured using the semiconductor stacked body 1.
  • the crystal quality of the nitride semiconductor layer 4 made of the GaN crystal manufactured by the above process was evaluated using an X-ray diffractometer. Measurement was performed on the (002) plane and the (101) plane of the GaN crystal constituting the nitride semiconductor layer 4.
  • FIG. 10 is a graph showing the relationship between the thickness of the AlN buffer layer and the half width of the rocking curve of X-ray diffraction.
  • FIG. 10 shows that in both the measurement results for the (002) plane and the (101) plane, the half width is smaller and the crystal quality is higher as the thickness of the AlN buffer layer 3 is smaller.
  • Example 2 the LED70 of the eighth embodiment is formed, and measuring the voltage drop V F forward.
  • an n-type ⁇ -Ga 2 O 3 substrate to which Si was added was prepared as a Ga 2 O 3 substrate 2.
  • the thickness of the ⁇ -Ga 2 O 3 substrate is 400 ⁇ m, and the main surface is (101).
  • an AlN buffer layer 3 was formed on the ⁇ -Ga 2 O 3 substrate by growing 2 nm of AlN crystal at a growth temperature of 450 ° C. using an MOCVD apparatus.
  • a GaN crystal having an Si concentration of 1.0 ⁇ 10 18 / cm 3 was grown to 5 ⁇ m to form a nitride semiconductor layer 4 as an n-type cladding layer.
  • three pairs of multiple quantum well structures composed of a GaN crystal having a thickness of 8 nm and an InGaN crystal having a thickness of 2 nm were formed at a growth temperature of 750 ° C., and a light emitting layer 73 was formed by further growing the GaN crystal by 10 nm.
  • a GaN crystal having an Mg concentration of 5.0 ⁇ 10 19 / cm 3 at a growth temperature of 1000 ° C. was grown to 150 nm to form a p-type cladding layer 74.
  • a GaN crystal having an Mg concentration of 1.5 ⁇ 10 20 / cm 3 was grown to 10 nm at a growth temperature of 1000 ° C., and a p-type contact layer 75 was formed.
  • TMG trimethylgallium
  • TMI trimethylindium
  • SiH 3 CH 3 monomethylsilane
  • Cp2Mg cyclopentadienylmagnesium
  • N source NH 3 ammonia
  • the surface of the LED epitaxial wafer produced as described above was etched from the p-type contact layer 75 side to a position deeper than the light emitting layer 73 using an ICP-RIE apparatus to form a mesa shape.
  • a SiO 2 film was formed on the side surface of the light emitting layer 73 using a sputtering apparatus.
  • electrodes that are ohmic-bonded were formed on the p-type contact layer 75 and the Ga 2 O 3 substrate 2 using a vapor deposition device, and an LED 70 having a light extraction surface on the Ga 2 O 3 substrate 2 side was obtained.
  • an LED having an AlN buffer layer 3 with a thickness of 20 nm was formed.

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Abstract

【課題】厚さ方向の電気抵抗が低い半導体積層体及びその製造方法、並びにその半導体積層体を含む半導体素子を提供する。 【解決手段】酸素が六角格子配置された面を主面とするＧａ２Ｏ３基板２と、Ｇａ２Ｏ３基板２上のＡｌＮバッファ層３と、ＡｌＮバッファ層３上の窒化物半導体層４と、を含む半導体積層体１を提供する。

Description

半導体積層体及びその製造方法、並びに半導体素子
　本発明は、半導体積層体及びその製造方法、並びに半導体素子に関する。
　従来、Ｇａ２Ｏ３基板、ＡｌＮバッファ層、及びＧａＮ層からなる半導体積層体を含む半導体素子が知られている（例えば、特許文献１参照）。特許文献１によれば、ＡｌＮバッファ層はＧａ２Ｏ３基板上にＡｌＮ結晶を成長させることにより、１０～３０ｎｍの厚さに形成される。また、ＧａＮ層はＡｌＮバッファ層上にＧａＮ結晶を成長させることにより形成され、ドナーとしてＳｉを含む。
特開２００６－３１０７６５号公報
　特許文献１の半導体素子等の、通電方向が縦方向である縦型の素子においては、半導体積層体の厚さ方向の電気抵抗の低減が重要である。
　したがって、本発明の目的は、厚さ方向の電気抵抗が低い半導体積層体及びその製造方法、並びにその半導体積層体を含む半導体素子を提供することにある。
　本発明の一態様は、上記目的を達成するために、［１］～［９］の半導体積層体、［１０］半導体素子、及び［１１］～［１３］の半導体積層体の製造方法を提供する。
［１］酸素が六角格子配置された面を主面とするＧａ２Ｏ３基板と、前記Ｇａ２Ｏ３基板上のＡｌＮバッファ層と、前記ＡｌＮバッファ層上の窒化物半導体層と、を含む半導体積層体。
［２］前記Ｇａ２Ｏ３基板の前記主面は、（１０１）、（－２０１）、（３０１）、（３－１０）のいずれかの面である、前記［１］に記載の半導体積層体。
［３］前記Ｇａ２Ｏ３基板の前記主面は、（１０１）である、前記［２］に記載の半導体積層体。
［４］前記ＡｌＮバッファ層の厚さは１ｎｍ以上５ｎｍ以下である、前記［１］～［３］のいずれか１つに記載の半導体積層体。
［５］前記ＡｌＮバッファ層の厚さは２ｎｍ以上３ｎｍ以下である、前記［４］に記載の半導体積層体。
［６］前記窒化物半導体層はＧａＮ層である、前記［１］に記載の半導体積層体。
［７］厚さ方向の電圧降下が０．６Ｖ以下である、前記［１］に記載の半導体積層体。
［８］前記窒化物半導体層は、前記ＡｌＮバッファ層側の一部の領域にＳｉ濃度が５×１０１８／ｃｍ３以上であるＳｉ高濃度領域を有する、前記［１］に記載の半導体積層体。
［９］前記Ｓｉ高濃度領域の厚さが２ｎｍ以上である、前記［８］に記載の半導体積層体。
［１０］酸素が六角格子配置された面を主面とするＧａ２Ｏ３基板と、前記Ｇａ２Ｏ３基板上のＡｌＮバッファ層と、前記ＡｌＮバッファ層上の窒化物半導体層と、を含む半導体積層体を含み、前記半導体積層体の厚さ方向に通電する、半導体素子。
［１１］酸素が六角格子配置された面を主面とするＧａ２Ｏ３基板上に、５００℃以下の温度条件でＡｌＮ結晶をエピタキシャル成長させてＡｌＮバッファ層を形成する工程と、前記ＡｌＮバッファ層上に窒化物半導体結晶を成長させて窒化物半導体層を形成する工程と、を含む半導体積層体の製造方法。
［１２］前記ＡｌＮバッファ層は１ｎｍ以上５ｎｍ以下の厚さに形成される、前記［１１］に記載の半導体積層体の製造方法。
［１３］前記窒化物半導体結晶はＧａＮ結晶である、前記［１１］又は［１２］に記載の半導体積層体の製造方法。
　本発明によれば、厚さ方向の電気抵抗が低い半導体積層体及びその製造方法、並びにその半導体積層体を含む半導体素子を提供することができる。
第１の実施の形態に係る半導体積層体の断面図 第１の実施の形態に係る半導体積層体の断面図 第２の実施の形態に係る縦型ＦＥＴの断面図 第３の実施の形態に係る縦型ＦＥＴの断面図 第４の実施の形態に係る縦型ＦＥＴの断面図 第５の実施の形態に係る縦型ＦＥＴの断面図 第６の実施の形態に係るＨＢＴの断面図 第７の実施の形態に係るＳＢＤの断面図 第８の実施の形態に係るＬＥＤの断面図 実施例に係るＡｌＮバッファ層の厚さと電圧降下との関係を表すグラフ 実施例に係るＡｌＮバッファ層の厚さとエックス線回折のロッキングカーブの半値幅との関係を表すグラフ
　本実施の形態によれば、Ｇａ２Ｏ３基板、ＡｌＮバッファ層、及びＧａＮ層等の窒化物半導体層からなる、厚さ方向の電気抵抗が低い半導体積層体を形成することができる。本発明者等は、特定の面を主面とするＧａ２Ｏ３基板上にＡｌＮ結晶をエピタキシャル成長させてＡｌＮバッファ層を形成することにより、ＡｌＮバッファ層が薄い場合であっても、表面が鏡面であるＧａＮ結晶等の窒化物半導体結晶をエピタキシャル成長させることができることを見いだした。ＡｌＮバッファ層を薄くすることにより、半導体積層体の厚さ方向の電気抵抗を大きく低減することができる。
　また、本実施の形態によれば、厚さ方向の電気抵抗が低い半導体積層体を用いることにより、高性能の半導体素子を形成することができる。以下、その実施の形態の一例について詳細に説明する。
〔第１の実施の形態〕
　図１Ａは、第１の実施の形態に係る半導体積層体の断面図である。半導体積層体１は、Ｇａ２Ｏ３基板２と、ＡｌＮバッファ層３と、窒化物半導体層４を含む。
　Ｇａ２Ｏ３基板２は、β－Ｇａ２Ｏ３単結晶からなる。Ｇａ２Ｏ３基板２は、酸素が六角格子配置された面、すなわち、（１０１）、（－２０１）、（３０１）、（３－１０）のいずれかの面を主面とする基板である。この場合、ＡｌＮバッファ層３が薄い（例えば１０ｎｍ以下）場合であっても、表面が平坦な窒化物半導体結晶をＡｌＮバッファ層３上に成長させ、窒化物半導体層４を形成することができる。特に、Ｇａ２Ｏ３基板２の主面は（１０１）であることがより好ましい。
　なお、上記の面以外の面、例えば（１００）、を主面とするＧａ２Ｏ３基板上に薄いＡｌＮバッファ層を形成すると、ＡｌＮバッファ層上にエピタキシャル成長させるＧａＮ結晶は六角ヒロック状に成長し、結晶表面が鏡面にならない。
　ＡｌＮバッファ層３は、ＭＯＣＶＤ（Metal Organic Chemical Vapor Deposition）法等により、Ｇａ２Ｏ３基板２上にＡｌＮ結晶をエピタキシャル成長させることにより形成される。ＡｌＮ結晶の成長温度は、３５０～６００℃であり、特に、３８０～５００℃であることが好ましい。
　ＡｌＮバッファ層３の厚さは、１～５ｎｍ（１ｎｍ以上、５ｎｍ以下）であり、より好ましくは２～３ｎｍである。厚さが１ｎｍ未満の場合は、窒化物半導体層４を構成するＧａＮ結晶等の窒化物半導体結晶は六角ヒロック状に成長し、表面が鏡面にならない。また、厚さが５ｎｍを超える場合は、半導体積層体１の厚さ方向の電気抵抗が大きくなる。厚さが２～３ｎｍである場合、半導体積層体１の厚さ方向の電気抵抗が低く、かつＡｌＮバッファ層３上に成長する窒化物半導体結晶の表面が比較的容易に鏡面になる。
　また、ＡｌＮバッファ層３の厚さが薄いほど、窒化物半導体層４の結晶品質が向上する。例えば、ＡｌＮバッファ層３の厚さは、１～５ｎｍである場合には、十分な結晶品質の窒化物半導体層４を形成することができる。
　窒化物半導体層４は、ＭＯＣＶＤ法等により、ＡｌＮバッファ層３上にＧａＮ結晶等の窒化物半導体結晶をＳｉ等の導電型不純物を添加しつつエピタキシャル成長させることにより形成される。窒化物半導体結晶としてＧａＮ結晶を用いる場合、その成長温度は、例えば、８００～１１００℃である。窒化物半導体層４の厚さは、例えば、２μｍである。窒化物半導体層４のＳｉ濃度は、例えば、２×１０１８／ｃｍ３である。
　また、図１Ｂに示されるように、半導体積層体１の窒化物半導体層４は、ＡｌＮバッファ層３側の表面近傍にＳｉ高濃度領域４ａを含んでもよい。Ｓｉ高濃度領域４ａが窒化物半導体層４中に形成されることにより、半導体積層体１の厚さ方向の電気抵抗をより低減することができる。
　Ｓｉ高濃度領域４ａは、ＡｌＮバッファ層３上での窒化物半導体結晶の成長の初期段階において、Ｓｉの添加量を大きくすることにより形成される。
　Ｓｉ高濃度領域４ａのＳｉ濃度は、その他の領域４ｂのＳｉ濃度よりも高い。Ｓｉ高濃度領域４ａのＳｉ濃度は、５×１０１８／ｃｍ３以上であり、特に、１×１０１９／ｃｍ３以上であることが好ましい。
　また、半導体積層体１の厚さ方向の電気抵抗をより低減するために、Ｓｉ高濃度領域４ａの厚さは、２ｎｍ以上であることが好ましい。
〔第２の実施の形態〕
　第２の実施の形態として、第１の実施の形態の半導体積層体１を含む縦型ＦＥＴ（Field effect transistor）について述べる。
　図２は、第２の実施の形態に係る半導体素子である縦型ＦＥＴの断面図である。縦型ＦＥＴ１０は、Ｇａ２Ｏ３基板２、ＡｌＮバッファ層３、及び窒化物半導体層であるｎ＋－ＧａＮ層１５を含む半導体積層体１と、ｎ＋－ＧａＮ層１５の表面（図２における上側の面）上に形成されたＧａＮ系縦型ＦＥＴ１４と、ＧａＮ系縦型ＦＥＴ１４上に形成されたゲート電極１１及びソース電極１２と、Ｇａ２Ｏ３基板２の表面（図２における下側の面）上に形成されたドレイン電極１３と、を含む。
　なお、縦型ＦＥＴ１０は、半導体積層体１を用いて形成することのできる縦型ＦＥＴの一例である。
〔第３の実施の形態〕
　第３の実施の形態として、第１の実施の形態の半導体積層体１を含むＭＩＳ（Metal Insulator Semiconductor）ゲート構造の縦型ＦＥＴについて述べる。
　図３は、第３の実施の形態に係る半導体素子である縦型ＦＥＴの断面図である。縦型ＦＥＴ２０は、Ｇａ２Ｏ３基板２、ＡｌＮバッファ層３、及び窒化物半導体層４を含む半導体積層体１と、窒化物半導体層４中にｐ型不純物を導入することにより形成されたｐ＋領域２５と、窒化物半導体層４の表面（図３における上側の面）上に形成されたＡｌ０．２Ｇａ０．８Ｎ層２６と、Ａｌ０．２Ｇａ０．８Ｎ層２６中にＳｉ等のｎ型不純物を導入することにより形成されたｎ＋領域２７と、Ａｌ０．２Ｇａ０．８Ｎ層２６上にゲート絶縁膜２４を介して形成されたゲート電極２１と、ｎ＋領域２７及びｐ＋領域２５に接続されたソース電極２２と、Ｇａ２Ｏ３基板２の表面（図３における下側の面）上に形成されたドレイン電極２３と、を含む。
　ここで、例えば、窒化物半導体層４の厚さは６μｍであり、Ｓｉ濃度は１×１０１８／ｃｍ３である。また、例えば、ｐ＋領域２５の厚さは１μｍであり、ｐ型不純物の濃度は１×１０１８／ｃｍ３である。Ａｌ０．２Ｇａ０．８Ｎ層２６は不純物を含まない。ソース電極２２及びドレイン電極２３は、例えば、Ｔｉ膜とＡｌ膜の積層体からなる。ゲート電極２１及びゲート絶縁膜２４は、例えば、それぞれＡｌ及びＳｉＯ２からなる。
　なお、縦型ＦＥＴ２０は、半導体積層体１を用いて形成することのできるＭＩＳゲート構造の縦型ＦＥＴの一例である。
〔第４の実施の形態〕
　第４の実施の形態として、第１の実施の形態の半導体積層体１を含むショットキーゲート構造の縦型ＦＥＴについて述べる。
　図４は、第４の実施の形態に係る半導体素子である縦型ＦＥＴの断面図である。縦型ＦＥＴ３０は、Ｇａ２Ｏ３基板２、ＡｌＮバッファ層３、及び窒化物半導体層４を含む半導体積層体１と、窒化物半導体層４の表面（図４における上側の面）上に積層されたｐ＋－ＧａＮ層３４、ｎ＋－ＧａＮ層３５、ＧａＮ層３６、及びＡｌ０．２Ｇａ０．８Ｎ層３７と、Ａｌ０．２Ｇａ０．８Ｎ層３７上に形成されたゲート電極３１と、ｐ＋－ＧａＮ層３４、ｎ＋－ＧａＮ層３５、ＧａＮ層３６、及びＡｌ０．２Ｇａ０．８Ｎ層３７に接続されたソース電極３２と、Ｇａ２Ｏ３基板２の表面（図４における下側の面）上に形成されたドレイン電極３３と、を含む。
　ここで、例えば、窒化物半導体層４の厚さは６μｍであり、Ｓｉ濃度は１×１０１６／ｃｍ３である。また、例えば、ｐ＋－ＧａＮ層３４の厚さは１μｍであり、ｐ型不純物の濃度は１×１０１８／ｃｍ３である。また、例えば、ｎ＋－ＧａＮ層３５の厚さは２００ｎｍであり、ｎ型不純物の濃度は１×１０１８／ｃｍ３である。ＧａＮ層３６は不純物を含まず、厚さは、例えば、１００ｎｍである。Ａｌ０．２Ｇａ０．８Ｎ層３７は不純物を含まず、厚さは、例えば、３０ｎｍである。ソース電極３２及びドレイン電極３３は、例えば、Ｔｉ膜とＡｌ膜の積層体からなる。ゲート電極３１は、例えば、Ｎｉ膜とＡｕ膜の積層体からなる。
　なお、縦型ＦＥＴ３０は、半導体積層体１を用いて形成することのできるショットキーゲート構造の縦型ＦＥＴの一例である。
〔第５の実施の形態〕
　第５の実施の形態として、第１の実施の形態の半導体積層体１を含む他のショットキーゲート構造の縦型ＦＥＴについて述べる。
　図５は、第５の実施の形態に係る半導体素子である縦型ＦＥＴの断面図である。縦型ＦＥＴ４０は、Ｇａ２Ｏ３基板２、ＡｌＮバッファ層３、及び窒化物半導体層４を含む半導体積層体１と、窒化物半導体層４の表面（図５における上側の面）上に形成されたｎ－－ＧａＮ層４４と、ｎ－－ＧａＮ層４４の平坦部上に形成されたゲート電極４１と、ｎ－－ＧａＮ層４４の凸部上にｎ＋－ＩｎＡｌＧａＮコンタクト層４５を介して形成されたソース電極４２と、Ｇａ２Ｏ３基板２の表面（図５における下側の面）上に形成されたドレイン電極４３と、を含む。
　ここで、例えば、窒化物半導体層４の厚さは６μｍであり、Ｓｉ濃度は１×１０１８／ｃｍ３である。また、例えば、ｎ－－ＧａＮ層４４の平坦部の厚さは３μｍであり、ｎ型不純物の濃度は１×１０１６／ｃｍ３である。ソース電極４２は、例えば、ＷＳｉからなる。ドレイン電極４３は、例えば、Ｔｉ膜とＡｌ膜の積層体からなる。ゲート電極４１は、例えば、ＰｄＳｉからなる。
　なお、縦型ＦＥＴ４０は、半導体積層体１を用いて形成することのできるショットキーゲート構造の縦型ＦＥＴの一例である。
〔第６の実施の形態〕
　第６の実施の形態として、第１の実施の形態の半導体積層体１を含むヘテロ接合バイポーラトランジスタ（ＨＢＴ）について述べる。
　図６は、第６の実施の形態に係る半導体素子であるＨＢＴの断面図である。ＨＢＴ５０は、Ｇａ２Ｏ３基板２、ＡｌＮバッファ層３、及び窒化物半導体層４を含む半導体積層体１と、窒化物半導体層４の表面（図６における上側の面）上に積層されたｎ－－ＧａＮ層５４及びｐ＋－ＧａＮ層５５と、ｐ＋－ＧａＮ層５５上に積層されたｎ＋－Ａｌ０．１Ｇａ０．９Ｎ層５６及びｎ＋－ＧａＮ層５７と、ｐ＋－ＧａＮ層５５上に形成されたベース電極５１と、ｎ＋－ＧａＮ層５７上に形成されたエミッタ電極５２と、Ｇａ２Ｏ３基板２の表面（図６における下側の面）上に形成されたコレクタ電極５３と、を含む。
　ここで、例えば、窒化物半導体層４の厚さは４μｍであり、Ｓｉ濃度は１×１０１８／ｃｍ３である。また、例えば、ｎ－－ＧａＮ層５４の厚さは２μｍであり、ｎ型不純物の濃度は１×１０１６／ｃｍ３である。また、例えば、ｐ＋－ＧａＮ層５５の厚さは１００ｎｍであり、ｐ型不純物の濃度は１×１０１８／ｃｍ３である。また、例えば、ｎ＋－Ａｌ０．１Ｇａ０．９Ｎ層５６の厚さは５００ｎｍであり、ｎ型不純物の濃度は１×１０１８／ｃｍ３である。また、例えば、ｎ＋－ＧａＮ層５７の厚さは１μｍであり、ｎ型不純物の濃度は１×１０１８／ｃｍ３である。エミッタ電極５２は、例えば、Ｔｉ膜とＡｌ膜の積層体からなる。コレクタ電極５３は、例えば、Ｔｉ膜とＡｕ膜の積層体からなる。ベース電極５１は、例えば、Ｎｉ膜とＡｕ膜の積層体からなる。
　なお、ＨＢＴ５０は、半導体積層体１を用いて形成することのできるヘテロ接合バイポーラトランジスタの一例である。
〔第７の実施の形態〕
　第７の実施の形態として、第１の実施の形態の半導体積層体１を含むショットキーバリアダイオード（ＳＢＤ）について述べる。
　図７は、第７の実施の形態に係る半導体素子であるＳＢＤの断面図である。ＳＢＤ６０は、Ｇａ２Ｏ３基板２、ＡｌＮバッファ層３、及び窒化物半導体層４を含む半導体積層体１と、窒化物半導体層４の表面（図７における上側の面）上に形成されたｎ－－ＧａＮ層６３と、ｎ－－ＧａＮ層６３上に形成されたアノード電極６１と、Ｇａ２Ｏ３基板２の表面（図７における下側の面）上に形成されたカソード電極６２と、を含む。
　ここで、例えば、窒化物半導体層４の厚さは６μｍであり、Ｓｉ濃度は１×１０１８／ｃｍ３である。また、例えば、ｎ－－ＧａＮ層６３の厚さは７μｍであり、ｎ型不純物の濃度は１×１０１６／ｃｍ３である。アノード電極６１は、例えば、Ａｕからなる。カソード電極６２は、例えば、Ｔｉ膜とＡｕ膜の積層体からなる。
　なお、ＳＢＤ６０は、半導体積層体１を用いて形成することのできるショットキーバリアダイオードの一例である。
〔第８の実施の形態〕
　第８の実施の形態として、第１の実施の形態の半導体積層体１を含む発光ダイオード（ＬＥＤ）について述べる。
　図８は、第８の実施の形態に係る半導体素子であるＬＥＤの断面図である。ＬＥＤ７０は、Ｇａ２Ｏ３基板２、ＡｌＮバッファ層３、及び窒化物半導体層４を含む半導体積層体１と、窒化物半導体層４の表面（図８における上側の面）上に積層された発光層７３、ｐ型クラッド層７４、及びｐ型コンタクト層７５と、ｐ型コンタクト層７５上に形成されたｐ電極７１と、Ｇａ２Ｏ３基板２の表面（図８における下側の面）上に形成されたｎ電極７２と、を含む。
　ここで、例えば、窒化物半導体層４の厚さは５μｍであり、Ｓｉ濃度は１×１０１８／ｃｍ３である。窒化物半導体層４は、n型クラッド層として働く。また、例えば、発光層７３は、厚さ８ｎｍのＧａＮ結晶と厚さ２ｎｍのＩｎＧａＮ結晶からなる多重量子井戸構造を３ペア含む。また、例えば、ｐ型クラッド層７４はＭｇ濃度が５．０×１０１９／ｃｍ３のＧａＮ結晶からなり、厚さは１５０ｎｍである。また、例えば、ｐ型コンタクト層７５はＭｇ濃度が１．５×１０２０／ｃｍ３のＧａＮ結晶からなり、厚さが１０ｎｍである。
　なお、ＬＥＤ７０は、半導体積層体１を用いて形成することのできる発光ダイオードの一例である。
（実施の形態の効果）
　第１の実施の形態によれば、酸素が六角格子配置された面、すなわち、（１０１）、（－２０１）、（３０１）、（３－１０）のいずれかの面を主面とするＧａ２Ｏ３基板２上にＡｌＮ結晶をエピタキシャル成長させてＡｌＮバッファ層３を形成することにより、ＡｌＮバッファ層３が薄い場合であっても、表面が鏡面であるＧａＮ結晶等の窒化物半導体結晶をエピタキシャル成長させ、表面が鏡面である窒化物半導体層４を形成することができる。ＡｌＮバッファ層３を薄くすることにより、半導体積層体１の厚さ方向の電気抵抗を大きく低減することができる。
　また、Ｓｉ濃度が５×１０１８／ｃｍ３以上であるＳｉ高濃度領域４ａを窒化物半導体層４中に形成することにより、半導体積層体１の厚さ方向の電気抵抗をより低減することができる。これは、Ｓｉ濃度の高いＳｉ高濃度領域４ａを形成することにより、電子がヘテロ界面の電位障壁をトンネルし、電流が流れやすくなることによると考えられる。
　また、Ｓｉ高濃度領域４ａの厚さを２ｎｍ以上とすることにより、半導体積層体の厚さ方向の電気抵抗をより低減できる。
　また、第２～８の実施の形態によれば、半導体積層体１を含み、通電方向が半導体積層体１の厚さ方向の縦型の半導体素子を形成することにより、高性能の縦型半導体素子を得ることができる。
　以下の実施例１、２に示すように、本実施の形態に係る半導体積層体１の評価を行った。
　実施例１においては、ＡｌＮバッファ層３の厚さが０．５～３２ｎｍの範囲内で異なる複数の半導体積層体１を形成し、ＡｌＮバッファ層３の厚さと半導体積層体１の厚さ方向の電気抵抗の関係を調べた。各半導体積層体１の形成工程は次の通りである。
　まず、主面が（１０１）であるＧａ２Ｏ３基板２を有機洗浄及び酸洗浄した後、ＭＯＣＶＤ装置の中に設置した。次に、窒素希釈したアンモニア（ＮＨ３）雰囲気中で基板温度を５５０℃にして表面を窒化した。
　その後、基板温度を４５０℃にしてトリメチルアルミニウム（ＴＭＡ）とＮＨ３を炉内に流してＡｌＮ結晶を成長させ、低温ＡｌＮバッファ層であるＡｌＮバッファ層３を形成した。
　基板温度を１０５０℃まで上昇させた後に、炉内雰囲気を水素に切り替えて、トリメチルガリウム（ＴＭＧ）とＮＨ３とモノシラン（ＭｔＳｉＨ３）を炉内に流し、Ｓｉ濃度が２．０×１０１８／ｃｍ３であるＧａＮ結晶を成長させ、厚さ２μｍの窒化物半導体層４を形成した。
　そして、上記の工程により製造したＧａ２Ｏ３基板２及び窒化物半導体層４の表面上に各々電極を形成した。そして、電極間に電圧を印加し、電流密度が２２０Ａ／ｃｍ２であるときの電圧降下を測定した。
　図９は、ＡｌＮバッファ層の厚さと電流密度が２２０Ａ／ｃｍ２であるときの電圧降下との関係を表すグラフである。図９に示されるように、ＡｌＮバッファ層３の厚さが小さいほど電圧降下が小さい、すなわち半導体積層体１の厚さ方向の電気抵抗が低い。特に、ＡｌＮバッファ層３の厚さが４ｎｍ以下であるときには、電圧降下が０．５Ｖと非常に小さい。例えば、電圧降下が０．６Ｖ以下である場合に、半導体積層体１を用いて高性能な半導体素子を製造することができる。
　また、上記の工程により製造したＧａＮ結晶からなる窒化物半導体層４の結晶品質をエックス線回折装置を用いて評価した。窒化物半導体層４を構成するＧａＮ結晶の（００２）面及び（１０１）面に対して測定を行った。
　図１０は、ＡｌＮバッファ層の厚さとエックス線回折のロッキングカーブの半値幅との関係を表すグラフである。図１０は、（００２）面及び（１０１）面のいずれについての測定結果においても、ＡｌＮバッファ層３の厚さが小さいほど半値幅が小さく、結晶品質が高いことを示している。
　実施例２においては、第８の実施の形態のＬＥＤ７０を形成し、順方向の電圧降下ＶＦを測定した。
　まず、Ｓｉを添加したｎ型のβ－Ｇａ２Ｏ３基板をＧａ２Ｏ３基板２として用意した。ここで、β－Ｇａ２Ｏ３基板の厚さは４００μｍであり、主面は（１０１）である。
　次に、β－Ｇａ２Ｏ３基板上に、ＭＯＣＶＤ装置を用いて成長温度４５０℃でＡｌＮ結晶を２ｎｍ成長させてＡｌＮバッファ層３を形成した。次に、Ｓｉ濃度１．０×１０１８／ｃｍ３のＧａＮ結晶を５μｍ成長させてn型クラッド層としての窒化物半導体層４を形成した。
　次に、成長温度７５０℃で厚さ８ｎｍのＧａＮ結晶と厚さ２ｎｍのＩｎＧａＮ結晶からなる多重量子井戸構造を３ペア形成し、さらにＧａＮ結晶を１０ｎｍ成長させて発光層７３を形成した。
　次に、成長温度１０００℃でＭｇ濃度が５．０×１０１９／ｃｍ３のＧａＮ結晶を１５０ｎｍ成長させ、ｐ型クラッド層７４を形成した。次に、成長温度１０００℃でＭｇ濃度が１．５×１０２０／ｃｍ３のＧａＮ結晶を１０ｎｍ成長させ、ｐ型コンタクト層７５を形成した。
　以上の工程において、Ｇａ原料としてＴＭＧ(トリメチルガリウム)、Ｉｎ原料としてＴＭＩ(トリメチルインジウム)、Ｓｉ原料としてＳｉＨ３ＣＨ３(モノメチルシラン)ガス、Ｍｇ原料としてＣｐ２Ｍｇ(シクロペンタジエニルマグネシウム)、Ｎ原料としてＮＨ３(アンモニア)ガスを用いた。
　上記のようにして作製したＬＥＤエピタキシャルウエハ表面を、ＩＣＰ－ＲＩＥ装置を用いてｐ型コンタクト層７５側から発光層７３より深い位置までエッチングし、メサ形状を形成した。次に、スパッタ装置を用いてＳｉＯ２膜を発光層７３の側面に形成した。更に、蒸着装置を用いてｐ型コンタクト層７５上及びＧａ２Ｏ３基板２上にそれぞれオーミック接合する電極を形成し、光取り出し面がＧａ２Ｏ３基板２側にあるＬＥＤ７０を得た。
　また、比較例として、ＡｌＮバッファ層３の厚さが２０ｎｍあるＬＥＤを形成した。
　その後、ＬＥＤ７０及び比較例のＬＥＤをキャンタイプのステムにＡｇペーストを用いてそれぞれ実装し、２０ｍＡの電流ＩＦが流れるときの電圧降下ＶＦを測定した。その結果、比較例の従来型のＬＥＤの電圧降下ＶＦが４．３２Ｖであったのに対して、ＬＥＤ７０の電圧降下ＶＦは３．１２Ｖであり、発光素子として実用可能なレベルの電圧降下ＶＦを示すことが確認された。
　以上、本発明の実施の形態及び実施例を説明したが、上記に記載した実施の形態及び実施例は特許請求の範囲に係る発明を限定するものではない。また、実施の形態及び実施例の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。
１…半導体積層体、２…Ｇａ２Ｏ３基板、３…ＡｌＮバッファ層、４…窒化物半導体層、４ａ…Ｓｉ高濃度領域、４ｂ…領域、１０、２０、３０、４０…縦型ＦＥＴ、５０…ＨＢＴ、６０…ＳＢＴ、７０…ＬＥＤ

Claims (13)

  1. 　酸素が六角格子配置された面を主面とするＧａ２Ｏ３基板と、
    　前記Ｇａ２Ｏ３基板上のＡｌＮバッファ層と、
    　前記ＡｌＮバッファ層上の窒化物半導体層と、
    　を含む半導体積層体。
  2. 　前記Ｇａ２Ｏ３基板の前記主面は、（１０１）、（－２０１）、（３０１）、（３－１０）のいずれかの面である、
    　請求項１に記載の半導体積層体。
  3. 　前記Ｇａ２Ｏ３基板の前記主面は、（１０１）である、
    　請求項２に記載の半導体積層体。
  4. 　前記ＡｌＮバッファ層の厚さは１ｎｍ以上５ｎｍ以下である、
    　請求項１～３のいずれか１つに記載の半導体積層体。
  5. 　前記ＡｌＮバッファ層の厚さは２ｎｍ以上３ｎｍ以下である、
    　請求項４に記載の半導体積層体。
  6. 　前記窒化物半導体層はＧａＮ層である、
    　請求項１に記載の半導体積層体。
  7. 　厚さ方向の電圧降下が０．６Ｖ以下である、
    　請求項１に記載の半導体積層体。
  8. 　前記窒化物半導体層は、前記ＡｌＮバッファ層側の一部の領域にＳｉ濃度が５×１０１８／ｃｍ３以上であるＳｉ高濃度領域を有する、
    　請求項１に記載の半導体積層体。
  9. 　前記Ｓｉ高濃度領域の厚さが２ｎｍ以上である、
    　請求項８に記載の半導体積層体。
  10. 　酸素が六角格子配置された面を主面とするＧａ２Ｏ３基板と、前記Ｇａ２Ｏ３基板上のＡｌＮバッファ層と、前記ＡｌＮバッファ層上の窒化物半導体層と、を含む半導体積層体を含み、
    　前記半導体積層体の厚さ方向に通電する、
    　半導体素子。
  11. 　酸素が六角格子配置された面を主面とするＧａ２Ｏ３基板上に、５００℃以下の温度条件でＡｌＮ結晶をエピタキシャル成長させてＡｌＮバッファ層を形成する工程と、
    　前記ＡｌＮバッファ層上に窒化物半導体結晶を成長させて窒化物半導体層を形成する工程と、
    　を含む半導体積層体の製造方法。
  12. 　前記ＡｌＮバッファ層は１ｎｍ以上５ｎｍ以下の厚さに形成される、
    　請求項１１に記載の半導体積層体の製造方法。
  13. 　前記窒化物半導体結晶はＧａＮ結晶である、
    　請求項１１又は１２に記載の半導体積層体の製造方法。
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KR20140030180A (ko) 2014-03-11
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DE112012001618T5 (de) 2014-03-27
CN103503148A (zh) 2014-01-08
US20140048823A1 (en) 2014-02-20
JP2014199935A (ja) 2014-10-23
TW201248921A (en) 2012-12-01

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