CN103503148A - 半导体层叠体及其制造方法以及半导体元件 - Google Patents

半导体层叠体及其制造方法以及半导体元件 Download PDF

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CN103503148A
CN103503148A CN201280016886.8A CN201280016886A CN103503148A CN 103503148 A CN103503148 A CN 103503148A CN 201280016886 A CN201280016886 A CN 201280016886A CN 103503148 A CN103503148 A CN 103503148A
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China
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multilayer body
semiconductor multilayer
resilient coating
substrate
semiconductor
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CN201280016886.8A
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佐藤慎九郎
仓又朗人
森岛嘉克
饭塚和幸
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Tamura Corp
Koha Co Ltd
Sun Wave Corp
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Tamura Corp
Koha Co Ltd
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Publication of CN103503148A publication Critical patent/CN103503148A/zh
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Abstract

本发明提供一种厚度方向的电阻低的半导体层叠体及其制造方法、以及包括该半导体层叠体的半导体元件。本发明提供包括将氧被六角网格状配置的面设为主面的Ga2O3基板（2）、Ga2O3基板（2）上的AlN缓冲层（3）、以及AlN缓冲层（3）上的氮化物半导体层（4）的半导体层叠体（1）。

Description

半导体层叠体及其制造方法以及半导体元件
技术领域
本发明涉及半导体层叠体及其制造方法、以及半导体元件。
背景技术
以往，包括由Ga2O3基板、AlN缓冲层、以及GaN层形成的半导体层叠体的半导体元件被广为人知（例如，参照专利文献1）。根据专利文献1，AlN缓冲层是通过在Ga2O3基板上使AlN结晶生长而形成为10～30nm的厚度。另外，GaN层通过在AlN缓冲层上使GaN结晶生长而形成，并且作为施主包括Si。
专利文献1：日本特开2006-310765号公报
在专利文献1的半导体元件等通电方向为纵向的纵型元件中，半导体层叠体的厚度方向的电阻的降低非常重要。
发明内容
鉴于此，本发明的目的在于提供一种厚度方向的电阻低的半导体层叠体及其制造方法、以及包括该半导体层叠体的半导体元件。
为了达到上述目的，本发明的一方式提供[1]～[9]的半导体层叠体、[10]半导体元件、以及[11]～[13]的半导体层叠体的制造方法。
[1]一种半导体层叠体，包括将六角网格状配置有氧的面设为主面的Ga2O3基板、上述Ga2O3基板上的AlN缓冲层、以及上述AlN缓冲层上的氮化物半导体层。
[2]根据上述[1]所记载的半导体层叠体，上述Ga2O3基板的上述主面是（101）、（-201）、（301）、（3-10）中的任意一种面。
[3]根据上述[2]所记载的半导体层叠体，上述Ga2O3基板的上述主面是（101）。
[4]根据上述[1]～[3]中任意1个所记载的半导体层叠体，上述AlN缓冲层的厚度为1nm以上5nm以下。
[5]根据上述[4]所记载的半导体层叠体，上述AlN缓冲层的厚度为2nm以上3nm以下。
[6]根据上述[1]所记载的半导体层叠体，上述氮化物半导体层是GaN层。
[7]根据上述[1]所记载的半导体层叠体，厚度方向的电压降为0.6V以下。
[8]根据上述[1]所记载的半导体层叠体，上述氮化物半导体层在上述AlN缓冲层侧的部分区域具有Si浓度为5×1018/cm3以上的Si高浓度区域。
[9]根据上述[8]所记载的半导体层叠体，上述Si高浓度区域的厚度为2nm以上。
[10]一种半导体元件，包括半导体层叠体，该半导体层叠体包括将六角网格状配置有氧的面设为主面的Ga2O3基板；上述Ga2O3基板上的AlN缓冲层；以及上述AlN缓冲层上的氮化物半导体层，并且向上述半导体层叠体的厚度方向通电。
[11]一种半导体层叠体的制造方法，包括：在将六角网格状配置有氧的面设为主面的Ga2O3基板上，在500℃以下的温度条件下使AlN结晶外延生长，从而形成AlN缓冲层的工序；以及在上述AlN缓冲层上使氮化物半导体结晶生长从而形成氮化物半导体层的工序。
[12]根据上述[11]所记载的半导体层叠体的制造方法，上述AlN缓冲层形成为1nm以上5nm以下的厚度。
[13]根据上述[11]或者[12]所记载的半导体层叠体的制造方法，上述氮化物半导体结晶是GaN结晶。
根据本发明，能够提供厚度方向的电阻低的半导体层叠体及及其制造方法、以及包括该半导体层叠体的半导体元件。
附图说明
图1A是第1实施方式所涉及的半导体层叠体的剖面图。
图1B是第1实施方式所涉及的半导体层叠体的剖面图。
图2是第2实施方式所涉及的纵型FET的剖面图。
图3是第3实施方式所涉及的纵型FET的剖面图。
图4是第4实施方式所涉及的纵型FET的剖面图。
图5是第5实施方式所涉及的纵型FET的剖面图。
图6是第6实施方式所涉及的HBT的剖面图。
图7是第7实施方式所涉及的SBD的剖面图。
图8是第8实施方式所涉及的LED的剖面图。
图9是表示实施例所涉及的AlN缓冲层的厚度与电压降的关系的图。
图10是表示实施例所涉及的AlN缓冲层的厚度与X-射线衍射的摇摆曲线的半值宽度的关系的图。
具体实施方式
根据本实施方式，能够形成由Ga2O3基板、AlN缓冲层、以及GaN层等氮化物半导体层构成的、厚度方向的电阻低的半导体层叠体。本发明者等发现：通过在将特定的面设为主面的Ga2O3基板上使AlN结晶外延生长从而形成AlN缓冲层，由此即使在AlN缓冲层较薄的情况下，也能够使表面为镜面的GaN结晶等氮化物半导体结晶外延生长。通过使AlN缓冲层变薄，能够较大地降低半导体层叠体的厚度方向的电阻。
另外，根据本实施方式，通过使用厚度方向的电阻小的半导体层叠体，能够形成高性能的半导体元件。下面，对该实施方式的一个例子进行详细地说明。
<第1实施方式>
图1A是第1实施方式所涉及的半导体层叠体的剖面图。半导体层叠体1包括Ga2O3基板2、AlN缓冲层3、和氮化物半导体层4。
Ga2O3基板2由β-Ga2O3单结晶构成。Ga2O3基板2是将氧被六角网格状配置的面、即（101）、（-201）、（301）、（3-10）中的任意一种面设为主面的基板。这种情况下，即使在AlN缓冲层3较薄（例如10nm以下）的情况下，也能够使表面平坦的氮化物半导体结晶在AlN缓冲层3上生长，从而形成氮化物半导体层4。尤其，优选Ga2O3基板2的主面为（101）。
另外，若在将上述的面以外的面、例如（100）设为主面的Ga2O3基板上形成薄的AlN缓冲层，则在AlN缓冲层上外延生长的GaN结晶会生长成六角丘状，结晶表面不能成为镜面。
AlN缓冲层3通过利用MOCVD（有机金属化学汽相淀积：MetalOrganic Chemical Vapor Deposition）法等，在Ga2O3基板2上使AlN结晶外延生长而形成。AlN结晶的生长温度为350～600℃，尤其优选380～500℃。
AlN缓冲层3的厚度为1～5nm（1nm以上、5nm以下），比较优选为2～3nm。在厚度为1nm以下的情况下，构成氮化物半导体层4的GaN结晶等氮化物半导体结晶成长成六角丘状，表面不能成为镜面。另外，在厚度超过5nm的情况下，半导体层叠体1的厚度方向的电阻变大。在厚度为2～3nm的情况下，半导体层叠体1的厚度方向的电阻小，且在AlN缓冲层3上生长的氮化物半导体结晶的表面比较容易成为镜面。
另外，AlN缓冲层3的厚度越薄，氮化物半导体层4的结晶品质越高。例如，在AlN缓冲层3的厚度为1～5nm的情况下，能够形成具有充分的结晶品质的氮化物半导体层4。
氮化物半导体层4通过利用MOCVD法等，在AlN缓冲层3上对GaN结晶等氮化物半导体结晶一边添加Si等导电型杂质一边使其外延生长而形成。在使用GaN结晶作为氮化物半导体结晶的情况下，其生长温度为例如800～1100℃。氮化物半导体层4的厚度为例如2μm。氮化物半导体层4的Si浓度为例如2×1018/cm3。
另外，如图1B所示，半导体层叠体1的氮化物半导体层4也可以在AlN缓冲层3侧的表面附近包含Si高浓度区域4a。通过在氮化物半导体层4中形成Si高浓度区域4a，能够更加降低半导体层叠体1的厚度方向的电阻。
Si高浓度区域4a通过在AlN缓冲层3上的氮化物半导体结晶的生长的初期阶段增大Si的添加量来形成。
Si高浓度区域4a的Si浓度比该其他的区域4b的Si浓度高。Si高浓度区域4a的Si浓度为5×1018/cm3以上，尤其优选1×1019/cm3以上。
另外，为了更加降低半导体层叠体1的厚度方向的电阻，优选Si高浓度区域4a的厚度为2nm以上。
<第2实施方式>
作为第2实施方式，对包含第1实施方式的半导体层叠体1的纵型FET（场效应晶体管：Field effect transistor）进行叙述。
图2是作为第2实施方式所涉及的半导体元件的纵型FET的剖面图。纵型FET10包括：具有Ga2O3基板2、AlN缓冲层3以及作为氮化物半导体层的n+-GaN层15的半导体层叠体1；形成于n+-GaN层15的表面（图2中的上侧的面）上的GaN系纵型FET14；形成于GaN系纵型FET14上的栅极电极11和源极电极12；以及形成于Ga2O3基板2的表面（图2中的下侧的面）上的漏极电极13。
另外，纵型FET10是能够使用半导体层叠体1来形成的纵型FET的一个例子。
<第3实施方式>
作为第3实施方式，对包括有第1实施方式的半导体层叠体1的MIS（金属-绝缘体-半导体：Metal Insulator Semiconductor）门结构的纵型FET进行叙述。
图3是作为第3实施方式所涉及的半导体元件的纵型FET的剖面图。纵型FET20包括：具有Ga2O3基板2、AlN缓冲层3、以及氮化物半导体层4的半导体层叠体1；通过向氮化物半导体层4中导入p型杂质而形成的p+区域25；形成于氮化物半导体层4的表面（图3中的上侧的面）上的Al0.2Ga0.8N层26；通过向Al0.2Ga0.8N层26中导入Si等n型杂质而形成的n+区域27；隔着栅极绝缘膜24而形成于Al0.2Ga0.8N层26上的栅极电极21；与n+区域27和p+区域25连接的源极电极22；以及形成于Ga2O3基板2的表面（图3中的下侧的面）上的漏极电极23。
此处，例如氮化物半导体层4的厚度为6μm，Si浓度为1×1018/cm3。另外，例如p+区域25的厚度为1μm，p型杂质的浓度为1×1018/cm3。Al0.2Ga0.8N层26不含杂质。源极电极22和漏极电极23例如由Ti膜和Al膜的层叠体构成。栅极电极21和栅极绝缘膜24例如分别由Al及SiO2构成。
另外，纵型FET20是能够使用半导体层叠体1来形成的MIS门结构的纵型FET的一个例子。
<第4实施方式>
作为第4实施方式，对包括有第1实施方式的半导体层叠体1的肖特基门结构的纵型FET进行叙述。
图4是作为第4实施方式所涉及的半导体元件的纵型FET的剖面图。纵型FET30包括：具有Ga2O3基板2、AlN缓冲层3、以及氮化物半导体层4的半导体层叠体1；层叠于氮化物半导体层4的表面（图4中的上侧的面）上的p+-GaN层34、n+-GaN层35、GaN层36以及Al0.2Ga0.8N层37；形成于Al0.2Ga0.8N层37上的栅极电极31；与p+-GaN层34、n+-GaN层35、GaN层36及Al0.2Ga0.8N层37连接的源极电极32；以及形成于Ga2O3基板2的表面（图4中的下侧的面）上的漏极电极33。
此处，例如氮化物半导体层4的厚度为6μm，Si浓度为1×1016/cm3。另外，例如p+-GaN层34的厚度为1μm，p型杂质的浓度为1×1018/cm3。另外，例如n+-GaN层35的厚度为200nm，n型杂质的浓度为1×1018/cm3。GaN层36不含杂质，且厚度为例如100nm。Al0.2Ga0.8N层37不含杂质，且厚度为例如30nm。源极电极32和漏极电极33例如由Ti膜和Al膜的层叠体构成。栅极电极31例如由Ni膜和Au膜的层叠体构成。
另外，纵型FET30是能够使用半导体层叠体1来形成的肖特基门结构的纵型FET的一个例子。
<第5实施方式>
作为第5实施方式，对包括有第1实施方式的半导体层叠体1的其他的肖特基门结构的纵型FET进行叙述。
图5是作为第5实施方式所涉及的半导体元件的纵型FET的剖面图。纵型FET40包括：具有Ga2O3基板2、AlN缓冲层3以及氮化物半导体层4的半导体层叠体1；形成于氮化物半导体层4的表面（图5中的上侧的面）上的n--GaN层44；形成于n--GaN层44的平坦部上的栅极电极41；隔着n+-InAlGaN接触层45而形成于n--GaN层44的凸部上的源极电极42；以及形成于Ga2O3基板2的表面（图5中的下侧的面）上的漏极电极43。
此处，例如氮化物半导体层4的厚度为6μm，Si浓度为1×1018/cm3。另外，例如n--GaN层44的平坦部的厚度为3μm，n型杂质的浓度为1×1016/cm3。源极电极42例如由WSi构成。漏极电极43例如由Ti膜和Al膜的层叠体构成。栅极电极41例如由PdSi构成。
另外，纵型FET40是能够使用半导体层叠体1来形成的肖特基门结构的纵型FET的一个例子。
<第6实施方式>
作为第6实施方式，对包括有第1实施方式的半导体层叠体1的异质结双极晶体管（HBT）进行叙述。
图6是作为第6实施方式所涉及的半导体元件的HBT的剖面图。HBT50包括：具有Ga2O3基板2、AlN缓冲层3以及氮化物半导体层4的半导体层叠体1；层叠于氮化物半导体层4的表面（图6中的上侧的面）上的n--GaN层54和p+-GaN层55；层叠于p+-GaN层55上的n+-Al0.1Ga0.9N层56和n+-GaN层57；形成于p+-GaN层55上的基极电极51；形成于n+-GaN层57上的发射极电极52；以及形成于Ga2O3基板2的表面（图6中的下侧的面）上的集电极电极53。
此处，例如氮化物半导体层4的厚度为4μm，Si浓度为1×1018/cm3。另外，例如n--GaN层54的厚度为2μm，n型杂质的浓度为1×1016/cm3。另外，例如p+-GaN层55的厚度为100nm，p型杂质的浓度为1×1018/cm3。另外，例如n+-Al0.1Ga0.9N层56的厚度为500nm，n型杂质的浓度为1×1018/cm3。另外，例如n+-GaN层57的厚度为1μm，n型杂质的浓度为1×1018/cm3。发射极电极52例如由Ti膜和Al膜的层叠体构成。集电极电极53例如由Ti膜和Au膜的层叠体构成。基极电极51例如由Ni膜和Au膜的层叠体构成。
另外，HBT50是能够使用半导体层叠体1来形成的异质结双极晶体管的一个例子。
<第7实施方式>
作为第7实施方式，对包括有第1实施方式的半导体层叠体1的肖特基势垒二极管（SBD）进行叙述。
图7是作为第7实施方式所涉及的半导体元件的SBD的剖面图。SBD60包括：具有Ga2O3基板2、AlN缓冲层3以及氮化物半导体层4的半导体层叠体1；形成于氮化物半导体层4的表面（图7中的上侧的面）上的n--GaN层63；形成于n--GaN层63上的阳极电极61；以及形成于Ga2O3基板2的表面（图7中的下侧的面）上的阴极电极62。
此处，例如氮化物半导体层4的厚度为6μm，Si浓度为1×1018/cm3。另外，例如n--GaN层63的厚度为7μm，n型杂质的浓度为1×1016/cm3。阳极电极61例如由Au构成。阴极电极62例如由Ti膜和Au膜的层叠体构成。
另外，SBD60是能够使用半导体层叠体1来形成的肖特基势垒二极管的一个例子。
<第8实施方式>
作为第8实施方式，对包括有第1实施方式的半导体层叠体1的发光二极管（LED）进行叙述。
图8是作为第8实施方式所涉及的半导体元件的LED的剖面图。LED70包括：具有Ga2O3基板2、AlN缓冲层3以及氮化物半导体层4的半导体层叠体1；层叠于氮化物半导体层4的表面（图8中的上侧的面）上的发光层73、p型金属包层74和p型接触层75；形成于p型接触层75上的p电极71；以及形成于Ga2O3基板2的表面（图8中的下侧的面）上的n电极72。
此处，例如氮化物半导体层4的厚度为5μm，Si浓度为1×1018/cm3。氮化物半导体层4作为n型金属包层工作。另外，例如发光层73包括3对由厚度为8nm的GaN结晶和厚度为2nm的InGaN结晶构成的多层量子阱结构。另外，例如p型金属包层74由Mg浓度为5.0×1019/cm3的GaN结晶构成，且厚度为150nm。另外，例如p型接触层75由Mg浓度为1.5×1020/cm3的GaN结晶构成，且厚度为10nm。
另外，LED70是能够使用半导体层叠体1来形成的发光二极管的一个例子。
（实施方式的效果）
根据第1实施方式，通过在将六角网格状配置有氧的面、即（101）、（-201）、（301）、（3-10）中的任意一种面设为主面的Ga2O3基板2上使AlN结晶外延生长来形成AlN缓冲层3，由此即使在AlN缓冲层3较薄的情况下，也能够使表面为镜面的GaN结晶等氮化物半导体结晶外延生长，从而形成表面为镜面的氮化物半导体层4。通过使AlN缓冲层3变薄，能够极大地降低半导体层叠体1的厚度方向的电阻。
另外，通过在氮化物半导体层4中形成Si浓度为5×1018/cm3以上的Si高浓度区域4a，能够更加降低半导体层叠体1的厚度方向的电阻。这是由于|通过形成Si浓度较高的Si高浓度区域4a，电子隧穿过异质界面的电位势垒，电流变得易于流动。
另外，通过将Si高浓度区域4a的厚度设为2nm以上，能够更加降低半导体层叠体的厚度方向的电阻。
另外，根据第2～8实施方式，通过包括半导体层叠体1来形成通电方向为半导体层叠体1的厚度方向的纵型的半导体元件，能够得到高性能的纵型半导体元件。
如以下的实施例1、2所示，进行对本实施方式所涉及的半导体层叠体1的评价。
实施例1
在实施例1中，形成在0.5～32nm的范围内AlN缓冲层3的厚度不同的多个半导体层叠体1，来调查了AlN缓冲层3的厚度与半导体层叠体1的厚度方向的电阻的关系。各个半导体层叠体1的形成工序如下所述。
首先，在对主面为（101）的Ga2O3基板2进行有机清洗和酸性清洗之后，设置于MOCVD装置之中。然后，在用氮气稀释了的氨气（NH3）气氛中使基板温度成为550℃来将表面氮化。
然后，使基板温度成为450℃且向炉内流入三甲基铝（TMA）和NH3来使AlN结晶生长，形成了低温AlN缓冲层亦即AlN缓冲层3。
在使基板温度上升至1050℃之后，将炉内气氛切换成氢气，向炉内流入三甲基镓（TMG）和NH3和单硅烷（MtSiH3），使Si浓度为2.0×1018/cm3的GaN结晶生长，形成了厚度为2μm的氮化物半导体层4。
而且，在由上述的工序制造的Ga2O3基板2和氮化物半导体层4的表面上形成了各个电极。然后，向电极间施加电压，测定了电流密度为220A/cm2时的电压降。
图9是表示AlN缓冲层的厚度与电流密度为220A/cm2时的电压降的关系的图。如图9所示，AlN缓冲层3的厚度越小电压降越小，即半导体层叠体1的厚度方向的电阻越低。尤其是当AlN缓冲层3的厚度为4nm以下时，电压降为0.5V，非常地小。例如，在电压降为0.6V以下的情况下，使用半导体层叠体1能够制造高性能的半导体元件。
另外，使用X-射线衍射装置对由上述工序制造的由GaN结晶构成的氮化物半导体层4的结晶品质进行了评价。对构成氮化物半导体层4的GaN结晶的（002）面以及（101）面进行了测定。
图10是表示AlN缓冲层的厚度与X-射线衍射的摇摆曲线的半值宽度的关系的图。图10显示在对于（002）面以及（101）面的任何一种面的测定结果中，都是AlN缓冲层3的厚度越小半值宽度越小，结晶品质越高。
实施例2
在实施例2中，形成了第8实施方式的LED70，并且测定了正向的电压降VF。
首先，准备添加了Si的n型的β-Ga2O3基板来作为Ga2O3基板2。此处，β-Ga2O3基板的厚度为400μm，主面为（101）。
然后，在β-Ga2O3基板上，使用MOCVD装置在生长温度450℃下使AlN结晶生长2nm，从而形成了AlN缓冲层3。接下来，使Si浓度1.0×1018/cm3的GaN结晶生长5μm，从而形成了作为n型金属包层的氮化物半导体层4。
接下来，在生长温度750℃下形成3对由厚度为8nm的GaN结晶和厚度为2nm的InGaN结晶构成的多层量子阱结构，然后使GaN结晶生长10nm，从而形成了发光层73。
接下来，在生长温度1000℃下使Mg浓度为5.0×1019/cm3的GaN结晶生长150nm，从而形成了p型金属包层74。然后，在生长温度1000℃下使Mg浓度为1.5×1020/cm3的GaN结晶生长10nm，从而形成了p型接触层75。
在以上的工序中，作为Ga原料使用了TMG(三甲基镓)、作为In原料使用了TMI(三甲基铟)、作为Si原料使用了SiH3CH3(单甲基硅烷)气体、作为Mg原料使用了Cp2Mg(茂基镁)、作为N原料使用了NH3(氨)气体。
使用ICP-RIE装置，从p型接触层75侧直至比发光层73更深的位置为止，对按照上述方式制作的LED外延片表面进行蚀刻，从而形成了高台形状。然后，使用溅射装置在发光层73的侧面形成了SiO2膜。接下来，使用蒸镀装置分别在p型接触层75上和Ga2O3基板2上形成欧姆接触的电极，从而得到了光取出面位于Ga2O3基板2侧的LED70。
另外，作为比较例，形成了AlN缓冲层3的厚度为20nm的LED。
此后，使用Ag膏分别将LED70和比较例的LED安装至罩型管座，测定了20mA的电流IF流动时的电压降VF。结果可以确认，相对于比较例的现有类型的LED的电压降VF为4.32V，LED70的电压降VF是3.12V，表示是作为发光元件而能够实用的水平的电压降VF。
以上，对本发明的实施方式和实施例进行了说明，但上述所记载的实施方式和实施例并不限定权利要求书所涉及的发明。另外，需要注意的是，所有的在实施方式和实施例中说明了的特征的组合，对于用于解决发明的课题的方法而言不一定是必不可少的。
附图标记说明：1...半导体层叠体；2...Ga2O3基板；3...AlN缓冲层；4...氮化物半导体层；4a...Si高浓度区域；4b...区域；10、20、30、40...纵型FET；50...HBT；60...SBT；70...LED。

Claims (13)

1.一种半导体层叠体，其中，包括：
将六角网格状配置有氧的面设为主面的Ga2O3基板；
所述Ga2O3基板上的AlN缓冲层；以及
所述AlN缓冲层上的氮化物半导体层。
2.根据权利要求1所述的半导体层叠体，其中，
所述Ga2O3基板的所述主面是（101）、（-201）、（301）、（3-10）中的任意一种面。
3.根据权利要求2所述的半导体层叠体，其中，
所述Ga2O3基板的所述主面是（101）。
4.根据权利要求1至3中任意一项所述的半导体层叠体，其中，
所述AlN缓冲层的厚度为1nm以上5nm以下。
5.根据权利要求4所述的半导体层叠体，其中，
所述AlN缓冲层的厚度为2nm以上3nm以下。
6.根据权利要求1所述的半导体层叠体，其中，
所述氮化物半导体层是GaN层。
7.根据权利要求1所述的半导体层叠体，其中，
厚度方向的电压降为0.6V以下。
8.根据权利要求1所述的半导体层叠体，其中，
所述氮化物半导体层在所述AlN缓冲层侧的部分区域具有Si浓度为5×1018/cm3以上的Si高浓度区域。
9.根据权利要求8所述的半导体层叠体，其中，
所述Si高浓度区域的厚度为2nm以上。
10.一种半导体元件，其中，包括半导体层叠体，
该半导体层叠体包括：
将六角网格状配置有氧的面设为主面的Ga2O3基板；
所述Ga2O3基板上的AlN缓冲层；以及
所述AlN缓冲层上的氮化物半导体层，
其中，向所述半导体层叠体的厚度方向通电。
11.一种半导体层叠体的制造方法，其中，包括：
在将六角网格状配置有氧的面设为主面的Ga2O3基板上，在500℃以下的温度条件下使AlN结晶外延生长，从而形成AlN缓冲层的工序；
在所述AlN缓冲层上使氮化物半导体结晶生长，从而形成氮化物半导体层的工序。
12.根据权利要求11所述的半导体层叠体的制造方法，其中，
所述AlN缓冲层形成为1nm以上5nm以下的厚度。
13.根据权利要求11或12所述的半导体层叠体的制造方法，其中，
所述氮化物半导体结晶是GaN结晶。
CN201280016886.8A 2011-04-08 2012-04-03 半导体层叠体及其制造方法以及半导体元件 Pending CN103503148A (zh)

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