CN103518008A - 半导体层叠体及其制造方法和半导体元件 - Google Patents
半导体层叠体及其制造方法和半导体元件 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000002425 crystallisation Methods 0.000 claims description 54
- 230000008025 crystallization Effects 0.000 claims description 54
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 claims description 39
- 229910052753 mercury Inorganic materials 0.000 claims description 37
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000000407 epitaxy Methods 0.000 claims description 3
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 abstract 2
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- 239000007789 gas Substances 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- MHYQBXJRURFKIN-UHFFFAOYSA-N C1(C=CC=C1)[Mg] Chemical compound C1(C=CC=C1)[Mg] MHYQBXJRURFKIN-UHFFFAOYSA-N 0.000 description 1
- 229910021140 PdSi Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
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- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明提供厚度方向的电阻低的半导体层叠体及其制造方法、以及具有该半导体层叠体的半导体元件。提供具有Ga2O3基板2、Ga2O3基板2上的AlGaInN缓冲层3、AlGaInN缓冲层3上的含Si的氮化物半导体层4、形成在氮化物半导体层4内的AlGaInN缓冲层3侧的部分区域上的Si浓度在5×1018/cm3以上的Si高浓度区域4a的半导体层叠体1。
Description
技术领域
本发明涉及半导体层叠体及其制造方法和半导体元件。
背景技术
以往,已知有包含由Ga2O3基板、AlN缓冲层及GaN层构成的半导体层叠体的半导体元件(例如专利文献1)。根据专利文献1,AlN缓冲层通过使AlN结晶在Ga2O3基板上生长而形成10~30nm的厚度。此外,GaN层通过使GaN结晶在AlN层上生长而形成,含有Si作为给体。
专利文献:
专利文献1:日本特开2006-310765号公报
发明内容
在专利文献1的半导体元件等通电方向为纵向的纵型元件中,半导体层叠体的厚度方向的电阻的降低很重要。
因此,本发明旨在提供厚度方向的电阻低的半导体层叠体及其制造方法、以及具有该半导体层叠体的半导体元件。
为了达成上述目的,本发明的一实施方式提供〔1〕~〔5〕的半导体层叠体、〔6〕半导体元件、以及〔7〕~〔11〕的半导体层叠体的制造方法。
〔1〕半导体层叠体,其具有Ga2O3基板、上述Ga2O3基板上的由AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的缓冲层和上述缓冲层上的由含有Si的AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的氮化物半导体层,上述氮化物半导体层在上述缓冲层侧的部分区域具有Si浓度在5×1018/cm3以上的Si高浓度区域。
〔2〕上述〔1〕所述的半导体层叠体,其中,上述Si高浓度区域的厚度在2nm以上。
〔3〕上述〔1〕或〔2〕所述的半导体层叠体,其中,上述缓冲层的厚度在0.5nm以上、10nm以下。
〔4〕上述〔1〕所述的半导体层叠体,其中,上述缓冲层的上述AlxGayInzN结晶为AlN结晶。
〔5〕上述〔1〕所述的半导体层叠体,其中,上述氮化物半导体层的上述AlxGayInzN 结晶为GaN结晶。
〔6〕半导体元件,其包含半导体层叠体,所述半导体层叠体具有Ga2O3基板、上述Ga2O3基板上的由AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的缓冲层和上述缓冲层上的由含有Si的AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的氮化物半导体层,上述氮化物半导体层在上述缓冲层侧的部分区域具有Si浓度在5×1018/cm3以上的Si高浓度区域,在上述半导体层叠体的厚度方向通电。
〔7〕半导体层叠体的制造方法,其包括在Ga2O3基板上使AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶外延生长、形成缓冲层的工序和边在上述缓冲层上添加Si边使AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶生长、形成氮化物半导体层的工序,通过在上述AlxGayInzN结晶的生长的初期阶段增大Si的添加浓度而在上述氮化物半导体层中形成Si浓度在5×1018/cm3以上的Si高浓度区域。
〔8〕上述〔7〕所述的半导体层叠体的制造方法,在该方法中,上述Si高浓度区域形成为2nm以上的厚度。
〔9〕上述〔7〕或〔8〕所述的半导体层叠体的制造方法,在该方法中,上述缓冲层形成为0.5nm以上、10nm以下的厚度。
〔10〕上述〔7〕所述的半导体层叠体的制造方法,在该方法中,上述缓冲层的上述AlxGayInzN结晶为AlN结晶。
〔11〕上述〔7〕所述的半导体层叠体的制造方法,在该方法中,上述氮化物半导体层的所述AlxGayInzN结晶为GaN。
根据本发明,可提供厚度方向的电阻低的半导体层叠体及其制造方法、以及具有该半导体层叠体的半导体元件。
附图说明
图1是第1实施方式的半导体层叠体的截面图。
图2是第2实施方式的纵型FET的截面图。
图3是第3实施方式的纵型FET的截面图。
图4是第4实施方式的纵型FET的截面图。
图5是第5实施方式的纵型FET的截面图。
图6是第6实施方式的HBT的截面图。
图7是第7实施方式的SBD的截面图。
图8是第8实施方式的LED的截面图。
图9是表示实施例1的Si高浓度区域的Si浓度与电压降的关系的图表。
图10是表示实施例2的AlGaInN缓冲层的厚度与电压降的关系的图表。
图11是表示实施例3的Si高浓度区域的厚度与电压降的关系的图表。
具体实施方式
根据本实施方式,能形成Ga2O3基板、由AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的AlxGayInzN缓冲层和由AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的氮化物半导体层所组成的厚度方向的电阻低的半导体层叠体。本发明者发现,通过提高氮化物半导体层的AlGaInN缓冲层侧的表面附近的给体Si的浓度,半导体层叠体的厚度方向的电阻会降低。此外还发现,通过使AlGaInN缓冲层的厚度为特定的厚度,能进一步降低半导体层叠体的厚度方向的电阻。
AlGaInN缓冲层优选由AlxGayInzN结晶中的AlN结晶(x=1、y=z=0)构成。这种情况下,Ga2O3基板与氮化物半导体层的密着性进一步提高。
此外,氮化物半导体层尤其优选由AlxGayInzN结晶中的结晶品质好的GaN结晶(y=1、x=z=0)构成。
此外,根据本实施方式,通过使用厚度方向的电阻低的半导体层叠体,能形成高性能的半导体元件。下面,对该实施方式的一个例子进行详细说明。
〔第1实施方式〕
图1是第1实施方式的半导体层叠体1的截面图。半导体层叠体1包括Ga2O3基板2、AlGaInN缓冲层3和氮化物半导体层4。
Ga2O3基板2由β-Ga2O3单晶构成。Ga2O3基板2优选为以氧呈六方晶格配置的面即(101)、(-201)、(301)、(3-10)中的任一面为主面的基板。这种情况下,即使AlGaInN缓冲层3薄(例如在10nm以下),也能使表面平坦的AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶在AlGaInN缓冲层3上生长,从而形成氮化物半导体层4。尤其优选Ga2O3基板2的主面为(101)。
AlGaInN缓冲层3可通过用MOCVD(Metal Organic Chemical Vapor Deposition)法等使AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶在Ga2O3基板上外延生长而形成。AlxGayInzN结晶的生长温度为350~600℃,尤其优选为380~500℃。
AlGaInN缓冲层3优选由AlxGayInzN结晶中的AlN结晶(x=1,y=z=0)构成。AlGaInN缓冲层3由AlN结晶构成时,Ga2O3基板2与氮化物半导体层4的密着性进一步提高。
AlGaInN缓冲层3的厚度为0.5~10nm。这种情况下,能大大降低半导体层叠体1的厚度方向的电阻。
氮化物半导体层4可通过用MOCVD法等向AlGaInN缓冲层3上边添加Si边使AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶在该层上外延生长而形成。该AlxGayInzN结晶的生长温度例如为800~1100℃。氮化物半导体层4的厚度例如为2μm。氮化物半导体层4优选由在AlxGayInzN中的结晶品质好的GaN结晶(y=1,x=z=0)构成。
氮化物半导体层4含有Si作为给体。氮化物半导体层4在AlGaInN缓冲层3侧的表面附近具有Si高浓度区域4a。Si高浓度区域4a通过在AlGaInN缓冲层3上的AlxGayInzN结晶生长的初期阶段增大Si的添加量而形成。
Si高浓度区域4a的Si浓度比其他区域4b的Si浓度高。Si高浓度区域4a的Si浓度在5×1018/cm3以上,尤其优选在1×1019/cm3以上。
Si高浓度区域4a的厚度优选在2nm以上。
〔第2实施方式〕
作为第2实施方式,对具有第1实施方式的半导体层叠体1的纵型FET(Field effect transistor)进行说明。
图2是为第2实施方式的半导体元件的纵型FET10的截面图。纵型FET 10包括:具有Ga2O3基板2、AlGaInN缓冲层3以及氮化物半导体层4的半导体层叠体1;形成在氮化物半导体层4的表面(图2中的上侧的面)上的GaN系纵型FET 14;形成在GaN系纵型FET 14上的栅极11及源极12;形成在Ga2O3基板2的表面(图2中的下侧的面)上的漏极13。
需要说明的是,纵型FET 10是可以使用半导体层叠体1形成的纵型FET的一个例子。
〔第3实施方式〕
作为第3实施方式,对具有第1实施方式的半导体层叠体1的MIS(Metal Insulator Semiconductor)栅极结构的纵型FET进行说明。
图3是为第3实施方式的半导体元件的纵型FET 20的截面图。纵型FET 20包括:具有Ga2O3基板2、AlGaInN缓冲层3以及氮化物半导体层4的半导体层叠体1;通过向区域4b中导入p型杂质而形成的p+区域25;形成在氮化物半导体层4的表面(图3中的上侧的面)的Al0.2Ga0.8N层26;通过向Al0.2Ga0.8N层26中导入Si等n型杂质而形成的n+区域27;在Al0.2Ga0.8N层26上介由栅极绝缘膜24而形成的栅极21;与n+区域27及p+区域25连接的源极22;形成在Ga2O3基板2的表面(图3中的下侧的面)上的漏极23。
这里,例如,区域4b的厚度为6μm,Si浓度为1×1018/cm3。此外,例如,p+区域25的厚度为1μm,p型杂质的浓度为1×1018/cm3。Al0.2Ga0.8N层26不含杂质。源极22及漏极23例如由Ti膜与Al膜的层叠体构成。栅极21及栅极绝缘膜24例如分别由Al及SiO2构成。
需要说明的是,纵型FET 20是可以使用半导体层叠体1形成的MIS栅极结构的纵型FET的一个例子。
〔第4实施方式〕
作为第4实施方式,对具有第1实施方式的半导体层叠体1的肖特基栅极结构的纵型FET进行说明。
图4是为第4实施方式的半导体元件的纵型FET 30的截面图。纵型FET 30包括:具有Ga2O3基板2、AlGaInN缓冲层3以及氮化物半导体层4的半导体层叠体1;层积在氮化物半导体层4的表面(图4中的上侧的面)的p+-GaN层34、n+-GaN层35、GaN层36及Al0.2Ga0.8N层37;形成在Al0.2Ga0.8N层37上的栅极31;与p+-GaN层34、n+-GaN层35、GaN层36及Al0.2Ga0.8N层37连接的源极32;形成在Ga2O3基板2的表面(图4中的下侧的面)上的漏极33。
这里,例如,区域4b的厚度为6μm,Si浓度为1×1016/cm3。此外,例如,p+-GaN层34的厚度为1μm,p型杂质的浓度为1×1018/cm3。此外,例如,n+-GaN层35的厚度为200nm,n型杂质的浓度为1×1018/cm3。GaN层36不含杂质,厚度例如为100nm。Al0.2Ga0.8N层37不含杂质,厚度例如为30nm。源极32及漏极33例如由Ti膜与Al膜的层叠体构成。栅极31例如由Ni膜与Au膜的层叠体构成。
需要说明的是,纵型FET 30是可以使用半导体层叠体1形成的肖特基栅极结构的纵型FET的一个例子。
〔第5实施方式〕
作为第5实施方式,对具有第1实施方式的半导体层叠体1的另一肖特基栅极结构的纵型FET进行说明。
图5是为第5实施方式的半导体元件的纵型FET 40的截面图。纵型FET 40包括:具有Ga2O3基板2、AlGaInN缓冲层3以及氮化物半导体层4的半导体层叠体1;形成在氮化物半导体层4的表面(图5中的上侧的面)上的n--GaN层44;形成在n--GaN层44的平坦部上的栅极41;在n--GaN层44的凸部上介由n+-InAlGaN接触层45而形成的源极42;形成在Ga2O3基板2的表面(图5中的下侧的面)上的漏极43。
这里,例如,区域4b的厚度为6μm,Si浓度为1×1018/cm3。此外,例如,n--GaN层44的平坦部的厚度为3μm,n型杂质的浓度为1×1016/cm3。源极42例如由WSi构成。漏极43例如由Ti膜与Al膜的层叠体构成。栅极41例如由PdSi构成。
需要说明的是,纵型FET 40是可以使用半导体层叠体1形成的肖特基栅极结构的纵型FET的一个例子。
〔第6实施方式〕
作为第6实施方式,对具有第1实施方式的半导体层叠体1的异质结双极性晶体管(HBT)进行说明。
图6是为第6实施方式的半导体元件的HBT 50的截面图。HBT 50包括:具有Ga2O3基板2、AlGaInN缓冲层3以及氮化物半导体层4的半导体层叠体1;层积在氮化物半导体层4的表面(图6中的上侧的面)上的n--GaN层54及p+-GaN层55;层积在p+-GaN层55上的n+-Al0.1Ga0.9N层56及n+-GaN层57;形成在p+-GaN层55上的基极51;形成在n+-GaN层57上的发射电极52;形成在Ga2O3基板2的表面(图6中的下侧的面)上的集电极53。
这里,例如,区域4b的厚度为4μm,Si浓度为1×1018/cm3。此外,例如,n--GaN层54的厚度为2μm,n型杂质的浓度为1×1016/cm3。此外,例如,p+-GaN层55的厚度为100nm,p型杂质的浓度为1×1018/cm3。此外,例如,n+-Al0.1Ga0.9N层56的厚度为500nm,n型杂质的浓度为1×1018/cm3。此外,例如,n+-GaN层57的厚度为1μm,n型杂质的浓度为1×1018/cm3。发射电极52例如由Ti膜与Al膜的层叠体构成。集电极53例如由Ti膜与Au膜的层叠体构成。基极51例如由Ni膜与Au膜的层叠体构成。
需要说明的是,HBT 50是可以使用半导体层叠体1形成的异质结双极性晶体管的一个例子。
〔第7实施方式〕
作为第7实施方式,对具有第1实施方式的半导体层叠体1的肖特基势垒二极管(SBD)进行说明。
图7是第7实施方式的半导体元件SBD 60的截面图。SBD 60包括:具有Ga2O3基板2、AlGaInN缓冲层3以及氮化物半导体层4的半导体层叠体1;形成在氮化物半导体层4的表面(图7中的上侧的面)上的n--GaN层63;形成在n--GaN层63上的阳极61;形成在Ga2O3基板2的表面(图7中的下侧的面)上的阴极62。
这里,例如,区域4b的厚度为6μm,Si浓度为1×1018/cm3。此外,例如,n-- GaN层63的厚度为7μm,n型杂质的浓度为1×1016/cm3。阳极61例如由Au构成。阴极62例如由Ti膜与Au膜的层叠体构成。
需要说明的是,SBD 60是可以使用半导体层叠体1形成的肖特基势垒二极管的一个例子。
〔第8实施方式〕
作为第8实施方式,对具有第1实施方式的半导体层叠体1的发光二极管(LED)进行说明。
图8是第8实施方式的半导体元件LED 70的截面图。LED 70包括:具有Ga2O3基板2、AlGaInN缓冲层3以及氮化物半导体层4的半导体层叠体1;层积在氮化物半导体层4的表面(图8中的上侧的面)上的发光层73、p型包覆层74及p型接触层75;形成在p型接触层75上的p电极71;形成在Ga2O3基板2的表面(图8中的下侧的面)上的n电极72。
这里,例如,区域4b的厚度为5μm,Si浓度为1×1018/cm3。区域4b作为n型包覆层起作用。此外,例如,发光层73具有3对由厚8nm的GaN结晶和厚2nm的InGaN结晶构成的多量子阱结构。此外,例如,p型包覆层74由Mg浓度为5.0×1019/cm3的GaN结晶构成,厚度为150nm。此外,例如,p型接触层75由Mg浓度为1.5×1020/cm3的GaN结晶构成,厚度为10nm。
需要说明的是,LED 70是可以使用半导体层叠体1形成的发光二极管的一个例子。
(实施方式的效果)
根据第1实施方式,通过在氮化物半导体层4中形成Si浓度在5×1018/cm3以上的Si高浓度区域4a,可形成厚度方向的电阻低的半导体层叠体1。这可能是由于通过形成Si浓度高的Si高浓度区域4a,电子穿过异质界面的电位势垒,电流容易流动的缘故。
此外,通过使Si高浓度区域4a的厚度在2nm以上,可以进一步降低半导体层叠体的厚度方向的电阻。此外,通过使AlGaInN缓冲层的厚度在0.5nm以上、10nm以下,能进一步降低半导体层叠体的厚度方向的电阻。
此外,根据第2~8实施方式,通过形成具有半导体层叠体1、通电方向为半导体层叠体1的厚度方向的纵型半导体元件,能得到高性能的纵型半导体元件。
下面,按实施例1~4所示,对本实施方式的半导体层叠体1进行评价。
实施例1
在实施例1中,形成Si高浓度区域4a的杂质浓度不同的多个半导体层叠体1,调查Si高浓度区域4a的杂质浓度与半导体层叠体1的厚度方向的电阻的关系。各半导体层叠体1的形成工序如下。
首先,将Ga2O3基板2设置在MOCVD装置内,在Ga2O3基板2上使AlN结晶在生长温度450℃下生长,形成厚5nm的AlGaInN缓冲层3。
然后,边向AlGaInN缓冲层3添加Si边使GaN结晶在生长温度1050℃下生长,形成厚2μm的氮化物半导体层4。此时,提高GaN结晶生长初期的Si添加浓度,形成10nm厚的Si高浓度区域4a。使区域4b的杂质浓度为2×1018/cm3。
接着,在Ga2O3基板2及氮化物半导体层4的表面,用光刻法及蒸镀技术形成各电极。然后,在电极间施加电压,测定电流密度为200A/cm2时的电压降。
图9是表示Si高密度区域4a的Si浓度与电流密度为200A/cm2时的电压降的关系的图表。如图9所示,Si高浓度区域4a的Si浓度越高,电压降越小,即,半导体层叠体1的厚度方向的电阻越低。
由此可以知道,尤其是在Si高浓度区域4a的Si浓度在5×1018/cm3以上时,半导体层叠体1的厚度方向的电阻低。此外,还可知道,若Si高浓度区域4a的Si浓度在1×1019/cm3以上,则电压降的值几乎恒定。
实施例2
在实施例2中,形成AlGaInN缓冲层3的厚度在0.5~20nm的范围内的不同的多个半导体层叠体1,调查AlGaInN缓冲层3的厚度与半导体层叠体1的厚度方向的电阻的关系。各半导体层叠体1的形成工序如下。
首先,将Ga2O3基板2设置在MOCVD装置内,在Ga2O3基板2上使AlN结晶在生长温度450℃下生长,形成AlGaInN缓冲层3。
然后,边向AlGaInN缓冲层3添加Si边使GaN结晶在生长温度1050℃下生长,形成厚2μm的氮化物半导体层4。此时,提高GaN结晶生长初期的Si添加浓度,形成10nm厚的Si高浓度区域4a。使Si高浓度区域4a及区域4b的Si浓度分别为2×1019/cm3、2×1018/cm3。
接着,在Ga2O3基板2及氮化物半导体层4的表面,用光刻法及蒸镀技术形成各电极。然后,在电极间施加电压,测定电流密度为200A/cm2时的电压降。
图10是表示AlGaInN缓冲层3的厚度与电流密度为200A/cm2时的电压降的关系的图表。如图10所示,AlGaInN缓冲层3的厚度越小,电压降越小,即,半导体层叠体1的厚度方向的电阻越低。
由此可以知道,尤其是在AlGaInN缓冲层3的厚度在10nm以下时,半导体层叠体1的厚度方向的电阻低。还可知道,AlGaInN缓冲层3的厚度厚时,即使是在Si高浓度区域4a的Si浓度充分高(2×1019/cm3)的情况下,半导体层叠体1的厚度方向的电阻也会增大。
实施例3
在实施例3中,形成Si高浓度区域4a的厚度在0~10nm的范围内的不同的多个半导体层叠体1,调查Si高浓度区域4a的厚度与半导体层叠体1的厚度方向的电阻的关系。各半导体层叠体1的形成工序如下。
首先,将Ga2O3基板2设置在MOCVD装置内,在Ga2O3基板2上使AlN结晶在生长温度450℃下生长,形成厚5nm的AlGaInN缓冲层3。
然后,边向AlGaInN缓冲层3添加Si边使GaN结晶在生长温度1050℃下生长,形成厚2μm的氮化物半导体层4。此时,提高GaN结晶生长初期的Si添加浓度,形成Si高浓度区域4a。使Si高浓度区域4a及区域4b的Si浓度分别为2×1019/cm3、2×1018/cm3。
接着,在Ga2O3基板2及氮化物半导体层4的表面,用光刻法及蒸镀技术形成各电极。然后,在电极间施加电压,测定电流密度为200A/cm2时的电压降。
图11是表示Si高浓度区域4a的厚度与电流密度为200A/cm2时的电压降的关系的图表。如图11所示,Si高浓度区域4a的厚度越大,电压降越小,即,半导体层叠体1的厚度方向的电阻越低。
由此可以知道,尤其是在Si高浓度区域4a的厚度在2nm以上时,半导体层叠体1的厚度方向的电阻低。
实施例4
在实施例4中,形成第8实施方式的LED 70,测定顺方向的电压降VF。
首先,准备好添加有Si的n型β-Ga2O3基板作为Ga2O3基板2。这里,β-Ga2O3基板的厚度为400μm,主面为(101)。
接着,在β-Ga2O3基板上,使用MOCVD装置,在生长温度450℃下使AlN结晶生长5nm,形成AlGaInN缓冲层3。接着,在生长温度1050℃下使Si浓度2.0×1019/cm3的GaN结晶生长10nm,形成Si高浓度区域4a,然后,使Si浓度1.0×1018/cm3的GaN结晶生长5μm,形成作为n型包覆层的区域4b。
接着,在生长温度750℃形成3对由厚8nm的GaN结晶和厚2nm的InGaN结晶构成的多量子阱结构,再使GaN结晶生长10nm,形成发光层73。
接着,在生长温度1000℃下使Mg浓度为5.0×1019/cm3的GaN结晶生长150nm,形成p型包覆层74。接着,在生长温度1000℃下使Mg浓度为1.5×1020/cm3的GaN结晶生长10nm,形成p型接触层75。
在上述工序中,使用TMG(三甲基镓)作为Ga原料,使用TMI(三甲基铟)作为In原料,使用SiH3CH3(单甲基硅烷)气体作为Si原料,使用Cp2Mg(环戊二烯基镁)作为Mg原料,使用NH3(氨)气体作为N原料。
对通过上述操作制成的LED外延晶圆的表面,使用ICP-RIE装置,从p型接触层75侧起到较发光层73深的位置为止进行蚀刻,形成台面(mesa)形状。接着,用溅射装置在发光层73的侧面形成SiO2膜。再用蒸镀装置形成分别与p型接触层75及Ga2O3基板2进行欧姆接触的的电极,得到光提取面在Ga2O3基板2一侧的LED70。
此外,作为比较例,形成AlGaInN缓冲层3的厚度为20nm、不含Si高浓度区域4a的LED。
然后,使用Ag膏将LED 70及比较例的LED分别安装到管式装置(can type stem)上,测定20mA的电流IF流过时的电压降VF。结果发现,比较例的现有式样的LED的电压降VF为4.32V,与此相对,LED 70的电压降VF为2.94V,显示出达到可实际用作发光元件的水平的电压降VF。
以上对本发明的实施方式及实施例做了说明,但以上所记载的实施方式及实施例并不是对权利要求书中的发明做出限定。此外,应当留意的是,实施方式及实施例中说明的特征组合的全部并不一定是达到发明目的的手段所必须的。
符号说明:
1‥‥半导体层叠体,2‥‥Ga2O3基板,3‥‥AlGaInN缓冲层,4‥‥氮化物半导体层,4a‥‥Si高浓度区域,4b‥‥区域,10、20、30、40‥‥纵型FET,50‥‥HBT,60‥‥SBT,70‥‥LED 。
Claims (11)
1.半导体层叠体,其具有Ga2O3基板、
所述Ga2O3基板上的由AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的缓冲层和
所述缓冲层上的由含有Si的AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的氮化物半导体层,
所述氮化物半导体层在所述缓冲层侧的部分区域具有Si浓度在5×1018/cm3以上的Si高浓度区域。
2.根据权利要求1所述的半导体层叠体,其特征在于,所述Si高浓度区域的厚度在2nm以上。
3.根据权利要求1或2所述的半导体层叠体,其特征在于,所述缓冲层的厚度在0.5nm以上、10nm以下。
4.根据权利要求1所述的半导体层叠体,其特征在于,所述缓冲层的所述AlxGayInzN结晶为AlN结晶。
5.根据权利要求1所述的半导体层叠体,其特征在于,所述氮化物半导体层的所述AlxGayInzN结晶为GaN结晶。
6.半导体元件,其包含半导体层叠体,所述半导体层叠体具有Ga2O3基板、所述Ga2O3基板上的由AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的缓冲层和所述缓冲层上的由含有Si的AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶构成的氮化物半导体层,所述氮化物半导体层在所述缓冲层侧的部分区域具有Si浓度在5×1018/cm3以上的Si高浓度区域,
在所述半导体层叠体的厚度方向通电。
7.半导体层叠体的制造方法,其包括在Ga2O3基板上使AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶外延生长、形成缓冲层的工序和
边向所述缓冲层上添加Si边使AlxGayInzN(0≤x≤1,0≤y≤1,0≤z≤1,x+y+z=1)结晶生长、形成氮化物半导体层的工序,
通过在所述AlxGayInzN结晶生长的初期阶段增大Si的添加浓度而在所述氮化物半导体层中形成Si浓度在5×1018/cm3以上的Si高浓度区域。
8.根据权利要求7所述的半导体层叠体的制造方法,其特征在于,所述Si高浓度区域形成为2nm以上的厚度。
9.根据权利要求7或8所述的半导体层叠体的制造方法,其特征在于,所述缓冲层形成为0.5nm以上、10nm以下的厚度。
10.根据权利要求7所述的半导体层叠体的制造方法,其特征在于,所述缓冲层的所述AlxGayInzN结晶为AlN结晶。
11.根据权利要求7所述的半导体层叠体的制造方法,其特征在于,所述氮化物半导体层的所述AlxGayInzN结晶为GaN。
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