WO2012136027A1 - 一种sonos快闪存储器及其制备方法和操作方法 - Google Patents

一种sonos快闪存储器及其制备方法和操作方法 Download PDF

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WO2012136027A1
WO2012136027A1 PCT/CN2011/077199 CN2011077199W WO2012136027A1 WO 2012136027 A1 WO2012136027 A1 WO 2012136027A1 CN 2011077199 W CN2011077199 W CN 2011077199W WO 2012136027 A1 WO2012136027 A1 WO 2012136027A1
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layer
silicon
flash memory
substrate
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蔡一茂
黄如
秦石强
田明
唐粕人
唐昱
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Peking University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Definitions

  • the present invention relates to the field of non-volatile semiconductor memory technology in a very large scale integrated circuit, and in particular to a SONOS type flash memory using a TFET (Tunneling Field Effective Transistor). Background technique
  • Flash Memory also known as flash memory
  • flash memory has been around for decades. During this period, while being widely used, improvements are constantly being made. In the order of time, the following two basic forms appear in order:
  • This type of flash memory uses a polysilicon floating gate for electronic storage.
  • the specific structure is as shown in FIG. 1.
  • the tunnel oxide layer 104, the polysilicon floating gate 105, the blocking oxide layer 106 and the control gate 107 are sequentially arranged above the channel. . It should be noted that the electrons of the structured flash memory are continuously distributed on the floating gate.
  • the difference from the floating gate flash memory is that the structure of the isolated trap type flash memory for storing electrons is a silicon nitride trap layer instead of a polysilicon floating gate, and the rest of the structure is substantially the same as that of the floating gate type flash memory (see FIG. 1 ), therefore,
  • the floating gate type flash memory is also called a SONOS (silicon-oxide-nitride-oxide-silicon) type flash.
  • the electrons deposited in the silicon nitride trap layer are localized and not continuous. Therefore, if the tunneling oxide layer is damaged and a leak path occurs, only the electrons in the channel region leak through the leak channel, and the electrons stored in other portions are not reduced, thus improving the holding characteristics of the entire device.
  • the latter structure has a larger performance improvement than the former one, especially in terms of maintaining characteristics, and thus has become a research hotspot in recent years.
  • the fast flash memory of this SONOS structure also has the same low programming efficiency, high power consumption, and difficulty in continuing to scale down as the first type of flash memory.
  • TFET Tunneling Filed Effect Transistor
  • the structure is different from the traditional MOS transistor in that the source and drain are two different doping types, and the lightly doped N-type silicon (N-type silicon) and the lightly doped P-type silicon (P-type) Silicon) can be used as a substrate.
  • 2 is a schematic view showing the structure of a TFET using N-type silicon as the substrate 201, which is respectively N+ terminal 202 at both ends of the silicon plane.
  • P+ terminal 203 above which is gate oxide layer 204 and polysilicon gate 205.
  • the energy band along the channel direction is as shown in Fig.
  • the entire transistor is turned off.
  • a sufficient negative bias and a positive bias are applied to the P+ terminal 203 and the N+ terminal 202, respectively, and the polysilicon gate 205 is properly biased, the energy band along the channel direction is as shown in Fig. 3(b). If the applied bias voltage is sufficient to bend the energy band at the junction of the P+ terminal 203 and the channel such that band to band tunneling occurs, electrons will tunnel from the valence band of the P+ terminal 203 to the channel region. The band is then drifted to the N+ terminal 202 by an electric field in the direction of the channel.
  • the transistor is used as an N-type TFET in which the N+ terminal 202 serves as a drain and the P+ terminal 203 serves as a source.
  • the energy band along the channel direction is as shown in Fig. 3(c). If the applied bias voltage is sufficient to bend the energy band at the junction of the N+ terminal 202 and the channel such that band to band tunneling occurs, electrons will tunnel from the valence band of the channel region to the N+ terminal 202, leaving The underlying holes are quickly swept to the P+ end 203 under the action of a strong electric field.
  • the transistor is used as a P-type TFET in which the P+ terminal 203 serves as a drain and the N+ terminal 202 serves as a source. Summary of the invention
  • the present invention provides a high-performance SONOS flash memory in combination with tunneling field effect transistors in view of the numerous challenges faced by conventional flash memories, which can improve programming efficiency, reduce programming power consumption, and suppress punch-through effects while improving retention characteristics. .
  • a SONOS flash memory includes a substrate, a source drain and a channel, the channel is located between the source and the drain, and the tunnel is followed by a tunneling oxide layer, a silicon nitride trap layer, a blocking oxide layer and a polysilicon control gate;
  • the substrate is lightly doped silicon;
  • the source and drain are of different types, the source end is a P+ region, and the drain end is an N+ region.
  • lightly doped P-type silicon P-type silicon
  • lightly doped N-type silicon N-type silicon
  • the invention also provides a method for preparing the above SONOS flash memory, comprising the following steps:
  • etching step 2) forming a polysilicon layer, a second silicon dioxide layer, a silicon nitride layer and a first silicon dioxide layer to form a gate stack structure;
  • step 1) may employ a P-type or N-type bulk silicon substrate.
  • the first silicon dioxide layer in the above step 2) may be formed by deposition or thermal growth.
  • a sacrificial oxide layer may be thermally grown on the silicon substrate before the formation of the first silicon oxide layer, and the sacrificial oxide layer is removed by wet etching, and then thermally grown or deposited.
  • the silicon dioxide layer acts as a tunneling oxide layer.
  • the SONOS flash memory of the present invention whether it is a P-type silicon substrate or an N-type silicon substrate, has the same operation method, and is briefly described as follows:
  • the P+ region is grounded, the N+ region is applied with a positive bias, and the control gate is applied with a positive bias.
  • this bias similar to an N-type TFET, electrons will tunnel from the valence band of the P+ region to the conduction band of the channel.
  • the electrons entering the channel region drift in the channel direction toward the N+ region under the action of the transverse electric field.
  • the energy obtained by some electrons is high enough to exceed the barrier height of Si/Si0 2 , pass through the tunneling oxide layer and enter the silicon nitride trap layer, and Capture, complete programming of the memory unit.
  • the N+ region and the P+ region apply a positive bias, and the control gate applies a negative bias. Under such bias conditions, FN tunneling will occur, causing electrons in the silicon nitride trap layer to enter the silicon substrate, completing the erasing of the memory cells.
  • the control gate When reading, a positive bias is applied to the N+ region, the P+ region is grounded, and the control gate applies a small positive bias.
  • the setting of the control bias requires that the current be read from the N+ region without misprogramming.
  • the amount of electrons trapped by the silicon nitride trap layer affects the current read from the drain (N+ region). In this way, the current read by the drain reflects the amount of electrons trapped by the silicon nitride trap layer, and the two states are distinguished to realize the storage function.
  • the invention combines a tunneling field effect transistor (TFET) to propose a SONOS flash memory structure, which has good compatibility with the existing standard CMOS process, and has the advantages of good maintenance characteristics of the general SONOS flash memory. At the same time, it can effectively improve programming efficiency, reduce power consumption, suppress punch-through effect, etc., and ideal for small size characteristics.
  • TFET tunneling field effect transistor
  • the energy band at the intersection of the P+ region and the channel will be obviously bent, and band to band tunneling will occur.
  • )phenomenon there will be a large voltage drop at the bend of the energy band, that is, the peak of the transverse electric field is located near the P+ region of the source, so that when the electron enters the channel, a large amount of energy can be obtained to cross the Si/ The barrier of Si0 2 enters the silicon nitride layer.
  • the peak of the transverse electric field along the channel direction is located near the drain end.
  • the energy is very low, which is not enough to cross the Si/Si0 2 barrier.
  • the energy is very low, which is not enough to cross the Si/Si0 2 barrier.
  • the drain end since it is very close to the drain end, there is a great chance that it is sucked away by the drain end, which greatly reduces the programming efficiency.
  • the electrons from the source P+ region of the flash memory of the present invention are efficiently injected into the silicon nitride trap layer, which greatly reduces the drain current which is ineffective for programming, and shortens the programming time. , to achieve the purpose of reducing power consumption.
  • the SONOS structure has better retention characteristics than the floating gate type flash memory.
  • the traditional MOS FET-based flash memory will have source and drain junction depletion in small size.
  • the regions are connected to each other, generating a large current flowing from the source to the drain, affecting the normal implementation of the function.
  • the source junction and the drain junction are not present at the same time, the Punch-Through Effect can be largely suppressed.
  • Figure 1 is a schematic cross-sectional view of a conventional flash memory (floating gate type and split trap type), in which:
  • FIG. 2 is a schematic cross-sectional structure of the TFET, wherein:
  • 201-body silicon substrate N-doped
  • 202-N+ terminal drain terminal for N-type TFET, source terminal for P-type TFET
  • 203-P+ terminal drain terminal for P-type TFET, N-type TFET is used as the source terminal
  • 204 gate oxide layer
  • 205 polysilicon gate.
  • Figure 3 is an energy band diagram of the TFET shown in Figure 2 along the channel direction under various bias conditions, where:
  • (b) is the energy band diagram of the device in Figure 2 as an N-type TFET (N+ terminal 202 is connected to forward voltage, P+ terminal 203 is grounded or negative voltage, and polysilicon gate 205 is connected to higher forward voltage);
  • FIG. 4 is a schematic structural diagram of a SONOS flash memory of the present invention, wherein:
  • FIGS. 5(a)-(c) are schematic diagrams showing the structure of products corresponding to the steps of the process of preparing a SONOS flash memory for preparing a P-type silicon substrate, wherein:
  • a flash memory of a P-type silicon substrate as an example to further illustrate the preparation of the flash memory of the present invention, and the basic operation mode of the flash memory, but does not limit the scope of the present invention.
  • the present invention is equally applicable to a flash memory using N-type silicon as a substrate.
  • the structure of the flash memory prepared in this embodiment is as shown in FIG. 4, and the P-type silicon 401 is used as a substrate.
  • the P+ region and the N+ region are both ends of the silicon plane, and the channel region is in the middle, and the channel is sequentially To tunnel the oxide layer, the silicon nitride trap layer, Block oxide layer and polysilicon control gate.
  • the entire device is a TFET type SONOS flash memory.
  • the preparation of the above flash memory includes the following steps:
  • RTA rapid thermal annealing
  • Arsenic (402) and boron (403) implantation are performed on both sides of the gate to form a heavily doped N+ region 402 and a P+ region 403, as shown in Fig. 5(c).
  • Subsequent steps are conventional processes: depositing a low-oxygen layer, etching lead holes, sputtering metal, forming metal lines, alloys, passivation, etc., and finally forming a testable flash memory cell.
  • control gate 407 applies a suitable positive voltage
  • P+ region 403 is grounded
  • N+ region 402 applies a positive voltage.
  • electrons of the P+ region 403 will tunnel into the channel region and then flow toward the N+ region 402 along the channel direction.
  • the applied bias is appropriate, some of the electrons get enough energy to cross the barrier of Si/Si0 2 into the silicon nitride trap layer 405 and be trapped by the traps to complete the programming of the device.
  • Control gate 407 applies a suitable negative voltage
  • P+ region 403 and N+ region 402 apply a positive voltage. Under such bias conditions, electrons located in the silicon nitride trap layer 405 tunnel into the substrate to complete the erase of the device.
  • the device's memory state is read using an N-TFET-like approach.
  • the control gate 407 adds a small positive voltage, the P+ region 403 is grounded, and the N+ region 402 is applied with a smaller forward voltage.
  • the bias setting requires reading the current of the N+ region 402 without misprogramming. .
  • the current read from the N+ region 402 terminal is small; when the electrons in the silicon nitride trap layer 405 are erased, the current read from the N+ region 402 terminal is compared. Large, this enables reading of two storage states.
  • the entire device can work normally and complete the storage function.

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Description

一种 SONOS快闪存觸及其制备^ ¾和操作方法
技术领域
本发明属于超大规模集成电路中的非挥发型半导体存储器技术领域，具体涉及一种采用 了 TFET (Tunneling Field Effective Transistor) 的 SONOS型快闪存储器。 背景技术
在当前各种消费类电子产品广泛兴起之际， 市场对非挥发性半导体存储器的需求也在不 断增加。 作为一种非常重要的非挥发性存储器， 快闪存储器近来成为了业界的宠儿。
快闪存储器（Flash Memory, 也称为闪存） 自从其出现到今天已有几十年的时间了。 在这 期间， 在得到广泛应用的同时， 也在不断地做出改进。 按照时间的先后顺序， 依次出现如下 两种基本形态：
1.浮栅型闪存 (Floating Gate Flash Memory)
这种结构的快闪存储器使用多晶硅浮栅实现电子的存储。 其具体结构如图 1所示， 在体 硅衬底 101上， 除了源 102、漏 103之外， 沟道以上依次为隧穿氧化层 104、多晶硅浮栅 105、 阻挡氧化层 106和控制栅 107。 需要指出的是， 该结构快闪存储器的电子在浮栅上是连续分 布的。
2. 分离陷阱型闪存 (Discrete Trap Flash Memory)
与浮栅型闪存的区别之处在于， 分离陷阱型闪存用于存储电子的结构为氮化硅陷阱层而 非多晶硅浮栅， 其余结构与浮栅型闪存基本相同 （参见图 1 )， 因此， 浮栅型闪存也被称为 SONOS ( silicon-oxide-nitride-oxide-silicon )型快闪。氮化硅陷阱层中存入的电子是局域化的， 并不连续。 因此， 如果隧穿氧化层受到损伤而出现泄漏通道时， 仅仅是通道区域的电子通过 该泄漏通道泄漏掉， 而其他部分存储的电子并不减少， 这样就提高了整个器件的保持特性。
需要说明的是后一种结构相比于前一种有着较大的性能改进，尤其是在保持特性方面， 因 此近年来成为了一大研究热点。 但由于最基本的编程机理限制， 这种 SONOS结构的快闪存 储器也和第一类闪存一样存在编程效率低、 功耗高和难以继续等比例缩小等问题。
另一方面， 隧穿场效应晶体管 （Tunneling Filed Effect Transistor, 记作 TFET) 是一种基 于量子隧穿效应的晶体管。 在结构上区别于传统的 MOS 晶体管之处在于源、 漏为两种不同 的掺杂类型， 并且轻掺杂的 N型硅 （N-型硅） 和轻掺杂的 P型硅（P-型硅） 都可以作为衬底 使用。 图 2为以 N-型硅作衬底 201的 TFET结构示意图， 在硅平面的两端分别为 N+端 202 和 P+端 203， 沟道之上依次为栅氧化层 204和多晶硅栅 205。在各端未接外部电压的情况下， 其沿沟道方向的能带如图 3 (a)所示， 此时整个晶体管处于关断状态。 当分别在 P+端 203 和 N+端 202施加足够负偏压和正偏压，且多晶硅栅 205加适当正偏压的情况下，沿沟道方向 的能带如图 3 (b)所示。如果施加的偏压足以让 P+端 203和沟道交接处的能带弯曲以致发生 带带隧穿 （Band to Band tunneling) 时， 电子会从 P+端 203的价带隧穿到沟道区的导带上， 进而在沿沟道方向的电场作用下漂移至 N+端 202。 此时， 该晶体管是作为 N型 TFET使用， 其中 N+端 202作为漏， P+端 203作为源。当分别在 P+端 203和 N+端 202施加足够负偏压和 正偏压， 且多晶硅栅 205加适当负偏压的情况下， 沿沟道方向的能带如图 3 (c)所示。 如果 施加的偏压足以让 N+端 202 和沟道交接处的能带弯曲以致发生带带隧穿 （Band to Band tunneling )时， 电子会从沟道区的价带隧穿到 N+端 202， 留下的空穴会在强电场的作用下迅 速扫至 P+端 203。此时， 该晶体管是作为 P型 TFET使用， 其中 P+端 203作为漏， N+端 202 作为源。 发明内容
本发明针对传统快闪存储器面临的众多挑战， 结合隧穿场效应晶体管提出一种高性能 SONOS快闪存储器， 在改善保持特性的同时， 可以有效提高编程效率、 降低工作功耗、抑制 穿通效应等。
本发明的技术方案如下：
一种 SONOS快闪存储器， 包括衬底、源漏和沟道， 沟道位于源漏之间， 沟道之上依次为 隧穿氧化层、 氮化硅陷阱层、 阻挡氧化层和多晶硅控制栅； 其特征在于， 所述衬底为轻掺杂 硅； 源漏的惨杂类型不同， 源端为 P+区， 漏端为 N+区。
上述快闪存储器， 轻掺杂 P型硅 （P-型硅） 和轻掺杂 N型硅 （N-型硅） 都可以作为衬底 使用。
本发明还提供了一种制备上述 SONOS快闪存储器的方法， 包括以下步骤：
1 ) 浅槽隔离轻掺杂硅衬底形成有源区；
2) 在衬底上依次形成第一二氧化硅层（隧穿氧化层）、氮化硅层（陷阱层）、第二二氧化 硅层 （阻挡氧化层） 和多晶硅层 （控制栅）；
3 ) 对多晶硅层进行重掺杂和热退火 （RTA)激活杂质；
4) 刻蚀步骤 2)形成的多晶硅层、 第二二氧化硅层、 氮化硅层和第一二氧化硅层， 形成 栅堆栈结构；
5 ) 在栅堆栈结构的两端分别进行 P+注入和 N+注入， 形成源漏。 上述步骤 1 ) 可以采用 P-型或 N-型体硅衬底。
上述步骤 2) 中第一二氧化硅层可以通过淀积或热生长的方式形成。 为改善沟道表面性 质， 在形成第一二氧化硅层之前可以在硅衬底上先热生长一层牺牲氧化层， 并湿法腐蚀去掉 该牺牲氧化层， 然后再热生长或淀积一层二氧化硅层作为隧穿氧化层。
本发明的 SONOS快闪存储器， 无论是 P-型硅衬底还是 N-型硅衬底， 具体的操作方法是 一样的， 简述如下：
编程时， P+区接地， N+区施加正偏压， 控制栅施加正偏压。 在这种偏压作用下， 类似于 N型 TFET, 电子将从 P+区的价带隧穿到沟道的导带上。 进入沟道区域的电子在横向电场的 作用下沿沟道方向朝 N+区漂移。在这一过程中由于外加电场的作用，会有部分电子获得的能 量足够高， 以至于超过 Si/Si02的势垒高度， 穿过隧穿氧化层进入到氮化硅陷阱层中， 并被捕 获， 完成存储单元的编程。
擦除时， N+区、 P+区施加正偏压， 控制栅施加负偏压。 这样的偏置条件下将会发生 FN 隧穿， 使得氮化硅陷阱层中的电子进入硅衬底， 完成对存储单元的擦除。
读取时， 在 N+区施加正偏压， P+区接地， 控制栅施加较小的正偏压。 控制偏压的设置， 要求在不进行误编程的前提下从 N+区读出电流。 氮化硅陷阱层捕获电子的多少会影响漏端 (N+区）读出的电流。 这样， 漏端读出的电流就反映了氮化硅陷阱层捕获电子的多少， 完成 了两个状态的区分， 实现了存储的功能。
本发明结合隧穿场效应晶体管 （TFET) 提出了一种 SONOS快闪存储器结构， 其与现有 的标准 CMOS工艺有着较好的兼容性， 并且在具有一般 SONOS快闪存储器保持特性较好的 优势的同时， 可以有效地提高编程效率、 降低功耗、 抑制穿通效应等， 且小尺寸特性理想。
以 P-型硅衬底的 SONOS快闪存储器为例， 在编程偏置条件下， P+区与沟道交接处的能 带将发生很明显的弯曲， 并出现带带隧穿（Band to Band tunneling)现象。此时在能带的弯曲 处， 将有很大的电压降， 即横向电场的峰值位于源端 P+区附近， 这样就使得电子刚进入沟道 时，就可以获得很大的能量以便越过 Si/Si02 的势垒进入氮化硅层。而传统的 SONOS型快闪 存储器在编程时， 沿沟道方向的横向电场峰值位于漏端附近， 电子在到达该峰值位置之前， 能量非常低， 不足以越过 Si/Si02势垒， 而当到达此峰值位置， 获得较大的能量时， 由于非 常靠近漏端， 又会有很大的几率被漏端吸走， 大大降低了编程效率。
在编程效率大大提高的情况下， 本发明的快闪存储器从源端 P+区出来的电子被高效率的 注入进氮化硅陷阱层， 大大降低了对编程无效的漏端电流， 縮短了编程时间， 达到了降低功 耗的目的。 同时由于采用了 SONOS结构相比于浮栅型的快闪存储器具有更好的保持特性。
另外， 传统的基于 MOS场效应晶体管的快闪存储器在小尺寸下， 会发生源结和漏结耗尽 区相连通， 产生很大的从源流向漏的电流， 影响功能的正常实现。 而本发明的快闪存储器， 由于源结和漏结不会同时存在， 可以在很大程度上抑制穿通效应 （Punch-Through Effect)。 附图说明
图 1是传统快闪存储器 （浮栅型和分离陷阱型） 的剖面结构示意图， 其中：
101—体硅衬底； 102—漏端； 103—源端； 104—隧穿氧化层； 105—多晶硅浮栅（对应于 浮栅型闪存）或氮化硅陷阱层（对应于分离陷阱型闪存）； 106—阻挡氧化层； 107—多晶硅控 图 2是 TFET的剖面结构示意图， 其中：
201—体硅衬底 （N-掺杂）； 202— N+端 （N型 TFET时做漏端， P型 TFET时做源端）； 203— P+端 （P型 TFET时做漏端， N型 TFET时做源端）； 204—栅氧化层； 205—多晶硅栅。
图 3是图 2所示 TFET在各种偏置条件下沿沟道方向的能带图， 其中：
(a)为各端未接偏置时的能带图；
(b)为图 2中的器件作为 N型 TFET时的能带图 （N+端 202接正向电压， P+端 203接地 或负向电压， 多晶硅栅 205接较高的正向电压）；
(c)为图 2中的器件作为 P型 TFET时的能带图（N+端 202接正向电压， P+端 203接地或 负向电压， 多晶硅栅 205接较高的负向电压）。
图 4是本发明的 SONOS快闪存储器的结构示意图， 其中：
401— N-或 P-型硅衬底； 402— N+区； 403— P+区； 404—隧穿氧化层； 405—氮化硅陷阱 层； 406—阻挡氧化层； 407—多晶硅控制栅。
图 5(a)-(c)是实施例制备 P-型硅衬底的 SONOS快闪存储器的工艺流程各步骤对应的产品 结构示意图， 其中：
401— P-型硅衬底； 402— N+区； 403— P+区； 404—隧穿氧化层； 405—氮化硅陷阱层； 406—阻挡氧化层； 407—多晶硅控制栅。 具体实施方式
以下结合附图， 以 P-型硅衬底的快闪存储器为例， 来进一步说明本发明快闪存储器的制 备， 以及这种快闪存储器的基本工作模式， 但并不因此限制本发明的范围， 本发明同样适用 于以 N-型硅为衬底的快闪存储器。
本实施例所制备的快闪存储器的结构如图 4所示， P-型硅 401作为衬底使用， 在硅平面 的两端为 P+区域和 N+区， 中间为沟道区域， 沟道上面依次为隧穿氧化层， 氮化硅陷阱层， 阻挡氧化层和多晶硅控制栅。 整个器件为一种 TFET型的 SONOS快闪存储器。
上述快闪存储器的制备包括以下步骤：
( 1 ) 对单抛 P-型硅衬底 401进行浅漕隔离 （STI), 形成有源区；
(2) 热生长一层牺牲氧化层以改善沟道表面质量， 随后氢氟酸漂洗掉该牺牲氧化层； 然后热生长氧化层 404， 厚度 5纳米， 再依次淀积氮化硅层 405 (厚度 8纳米）、 氧化层 406 (厚度 9纳米） 和多晶硅层 407 (厚都 50纳米）， 如图 5 (a) 所示；
(3 ) 对顶层多晶硅 407进行重掺杂， 接着快速热退火 （RTA)激活杂质；
(4) 刻蚀多晶硅层 407、 二氧化硅层 406、 氮化硅层 405和二氧化硅层 404形成图 5
(b) 所示的栅堆栈结构；
(5 ) 在栅的两侧分别进行砷 （402) 和硼 （403) 注入， 形成重掺杂的 N+区 402和 P+ 区 403， 如图 5 (c) 所示。
之后的歩骤都是常规的工艺流程： 淀积低氧层， 刻蚀引线孔， 溅射金属， 形成金属线， 合金， 钝化等， 最后形成可测试的闪存单元。
以下用来说明上述器件的具体工作模式。
编程： 本器件在编程时， 控制栅 407施加合适的正电压， P+区 403接地， N+区 402施加 正电压。 在这样的偏置条件下， P+区 403的电子会通过隧穿进入到沟道区域， 然后沿着沟道 方向朝 N+区 402流动。 当所加偏置合适时， 就会有部分电子获得足够的能量， 越过 Si/Si02 的势垒进入到氮化硅陷阱层 405中， 并被其中的陷阱捕获， 完成器件的编程。
擦除：本器件的擦除通过 FN的方式实施。控制栅 407施加合适的负电压， P+区 403和 N+ 区 402施加正电压。 在这样的偏置条件下， 位于氮化硅陷阱层 405中的电子就会隧穿进入衬 底中去， 完成对器件的擦除。
读取： 器件存储状态的读取采用类似 N-TFET的方式。 读取时， 控制栅 407加较小的正 电压， P+区 403接地， N+区 402加较小的正向电压， 偏压的设置要求在不进行误编程的前提 下读出 N+区 402的电流。 当氮化硅陷阱层 405中捕获有电子时， 从 N+区 402端读出的电流 较小； 当氮化硅陷阱层 405中的电子被擦除后， 从 N+区 402端读出的电流较大， 这样就实现 了两种存储状态的读取。
通过上述的编程、 擦除和读取操作， 整个器件就可以正常的工作， 完成存储的功能。

Claims

权 利 要 求 书
1. 一种 SONOS快闪存储器， 包括衬底、 源漏和沟道， 沟道位于源漏之间， 沟道之上依次为 隧穿氧化层、氮化硅陷阱层、 阻挡氧化层和多晶硅控制栅； 其特征在于， 所述衬底为轻掺 杂硅； 源漏的掺杂类型不同， 源端为 P+区， 漏端为 N+区。
2. 如权利要求 1所述的快闪存储器， 其特征在于， 所述衬底为轻掺杂 P型硅或轻掺杂 N型 硅。
3. 一种 SONOS快闪存储器的制备方法， 包括以下步骤：
1) 浅槽隔离轻掺杂硅衬底形成有源区；
2) 在衬底上依次形成第一二氧化硅层、 氮化硅层、 第二二氧化硅层和多晶硅层；
3) 对多晶硅层进行重掺杂和热退火激活杂质；
4) 刻蚀歩骤 2)形成的多晶硅层、第二二氧化硅层、氮化硅层和第一二氧化硅层， 形成栅 堆栈结构；
5) 在栅堆栈结构的两端分别进行 P+注入和 N+注入， 形成源漏。
4. 如权利要求 3所述的制备方法，其特征在于， 步骤 1)所述轻掺杂硅衬底是 P-型或 N-型体 硅衬底。
5. 如权利要求 3所述的制备方法， 其特征在于， 步骤 2)通过淀积或热生长的方式形成第一 二氧化硅层。
6. 如权利要求 3所述的制备方法， 其特征在于， 步骤 2)在形成第一二氧化硅层之前， 在硅 衬底上先热生长一层牺牲氧化层， 然后湿法腐蚀去掉该牺牲氧化层。
7. 权利要求 1所述 SONOS快闪存储器的操作方法， 包括： 编程时， P+区接地， N+区施加 正偏压， 多晶硅控制栅施加正偏压， 使部分电子穿过隧穿氧化层进入到氮化硅陷阱层中， 并被捕获； 擦除时， N+区、 P+区施加正偏压， 多晶硅控制栅施加负偏压， 使氮化硅陷阱 层中的电子进入衬底； 读取时， 在 N+区施加正偏压， P+区接地， 多晶硅控制栅施加正偏 压， 控制偏压大小， 在不进行误编程的前提下从 N+区读出电流。
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