WO2012136027A1

WO2012136027A1 - Sonos flash memory device, manufacturing method and operation method therefor

Info

Publication number: WO2012136027A1
Application number: PCT/CN2011/077199
Authority: WO
Inventors: 蔡一茂; 黄如; 秦石强; 田明; 唐粕人; 唐昱
Original assignee: 北京大学
Priority date: 2011-04-08
Filing date: 2011-07-15
Publication date: 2012-10-11
Also published as: CN102738244B; CN102738244A

Abstract

A SONOS flash memory device, a manufacturing method and an operation method therefor, comprising a substrate (401), a source and drain (402 and 403), and a channel. Sequentially provided on the channel are a tunneled oxide layer (404), a silicon nitride trap layer (405), a blocking oxide layer (406), and a polycrystalline control gate (407). The SONOS flash memory device is characterized in that: the substrate (401) is of lightly doped silicon, and the source and drain (402 and 403) are of different doping types, being respectively a P+ region and an N+ region. The device is provided with improved compatibility with existing standard CMOS techniques, thus allowing for effectively increased programming efficiency, reduced power consumption, inhibited feedthrough effect, and a compact size.

Description

SONOS fast flash touch and its preparation ^ 3⁄4 and operation method

Technical field

The present invention relates to the field of non-volatile semiconductor memory technology in a very large scale integrated circuit, and in particular to a SONOS type flash memory using a TFET (Tunneling Field Effective Transistor). Background technique

At a time when various consumer electronics products are widely emerging, the demand for non-volatile semiconductor memories is increasing. As a very important non-volatile memory, flash memory has recently become the darling of the industry.

Flash Memory (also known as flash memory) has been around for decades. During this period, while being widely used, improvements are constantly being made. In the order of time, the following two basic forms appear in order:

1.Floating Gate Flash Memory

This type of flash memory uses a polysilicon floating gate for electronic storage. The specific structure is as shown in FIG. 1. On the bulk silicon substrate 101, in addition to the source 102 and the drain 103, the tunnel oxide layer 104, the polysilicon floating gate 105, the blocking oxide layer 106 and the control gate 107 are sequentially arranged above the channel. . It should be noted that the electrons of the structured flash memory are continuously distributed on the floating gate.

2. Discrete Trap Flash Memory

The difference from the floating gate flash memory is that the structure of the isolated trap type flash memory for storing electrons is a silicon nitride trap layer instead of a polysilicon floating gate, and the rest of the structure is substantially the same as that of the floating gate type flash memory (see FIG. 1 ), therefore, The floating gate type flash memory is also called a SONOS (silicon-oxide-nitride-oxide-silicon) type flash. The electrons deposited in the silicon nitride trap layer are localized and not continuous. Therefore, if the tunneling oxide layer is damaged and a leak path occurs, only the electrons in the channel region leak through the leak channel, and the electrons stored in other portions are not reduced, thus improving the holding characteristics of the entire device.

It should be noted that the latter structure has a larger performance improvement than the former one, especially in terms of maintaining characteristics, and thus has become a research hotspot in recent years. However, due to the most basic programming mechanism limitations, the fast flash memory of this SONOS structure also has the same low programming efficiency, high power consumption, and difficulty in continuing to scale down as the first type of flash memory.

On the other hand, a Tunneling Filed Effect Transistor (referred to as TFET) is a transistor based on quantum tunneling effect. The structure is different from the traditional MOS transistor in that the source and drain are two different doping types, and the lightly doped N-type silicon (N-type silicon) and the lightly doped P-type silicon (P-type) Silicon) can be used as a substrate. 2 is a schematic view showing the structure of a TFET using N-type silicon as the substrate 201, which is respectively N+ terminal 202 at both ends of the silicon plane. And P+ terminal 203, above which is gate oxide layer 204 and polysilicon gate 205. In the case where the external voltage is not connected to each terminal, the energy band along the channel direction is as shown in Fig. 3 (a), and the entire transistor is turned off. When a sufficient negative bias and a positive bias are applied to the P+ terminal 203 and the N+ terminal 202, respectively, and the polysilicon gate 205 is properly biased, the energy band along the channel direction is as shown in Fig. 3(b). If the applied bias voltage is sufficient to bend the energy band at the junction of the P+ terminal 203 and the channel such that band to band tunneling occurs, electrons will tunnel from the valence band of the P+ terminal 203 to the channel region. The band is then drifted to the N+ terminal 202 by an electric field in the direction of the channel. At this time, the transistor is used as an N-type TFET in which the N+ terminal 202 serves as a drain and the P+ terminal 203 serves as a source. When a sufficient negative bias and a positive bias are applied to the P+ terminal 203 and the N+ terminal 202, respectively, and the polysilicon gate 205 is properly biased, the energy band along the channel direction is as shown in Fig. 3(c). If the applied bias voltage is sufficient to bend the energy band at the junction of the N+ terminal 202 and the channel such that band to band tunneling occurs, electrons will tunnel from the valence band of the channel region to the N+ terminal 202, leaving The underlying holes are quickly swept to the P+ end 203 under the action of a strong electric field. At this time, the transistor is used as a P-type TFET in which the P+ terminal 203 serves as a drain and the N+ terminal 202 serves as a source. Summary of the invention

The present invention provides a high-performance SONOS flash memory in combination with tunneling field effect transistors in view of the numerous challenges faced by conventional flash memories, which can improve programming efficiency, reduce programming power consumption, and suppress punch-through effects while improving retention characteristics. .

The technical solution of the present invention is as follows:

A SONOS flash memory includes a substrate, a source drain and a channel, the channel is located between the source and the drain, and the tunnel is followed by a tunneling oxide layer, a silicon nitride trap layer, a blocking oxide layer and a polysilicon control gate; The substrate is lightly doped silicon; the source and drain are of different types, the source end is a P+ region, and the drain end is an N+ region.

The above flash memory, lightly doped P-type silicon (P-type silicon) and lightly doped N-type silicon (N-type silicon) can be used as the substrate.

The invention also provides a method for preparing the above SONOS flash memory, comprising the following steps:

1) shallow trench isolation lightly doped silicon substrate to form an active region;

2) sequentially forming a first silicon dioxide layer (tunneling oxide layer), a silicon nitride layer (trap layer), a second silicon dioxide layer (blocking oxide layer), and a polysilicon layer (control gate) on the substrate;

3) heavily doping and thermal annealing (RTA) of the polysilicon layer to activate impurities;

4) etching step 2) forming a polysilicon layer, a second silicon dioxide layer, a silicon nitride layer and a first silicon dioxide layer to form a gate stack structure;

5) P+ implant and N+ implant are respectively performed on both ends of the gate stack structure to form source and drain. The above step 1) may employ a P-type or N-type bulk silicon substrate.

The first silicon dioxide layer in the above step 2) may be formed by deposition or thermal growth. In order to improve the surface properties of the channel, a sacrificial oxide layer may be thermally grown on the silicon substrate before the formation of the first silicon oxide layer, and the sacrificial oxide layer is removed by wet etching, and then thermally grown or deposited. The silicon dioxide layer acts as a tunneling oxide layer.

The SONOS flash memory of the present invention, whether it is a P-type silicon substrate or an N-type silicon substrate, has the same operation method, and is briefly described as follows:

During programming, the P+ region is grounded, the N+ region is applied with a positive bias, and the control gate is applied with a positive bias. Under this bias, similar to an N-type TFET, electrons will tunnel from the valence band of the P+ region to the conduction band of the channel. The electrons entering the channel region drift in the channel direction toward the N+ region under the action of the transverse electric field. In this process, due to the action of the applied electric field, the energy obtained by some electrons is high enough to exceed the barrier height of Si/Si0 ₂ , pass through the tunneling oxide layer and enter the silicon nitride trap layer, and Capture, complete programming of the memory unit.

When erasing, the N+ region and the P+ region apply a positive bias, and the control gate applies a negative bias. Under such bias conditions, FN tunneling will occur, causing electrons in the silicon nitride trap layer to enter the silicon substrate, completing the erasing of the memory cells.

When reading, a positive bias is applied to the N+ region, the P+ region is grounded, and the control gate applies a small positive bias. The setting of the control bias requires that the current be read from the N+ region without misprogramming. The amount of electrons trapped by the silicon nitride trap layer affects the current read from the drain (N+ region). In this way, the current read by the drain reflects the amount of electrons trapped by the silicon nitride trap layer, and the two states are distinguished to realize the storage function.

The invention combines a tunneling field effect transistor (TFET) to propose a SONOS flash memory structure, which has good compatibility with the existing standard CMOS process, and has the advantages of good maintenance characteristics of the general SONOS flash memory. At the same time, it can effectively improve programming efficiency, reduce power consumption, suppress punch-through effect, etc., and ideal for small size characteristics.

Taking the SONOS flash memory of P-type silicon substrate as an example, under the programming bias condition, the energy band at the intersection of the P+ region and the channel will be obviously bent, and band to band tunneling will occur. )phenomenon. At this point, there will be a large voltage drop at the bend of the energy band, that is, the peak of the transverse electric field is located near the P+ region of the source, so that when the electron enters the channel, a large amount of energy can be obtained to cross the Si/ The barrier of Si0 ₂ enters the silicon nitride layer. In the conventional SONOS-type flash memory, the peak of the transverse electric field along the channel direction is located near the drain end. Before the electron reaches the peak position, the energy is very low, which is not enough to cross the Si/Si0 ₂ barrier. At this peak position, when a large amount of energy is obtained, since it is very close to the drain end, there is a great chance that it is sucked away by the drain end, which greatly reduces the programming efficiency.

In the case that the programming efficiency is greatly improved, the electrons from the source P+ region of the flash memory of the present invention are efficiently injected into the silicon nitride trap layer, which greatly reduces the drain current which is ineffective for programming, and shortens the programming time. , to achieve the purpose of reducing power consumption. At the same time, the SONOS structure has better retention characteristics than the floating gate type flash memory.

In addition, the traditional MOS FET-based flash memory will have source and drain junction depletion in small size. The regions are connected to each other, generating a large current flowing from the source to the drain, affecting the normal implementation of the function. In the flash memory of the present invention, since the source junction and the drain junction are not present at the same time, the Punch-Through Effect can be largely suppressed. DRAWINGS

Figure 1 is a schematic cross-sectional view of a conventional flash memory (floating gate type and split trap type), in which:

101-body silicon substrate; 102-drain terminal; 103-source terminal; 104-tunneling oxide layer; 105-polysilicon floating gate (corresponding to floating gate type flash memory) or silicon nitride trap layer (corresponding to separate trap type flash memory) 106—blocking oxide layer; 107—polysilicon control FIG. 2 is a schematic cross-sectional structure of the TFET, wherein:

201-body silicon substrate (N-doped); 202-N+ terminal (drain terminal for N-type TFET, source terminal for P-type TFET); 203-P+ terminal (drain terminal for P-type TFET, N-type TFET is used as the source terminal); 204—gate oxide layer; 205—polysilicon gate.

Figure 3 is an energy band diagram of the TFET shown in Figure 2 along the channel direction under various bias conditions, where:

(a) an energy band diagram when the terminals are not biased;

(b) is the energy band diagram of the device in Figure 2 as an N-type TFET (N+ terminal 202 is connected to forward voltage, P+ terminal 203 is grounded or negative voltage, and polysilicon gate 205 is connected to higher forward voltage);

(c) The energy band diagram for the device in Figure 2 as a P-type TFET (N+ terminal 202 is connected to the forward voltage, P+ terminal 203 is connected to the ground or negative voltage, and polysilicon gate 205 is connected to the higher negative voltage).

4 is a schematic structural diagram of a SONOS flash memory of the present invention, wherein:

401—N- or P-type silicon substrate; 402—N+ region; 403—P+ region; 404—tunneling oxide layer; 405—silicon nitride trap layer; 406—barrier oxide layer; 407—polysilicon control gate.

5(a)-(c) are schematic diagrams showing the structure of products corresponding to the steps of the process of preparing a SONOS flash memory for preparing a P-type silicon substrate, wherein:

401—P-type silicon substrate; 402—N+ region; 403—P+ region; 404—tunneling oxide layer; 405—silicon nitride trap layer; 406—barrier oxide layer; 407—polysilicon control gate. detailed description

The following is a description of a flash memory of a P-type silicon substrate as an example to further illustrate the preparation of the flash memory of the present invention, and the basic operation mode of the flash memory, but does not limit the scope of the present invention. The present invention is equally applicable to a flash memory using N-type silicon as a substrate.

The structure of the flash memory prepared in this embodiment is as shown in FIG. 4, and the P-type silicon 401 is used as a substrate. The P+ region and the N+ region are both ends of the silicon plane, and the channel region is in the middle, and the channel is sequentially To tunnel the oxide layer, the silicon nitride trap layer, Block oxide layer and polysilicon control gate. The entire device is a TFET type SONOS flash memory.

The preparation of the above flash memory includes the following steps:

(1) performing shallow germanium isolation (STI) on the single throw P-type silicon substrate 401 to form an active region;

(2) thermally growing a sacrificial oxide layer to improve the surface quality of the channel, and then hydrofluoric acid rinses off the sacrificial oxide layer; then thermally growing the oxide layer 404 to a thickness of 5 nm, and sequentially depositing a silicon nitride layer 405 (thickness) 8 nm), oxide layer 406 (thickness 9 nm) and polysilicon layer 407 (both 50 nm thick), as shown in Figure 5 (a);

(3) heavily doping the top polysilicon 407, followed by rapid thermal annealing (RTA) to activate the impurity;

(4) etching the polysilicon layer 407, the silicon dioxide layer 406, the silicon nitride layer 405, and the silicon dioxide layer 404 to form Fig. 5

(b) the gate stack structure shown;

(5) Arsenic (402) and boron (403) implantation are performed on both sides of the gate to form a heavily doped N+ region 402 and a P+ region 403, as shown in Fig. 5(c).

Subsequent steps are conventional processes: depositing a low-oxygen layer, etching lead holes, sputtering metal, forming metal lines, alloys, passivation, etc., and finally forming a testable flash memory cell.

The following is a description of the specific operating modes of the above devices.

Programming: When the device is programmed, control gate 407 applies a suitable positive voltage, P+ region 403 is grounded, and N+ region 402 applies a positive voltage. Under such bias conditions, electrons of the P+ region 403 will tunnel into the channel region and then flow toward the N+ region 402 along the channel direction. When the applied bias is appropriate, some of the electrons get enough energy to cross the barrier of Si/Si0 ₂ into the silicon nitride trap layer 405 and be trapped by the traps to complete the programming of the device.

Erase: The erasing of this device is implemented by means of FN. Control gate 407 applies a suitable negative voltage, and P+ region 403 and N+ region 402 apply a positive voltage. Under such bias conditions, electrons located in the silicon nitride trap layer 405 tunnel into the substrate to complete the erase of the device.

Read: The device's memory state is read using an N-TFET-like approach. When reading, the control gate 407 adds a small positive voltage, the P+ region 403 is grounded, and the N+ region 402 is applied with a smaller forward voltage. The bias setting requires reading the current of the N+ region 402 without misprogramming. . When electrons are trapped in the silicon nitride trap layer 405, the current read from the N+ region 402 terminal is small; when the electrons in the silicon nitride trap layer 405 are erased, the current read from the N+ region 402 terminal is compared. Large, this enables reading of two storage states.

Through the above programming, erasing and reading operations, the entire device can work normally and complete the storage function.

Claims

Claim

A SONOS flash memory comprising a substrate, a source drain and a channel, the channel being located between the source and the drain, and a tunneling oxide layer, a silicon nitride trap layer, a blocking oxide layer and a polysilicon control a gate; the substrate is lightly doped silicon; the doping type of the source and drain are different, the source end is a P+ region, and the drain end is an N+ region.

2. The flash memory according to claim 1, wherein the substrate is lightly doped P-type silicon or lightly doped N-type silicon.

3. A method of preparing a SONOS flash memory, comprising the steps of:

2) sequentially forming a first silicon dioxide layer, a silicon nitride layer, a second silicon dioxide layer, and a polysilicon layer on the substrate;

3) heavily doping and thermal annealing the polysilicon layer to activate impurities;

4) etching a step 2) forming a polysilicon layer, a second silicon dioxide layer, a silicon nitride layer and a first silicon dioxide layer to form a gate stack structure;

5) P+ implant and N+ implant are respectively performed on both ends of the gate stack structure to form source and drain.

The method according to claim 3, wherein the step 1) the lightly doped silicon substrate is a P-type or N-type bulk silicon substrate.

The method according to claim 3, wherein the step 2) forms the first silicon dioxide layer by deposition or thermal growth.

6. The method according to claim 3, wherein step 2) thermally growing a sacrificial oxide layer on the silicon substrate before forming the first silicon dioxide layer, and then removing the sacrifice by wet etching. Oxide layer.

7. The method of operating a SONOS flash memory according to claim 1, comprising: during programming, the P+ region is grounded, the N+ region is applied with a positive bias voltage, and the polysilicon control gate is applied with a positive bias voltage to allow a portion of the electrons to pass through the tunneling oxide layer. In the silicon nitride trap layer, and is captured; when erasing, the N+ region and the P+ region are applied with a positive bias voltage, and the polysilicon control gate applies a negative bias voltage to cause electrons in the silicon nitride trap layer to enter the substrate; A positive bias is applied to the N+ region, the P+ region is grounded, a polysilicon control gate is applied with a positive bias voltage, the bias voltage is controlled, and current is read from the N+ region without misprogramming.