WO2012079481A1 - 具有夹心式电流阻挡结构的发光二极管 - Google Patents

具有夹心式电流阻挡结构的发光二极管 Download PDF

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WO2012079481A1
WO2012079481A1 PCT/CN2011/083621 CN2011083621W WO2012079481A1 WO 2012079481 A1 WO2012079481 A1 WO 2012079481A1 CN 2011083621 W CN2011083621 W CN 2011083621W WO 2012079481 A1 WO2012079481 A1 WO 2012079481A1
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layer
transparent conductive
conductive oxide
emitting diode
transparent
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PCT/CN2011/083621
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English (en)
French (fr)
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潘群峰
吴志强
林科闯
黄少华
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厦门市三安光电科技有限公司
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Publication of WO2012079481A1 publication Critical patent/WO2012079481A1/zh
Priority to US13/541,847 priority Critical patent/US8581268B2/en
Priority to US14/054,787 priority patent/US8823046B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/42—Bombardment with radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor

Definitions

  • the present invention relates to a gallium nitride based light emitting diode, and more particularly to a light emitting diode having a sandwich current blocking structure. Background technique
  • GaN gallium nitride
  • LEDs light emitting diodes
  • a transparent electrode is formed over the layer as an ohmic contact layer and a current spreading layer; then, a metal electrode (p electrode) is disposed over the transparent electrode for the bonding wire.
  • a metal electrode p electrode
  • the presence of the metal electrode causes the light emitted in the active layer to be blocked and absorbed, thereby reducing the light-emitting efficiency of the light-emitting diode chip.
  • a prior art gallium nitride based light emitting diode having a current blocking structure includes: a sapphire substrate 100, a buffer layer 101, an n-GaN layer 102, a multiple quantum well active layer 103, p a GaN layer 104, an ITO layer (transparent electrode) 200, an insulating layer 201, a p electrode 210, and an n electrode 220.
  • the bottom layer is a sapphire substrate 100; the buffer layer 101 is formed on the sapphire substrate 100; the n-GaN layer 102 is formed on the buffer layer 101; and the multiple quantum well active layer 103 is formed.
  • a p-GaN layer 104 is formed over the multiple quantum well active layer 103; a Si0 2 layer 201 is formed over a partial region of the p-GaN layer 104; and an ITO layer 200 is formed on the p- Another partial region of the GaN layer 104 and the SiO 2 layer 201; the p electrode 210 is formed over the ITO layer 200, and the p electrode 210 is included in the SiO 2 layer 201 in the axial direction; the n electrode 220 is formed in the n- Above the GaN layer 102.
  • the gallium nitride based light emitting diode of the above current current blocking structure can effectively solve the problem of light absorption of the metal electrode by suppressing current injection and light emission in the active layer 103 under the p electrode 210.
  • this structure causes current injection and composite illumination to be mostly concentrated in a peripheral region of the Si0 2 layer 201, and the position of the Si0 2 layer (current blocking structure) is usually in the central region of the chip, that is, the structure causes current injection and illumination. Focus on the local area of the chip near the center.
  • Figure 2 qualitatively depicts the current distribution of a prior art gallium nitride based light emitting diode having a current blocking structure.
  • the light-emitting surface of the chip includes a front side, a back side, and a side surface, and the side light occupies a certain light-emitting ratio, and for a photon, the active layer position is different, and the corresponding side light-emitting probability is different, the chip In the local area near the center, the probability that the photon is absorbed during the multiple reflections inside is high, which leads to a decrease in the probability of side light emission. In the outer ring area away from the center of the chip, the probability of photons being taken out from the side is high.
  • the gallium nitride-based light-emitting diode with current blocking structure produced according to the prior art has a large distribution of current concentrated on a local area near the center of the chip, thereby causing a decrease in the side light-emitting probability, and finally affecting the light-collecting efficiency of the light-emitting diode. .
  • the present invention is directed to a light emitting diode having a sandwich current blocking structure.
  • the present invention provides a light emitting diode having a sandwich current blocking structure.
  • the method comprises: a sapphire substrate; an illuminating epitaxial layer composed of an n-type GaN-based epitaxial layer, an active layer and a p-type GaN-based epitaxial layer; and a first transparent conductive oxide layer formed on the sapphire substrate; a GaN-based epitaxial layer; a transparent insulating layer formed on the first transparent conductive oxide layer, and the transparent insulating layer covering region is inwardly retracted relative to the first transparent conductive oxide layer, and the indentation scale is 1 ⁇ 50 micrometers; a second transparent conductive oxide layer is formed on the transparent insulating layer, and the second transparent conductive oxide layer covering region expands outward relative to the transparent insulating layer and forms an electrical connection with the first transparent conductive oxide layer;
  • the electrode is formed on the second transparent conductive oxide layer; the n electrode is formed on the n-type GaN-based epitaxial
  • the first transparent conductive oxide layer is prepared by using at least one of indium oxide, tin oxide, indium tin oxide, and zinc oxide.
  • the transparent insulating layer is prepared by using at least one material selected from the group consisting of silicon oxide, titanium oxide, silicon nitride, aluminum oxide, magnesium fluoride, SOG, and polymer.
  • the transparent insulating layer is made of silicon nitride; the refractive index of the commonly used transparent conductive oxide layer material is between 1.8 and 2.0, and the refractive index matching is preferred.
  • a transparent insulating layer is prepared from a silicon (refractive index of about 1.9) material.
  • the transparent insulating layer has a retracted dimension of less than 20 microns with respect to the first transparent conductive oxide layer.
  • the p-electrode is in a central partial region of the second transparent conductive oxide layer.
  • the invention innovatively employs a "transparent conductive oxide layer / transparent insulating layer / transparent conductive oxide layer" combined sandwich current blocking structure.
  • the first transparent conductive oxide layer functions to form an ohmic contact with the p-type GaN-based epitaxial layer;
  • the second transparent conductive oxide layer functions to electrically connect the first transparent conductive oxide layer and the p-electrode;
  • the transparent insulating layer functions Isolating the first transparent conductive oxide
  • the layer and the second transparent conductive oxide layer, and limiting the conduction path of the current in the first transparent conductive oxide layer, are laterally transmitted from the outer to the inner side.
  • the transparent insulating layer is retracted relative to the first transparent conductive oxide layer, and the shrinkage dimension is limited to a small range of 1 to 50 micrometers, so that the contact area of the first transparent conductive oxide layer and the second transparent conductive oxide layer It only occurs in a small area of 1 to 50 micrometers of the outer ring of the chip, so the current is first injected into the light-emitting layer from the first transparent conductive oxide layer of the outer ring region of the chip, and since the transparent conductive oxide layer has a certain lateral transmission resistance, Therefore, the distribution of the current distribution in the luminescent epitaxial layer is decreased from the outside to the inside, that is, the closer to the central region of the chip (corresponding to the position of the p-electrode), the smaller the current density, and may even tend to zero, so the current blocking structure of the present invention can Effectively avoiding the shading of the p-electrode; at the same time, since the current is more injected from the outer ring region of the chip, the active layer of the
  • FIG. 1 is a cross-sectional view showing a structure of a light-emitting diode having a current blocking structure in the prior art
  • FIG. 2 is a schematic diagram showing current distribution of a light-emitting diode having a current blocking structure in the prior art
  • FIG. 3 is a sandwich current blocking method according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram showing the current distribution of a light emitting diode having a sandwich current blocking structure according to an embodiment of the present invention.
  • 1 and 2 are: 100: sapphire substrate; 101: buffer layer; 102: n-GaN layer; 103: multiple quantum well (MQW) active layer; 104: p-GaN layer; ITO layer; 201: Si0 2 layer; 210: n electrode; 220: p electrode.
  • the reference numerals in FIGS. 3 and 4 are: 300: sapphire substrate; 301: buffer layer; 302: n-GaN layer; 303: multiple quantum well (MQW) active layer; 304: p-GaN layer; First ITO layer; 401: Si 3 N 4 layer; 402: second ITO layer; 410: ⁇ electrode; 420: ⁇ electrode.
  • the invention provides a light emitting diode with a sandwich current blocking structure, comprising: a sapphire substrate; an n-type GaN-based epitaxial layer, an active layer and a p-type GaN-based epitaxial layer are sequentially stacked on the sapphire substrate a light emitting epitaxial layer; the first transparent conductive oxide layer is formed on the p-type GaN-based epitaxial layer; the transparent insulating layer is formed on the first transparent conductive oxide layer, and the transparent insulating layer covers the first transparent The conductive oxide layer is inwardly retracted and has a shrinkage dimension of 1 to 50 microns; the second transparent conductive oxide layer is formed on the transparent insulating layer, and the second transparent conductive oxide layer covers the region with respect to the transparent insulating layer Externally expanded and electrically connected to the first transparent conductive oxide layer; the p-electrode is formed on the second transparent conductive oxide layer; and the n-electrode is formed on the n-type GaN-based
  • the n-type GaN-based epitaxial layer is an n-GaN layer
  • the active layer is a multiple quantum well active layer
  • the p-type GaN-based epitaxial layer is a p-GaN layer
  • the first transparent conductive oxide and the second The transparent oxide is ITO
  • the transparent insulating layer is a Si 3 N 4 layer, wherein the region where the Si 3 N 4 layer 401 covers the first ITO layer 400 is retracted by 10 micrometers relative to the first ITO layer 400,
  • the above materials, structures, and parameters can be configured according to specific needs.
  • the bottom layer is a sapphire substrate 300; the buffer layer 301 is formed on the sapphire substrate 300; the n-GaN layer 302 is formed on the buffer layer 301; and the multiple quantum well active layer 303 is formed on the n-GaN layer 302.
  • the material is indium gallium nitride (InGaN); the p-GaN layer 304 is formed on the multiple quantum well active layer 303; the first ITO layer 400 is formed on the p-GaN layer 304.
  • a "first ITO layer 400 / Si 3 N 4 layer 401 / second ITO layer 402" combined sandwich current blocking structure is used, wherein: the first ITO layer 400 functions to form an ohmic with the p-GaN layer 304.
  • the second ITO layer 402 functions to electrically connect the first ITO layer 400 and the p-electrode 410;
  • the transparent insulating layer is a Si 3 N 4 layer 401 functioning to isolate the first ITO layer 400 from the second ITO layer 402, and
  • the conduction path of the limiting current in the first ITO layer 400 is a lateral transmission from the outward to the inner type; in particular: Si 3 N 4 : 401 is formed as a transparent insulating layer on the first ITO layer 400, and 81 4 layers 401
  • the area covering the first ITO layer 400 is retracted by 10 micrometers with respect to the first ITO layer 400;
  • the second ITO layer 402 is formed on the 81 ⁇ 4 layer 401, and is recessed by the 81 ⁇ 4 layer 401
  • the exposed first ITO layer 400 forms an electrical contact;
  • the p-electrode 410 is formed over a central partial region of the second ITO layer 402, the material of which is Cr/Pt/Au;
  • a gallium nitride-based light-emitting diode having a sandwich current blocking structure has a current injection path of a p-electrode 410, a second ITO layer 402, a first ITO layer 400, and p-.
  • the current transmission mode is defined as "transverse transmission from the outside to the inside", and the lateral transmission of the current in the ITO layer has a larger area than the central area of the chip, and finally the photon side extraction probability of the outer ring area is higher, thereby obtaining higher The light extraction efficiency.

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  • Manufacturing & Machinery (AREA)
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Description

具有夹心式电流阻挡结构的发光二极管
本申请要求于 2010 年 12 月 16 日提交中国专利局、 申请号为 201010590655.0、 发明名称为"具有夹心式电流阻挡结构的发光二极管"的中国 专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种氮化镓基发光二极管，特别一种具有夹心式电流阻挡结构 的发光二极管。 背景技术
目前氮化镓（ GaN )基发光二极管 （ LED, Light Emitting Diode ) 已广泛 应用于手机按键、 指示、 显示、 背光源以及照明等领域。 传统的氮化镓基发光
层之上制作一透明电极作为欧姆接触层和电流扩展层； 然后，在透明电极上面 布置金属电极（p电极）用于焊线。 然而， 金属电极的存在会造成有源层中发 出的光被遮挡和吸收， 从而降低发光二极管芯片的出光效率。 为了避免上述问题，必须抑制或者减少金属电极下方有源层载流子输运及 其复合发光。 现有技术的解决方案之一是在芯片结构中引入一电流阻挡结构， 例如在透明电极与 p型氮化镓基外延层之间插入一绝缘层， 并且使得绝缘层区 域在芯片轴向上包含 p电极区域。如附图 1所示，采用现有技术的具有电流阻挡 结构的氮化镓基发光二极管， 包括：蓝宝石衬底 100、緩沖层 101、 n-GaN层 102、 多量子阱有源层 103、 p-GaN层 104、 ITO层 （透明电极） 200、 绝缘层 201、 p 电极 210和 n电极 220。 其中， 最底层为蓝宝石衬底 100; 緩沖层 101形成于蓝宝 石衬底 100之上； n-GaN层 102形成于緩沖层 101之上； 多量子阱有源层 103形成 于 n-GaN层 102之上； p-GaN层 104形成于多量子阱有源层 103之上； Si02层 201 形成于 p-GaN层 104的部分区域之上； ITO层 200形成于 p-GaN层 104的另一部分 区域以及 Si02层 201之上； p电极 210形成于 ITO层 200之上，且 p电极 210在轴向 上包含于 Si02层 201之内； n电极 220形成于 n-GaN层 102之上。 上述现有电流阻挡结构的氮化镓基发光二极管可通过抑制 p电极 210下方 有源层 103中的电流注入和发光， 有效地解决金属电极的吸光问题。 然而， 该 结构会使得电流注入和复合发光大部分集中于 Si02层 201外围局部区域， 而 Si02层 (电流阻挡结构）的位置通常处于芯片中央区域， 也就是该结构会使得 电流注入和发光集中于芯片靠近中央的局部区域。 附图 2定性地描述了现有技 术具有电流阻挡结构的氮化镓基发光二极管的电流分布状况。就出光而言， 芯 片的出光面包括正面、 背面和侧面， 侧面出光占据一定的出光比例， 而对于光 子来说， 其所发自的有源层位置不同， 对应的侧面出光概率就不同， 芯片中靠 近中央的局部区域， 因光子在内部多次反射过程中被吸收的概率较高，导致侧 面出光的概率降低； 而芯片中远离中央的外环区域， 光子从侧面取出的概率较 高。所以依照现有技术生产的具有电流阻挡结构的氮化镓基发光二极管， 因其 中电流的分布较多的集中于芯片靠近中央的局部区域从而导致侧面出光概率 降低， 最终影响发光二极管的取光效率。
发明内容
为提高上述具有电流阻挡结构的氮化镓基发光二极管的取光效率，本发明 旨在提出一种具有夹心式电流阻挡结构的发光二极管。
为达上述目的， 本发明提出一种具有夹心式电流阻挡结构的发光二极管， 其包括： 蓝宝石衬底； 在蓝宝石衬底之上依次层叠有由 n型 GaN基外延层、 有 源层和 p型 GaN基外延层构成的发光外延层； 第一透明导电氧化物层形成于 p 型 GaN基外延层之上； 透明绝缘层形成于第一透明导电氧化物层之上， 并且透 明绝缘层覆盖区域相对于第一透明导电氧化物层向内缩进， 并且内缩尺度为 1 ~ 50微米； 第二透明导电氧化物层形成于透明绝缘层之上， 并且第二透明导 电氧化物层覆盖区域相对于透明绝缘层向外扩展且与第一透明导电氧化物层 形成电学连接； p电极形成于第二透明导电氧化物层之上； n电极形成于 n型 GaN 基外延层之上。
所述的第一透明导电氧化物层选用氧化铟、 氧化锡、 氧化铟锡、 氧化锌中 的至少一种材料制备。
所述的透明绝缘层选用氧化硅、 氧化钛、 氮化硅、 氧化铝、 氟化镁、 SOG、 Polymer中的至少一种材料制备。
所述的透明绝缘层的制备材料为氮化硅； 目前常用的透明导电氧化物层材 料的折射率一半在 1.8 - 2.0, 基于折射率匹配方面考虑， 本发明优先采用折射 率最佳的氮化硅（折射率约 1.9 )材料制备透明绝缘层。
所述的透明绝缘层相对于第一透明导电氧化物层的内缩尺寸小于 20微米。 所述的 p电极处于第二透明导电氧化物层的中央局部区域。
本发明创新地采用了一"透明导电氧化物层 / 透明绝缘层 / 透明导电氧化 物层" 组合夹心式的电流阻挡结构。 第一透明导电氧化物层的作用在于与 p型 GaN基外延层形成欧姆接触；第二透明导电氧化物层的作用在于电学连接第一 透明导电氧化物层和 p电极； 透明绝缘层的作用在于隔离第一透明导电氧化物 层与第二透明导电氧化物层，并限制电流在第一透明导电氧化物层中的传导路 径是从外向内式的横向传输。 透明绝缘层相对于第一透明导电氧化物层的内 缩， 且内缩尺度限制在 1 ~ 50微米的小范围内， 使得第一透明导电氧化物层与 第二透明导电氧化物层的接触区域仅发生在芯片的外环 1 ~ 50微米的小范围区 域， 所以电流首先从芯片外环区域的第一透明导电氧化物层注入发光层， 而因 为透明导电氧化物层具有一定的横向传输电阻，所以电流分布在发光外延层中 的分布是由外向内递减的， 即越靠近芯片中央区域（与 p电极位置对应） 的电 流密度越小， 甚至可以趋于零， 因此本发明的电流阻挡结构可以有效的避免 p 电极的遮光； 同时， 因电流更多地从芯片中的外环区域注入有源层， 使得芯片 外环的有源层发出更多的光子， 而外环区域的光子侧面取出概率较高， 因此本 发明具有夹心式电流阻挡结构的发光二极管可以获得更高的取光效率。
附图说明
图 1是现有技术的具有电流阻挡结构的发光二极管结构剖示图； 图 2是现有技术的具有电流阻挡结构的发光二极管的电流分布示意图； 图 3是本发明实施例具有夹心式电流阻挡结构的发光二极管结构剖示图； 图 4是本发明实施例具有夹心式电流阻挡结构的发光二极管的电流分布 示意图。 图 1和图 2中附图标识为： 100: 蓝宝石衬底； 101: 緩沖层； 102: n-GaN 层； 103: 多量子阱 (MQW)有源层； 104: p-GaN层； 200: ITO层； 201: Si02层； 210: n电极； 220: p电极。 图 3和图 4中附图标识为： 300: 蓝宝石衬底； 301: 緩沖层； 302: n-GaN 层； 303: 多量子阱 (MQW)有源层； 304: p-GaN层； 300: 第一 ITO层； 401: Si3N4层; 402: 第二 ITO层； 410: ρ电极; 420: η电极。
具体实施方式
本发明提出了一种具有夹心式电流阻挡结构的发光二极管， 其包括： 蓝宝 石衬底； 在蓝宝石衬底之上依次层叠有由 η型 GaN基外延层、 有源层和 p型 GaN基外延层构成的发光外延层； 第一透明导电氧化物层形成于 p型 GaN基 外延层之上； 透明绝缘层形成于第一透明导电氧化物层之上， 并且透明绝缘层 覆盖区域相对于第一透明导电氧化物层向内缩进， 并且内缩尺度为 1 ~ 50微 米； 第二透明导电氧化物层形成于透明绝缘层之上， 并且第二透明导电氧化物 层覆盖区域相对于透明绝缘层向外扩展且与第一透明导电氧化物层形成电学 连接； p电极形成于第二透明导电氧化物层之上； n电极形成于 n型 GaN基外 延层之上。
为了更好地理解本发明， 下面结合图 3、 图 4和具体的实施例对本发明进 一步说明。
在此实施例中， n型 GaN基外延层为 n-GaN层， 有源层为多量子阱有源层， p型 GaN基外延层为 p-GaN层， 第一透明导电氧化物和第二透明氧化物为 ITO , 透明绝缘层为 Si3N4层，其中， Si3N4层 401覆盖第一 ITO层 400的区域相对于第 一 ITO层 400作 10微米的等比例内缩， 以上仅为示例， 可以根据具体需要配 置以上材料、 结构和参数。
如图 3所示的一种具有夹心式电流阻挡结构的氮化镓基发光二极管结构， 其包括蓝宝石衬底 300、緩沖层 301、 n-GaN层 302、多量子阱有源层 303、p-GaN 层 304、第一 ITO层 400、 Si3N4 : 401、第二 ITO层 402、 p电极 410和 n电极 420。 其中，最底层为蓝宝石衬底 300;緩沖层 301形成于蓝宝石衬底 300之上； n-GaN 层 302形成于緩沖层 301之上；多量子阱有源层 303形成于 n-GaN层 302之上， 其材料为氮化铟镓（InGaN )； p-GaN层 304形成于多量子阱有源层 303之上； 第一 ITO层 400形成于 p-GaN层 304之上。
本发明中采用 "第一 ITO层 400/ Si3N4层 401/第二 ITO层 402" 组合夹心式 的电流阻挡结构， 其中： 第一 ITO层 400的作用在于与 p-GaN层 304形成欧姆 接触； 第二 ITO层 402的作用在于电学连接第一 ITO层 400和 p电极 410; 透明 绝缘层为 Si3N4层 401的作用在于隔离第一 ITO层 400与第第二 ITO层 402 , 并 限制电流在第一 ITO层 400中的传导路径是从外向内式的横向传输； 尤其是： Si3N4 : 401作为透明绝缘层形成于第一 ITO层 400之上，并且 81^4层 401覆盖 第一 ITO层 400的区域相对于第一 ITO层 400作 10微米的等比例内缩；第二 ITO 层 402形成于 81^4层 401之上，并且与因 81^4层 401内缩而暴露出的第一 ITO 层 400形成电学接触； p电极 410形成于第二 ITO层 402的中央局部区域之上， 其材料为 Cr/Pt/Au; n电极 420形成于 n-GaN层 302之上， 其材料为 Cr/Pt/Au。
如图 4所示，根据本发明制作的具有夹心式电流阻挡结构的氮化镓基发光 二极管，其电流注入的路径依次为 p电极 410、第二 ITO层 402、第一 ITO层 400、 p-GaN层 304、 多量子阱 (MQW)有源层 303、 n-GaN层 302、 n电极 420, 其中 由于 Si3N4层 401的引入及其 "内缩" 的定位， 使得第一 ITO层 400中的电流传 输方式被定义为 "由外向内" 横向传输， 而因电流在 ITO层中横向传输具有一 大于芯片中央区域， 最后由于芯片外环区域的光子侧面取出概率较高，从而获 得更高的取光效率。 以上实施例仅供说明本发明之用， 而非对本发明的限制， 本技术领域的普 通技术人员，在不脱离本发明的精神和范围的情况下，还可以作出各种变换或 变化； 所有等同的技术方案也应该属于本发明的范畴， 由各权利要求限定。

Claims

权 利 要 求
1、 具有夹心式电流阻挡结构的发光二极管， 其包括： 蓝宝石 ^十底； 在蓝宝石衬底之上依次层叠有由 n型 GaN基外延层、 有源层和 p型 GaN 基外延层构成的发光外延层； 第一透明导电氧化物层形成于 p型 GaN基外延层之上； 透明绝缘层形成于第一透明导电氧化物层之上，并且透明绝缘层覆盖区域 相对于第一透明导电氧化物层向内缩进， 并且内缩尺度为 1 ~ 50微米； 第二透明导电氧化物层形成于透明绝缘层之上，并且第二透明导电氧化物 层覆盖区域相对于透明绝缘层向外扩展且与第一透明导电氧化物层形成电学 连接； p电极形成于第二透明导电氧化物层之上； n电极形成于 n型 GaN基外延层之上。
2、 根据权利要求 1所述的具有夹心式电流阻挡结构的发光二极管， 其特 征在于： 所述的第一透明导电氧化物层选用氧化铟、 氧化锡、 氧化铟锡、 氧化 锌中的至少一种材料制备。
3、 根据权利要求 1所述的具有夹心式电流阻挡结构的发光二极管， 其特 征在于： 所述的透明绝缘层选用氧化硅、 氧化钛、 氮化硅、 氧化铝、 氟化镁、 SOG、 Polymer中的至少一种材料制备。
4、 根据权利要求 3所述的具有夹心式电流阻挡结构的发光二极管， 其特 征在于： 所述的透明绝缘层的制备材料为氮化硅。
5、 根据权利要求 1所述的具有夹心式电流阻挡结构的发光二极管， 其特 征在于： 所述的透明绝缘层相对于第一透明导电氧化物层内缩的尺寸小于 20 微米。
6、 根据权利要求 1所述的具有夹心式电流阻挡结构的发光二极管， 其特 征在于： 所述的第二透明导电氧化物层选用氧化铟、 氧化锡、 氧化铟锡、 氧化 锌中的至少一种材料制备。
7、 根据权利要求 1所述的具有夹心式电流阻挡结构的发光二极管， 其特 征在于： 所述的 p电极处于第二透明导电氧化物层的中央局部区域。
PCT/CN2011/083621 2010-12-16 2011-12-07 具有夹心式电流阻挡结构的发光二极管 WO2012079481A1 (zh)

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