WO2012051820A1 - 衬底结构、半导体器件及其制造方法 - Google Patents
衬底结构、半导体器件及其制造方法 Download PDFInfo
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- WO2012051820A1 WO2012051820A1 PCT/CN2011/071224 CN2011071224W WO2012051820A1 WO 2012051820 A1 WO2012051820 A1 WO 2012051820A1 CN 2011071224 W CN2011071224 W CN 2011071224W WO 2012051820 A1 WO2012051820 A1 WO 2012051820A1
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- WIPO (PCT)
- Prior art keywords
- trench
- heat dissipation
- layer
- dielectric layer
- substrate
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 134
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 87
- 230000017525 heat dissipation Effects 0.000 claims description 90
- 238000000034 method Methods 0.000 claims description 29
- 230000000149 penetrating effect Effects 0.000 claims description 23
- 239000011810 insulating material Substances 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 7
- 230000010354 integration Effects 0.000 abstract description 6
- 239000000463 material Substances 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Definitions
- the present invention relates generally to semiconductor fabrication techniques and, in particular, to a substrate structure, a semiconductor device, and a method of fabricating the same. Background technique
- Isolation is a component that separates the active areas of each component.
- shallow trench isolation Shallow Trench Isolation
- a surface of the bottom forms a shallow trench isolation filled with a dielectric material in the substrate, so that the device can be formed only on one surface of the substrate, which is disadvantageous for improving substrate utilization and device integration.
- the present invention provides a substrate structure, the substrate structure comprising: a semiconductor substrate; a first isolation region; wherein the first isolation region comprises: a first trench, the trench through a semiconductor substrate; a first dielectric layer, the first dielectric layer filling the first trench.
- the present invention also provides another substrate structure, the structure comprising: a semiconductor substrate; a second isolation region; wherein the second isolation region comprises: a second trench, the second trench penetrating the semiconductor a second dielectric layer, the second dielectric layer is formed on a sidewall of the second trench; a first heat dissipation layer, the first heat dissipation layer fills an area between the inner walls of the second dielectric layer .
- the present invention further provides a substrate structure, the structure comprising: a semiconductor substrate; a third isolation region; wherein the third isolation region comprises: a third trench, the third trench penetrating the semiconductor a second heat dissipation layer, the second heat dissipation layer is formed on a sidewall of the third trench; and a third dielectric layer is filled between the inner walls of the second heat dissipation layer region.
- the present invention also provides a semiconductor device formed on the upper surface and/or the lower surface of any of the above semiconductor substrate structures.
- the present invention also provides a method of fabricating the above semiconductor substrate structure, the method comprising: A) Providing a semiconductor substrate; B) forming a support layer on the semiconductor substrate; C) forming a trench penetrating the semiconductor substrate and exposing the support layer, and filling the trench to form isolation Zone; D) removing the support layer.
- a method of fabricating a semiconductor device in which a semiconductor device is formed on an upper surface and/or a lower surface of the above substrate structure.
- the device structure By forming a substrate structure having a through-isolation region penetrating through the substrate, the device structure can be formed by using the two surfaces of the substrate, thereby improving the utilization of the substrate and improving the integration of the device.
- FIGS. 17-20 illustrate schematic structural views of a semiconductor device in accordance with some embodiments of the present invention. detailed description
- the present invention generally relates to methods of fabricating semiconductor devices.
- the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
- the components and settings of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
- the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
- the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
- the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
- FIG. 7 illustrates a first embodiment of a substrate structure of the present invention.
- the substrate structure includes: a semiconductor substrate 200; a first isolation region 310; wherein the first The isolation region 310 includes: a first trench 206-1, the first trench 206-1 penetrating the semiconductor substrate 200; a first dielectric layer 208, the first dielectric layer 208 filling the first trench Slot 206-1.
- FIG. 8 illustrates a second embodiment of a substrate structure of the present invention.
- the substrate structure includes: a semiconductor substrate 200; a second isolation region 320; wherein the second The isolation region 320 includes: a second trench 206-2, the second trench 206-2 penetrating the semiconductor substrate 200; a second dielectric layer 210, the second dielectric layer 210 is formed in the second trench a sidewall of the trench 260-2; a first heat dissipation layer 212, the first heat dissipation layer 212 is filled A region between the inner walls 210-2 of the second dielectric layer 210 is filled.
- FIG. 9 illustrates a third embodiment of a substrate structure of the present invention.
- the substrate structure includes: a semiconductor substrate 200; a third isolation region 330; wherein the third The isolation region 330 includes: a third trench 206-3, the third trench 206-3 penetrating the semiconductor substrate 200; a second heat dissipation layer 214, the second heat dissipation layer 214 is formed in the third trench On the sidewall of the trench 206-3; a third dielectric layer 216 filling the region between the inner walls 214-2 of the second heat dissipation layer 214.
- the third isolation region 330 can simultaneously provide isolation and heat dissipation.
- the substrate structure may further include one or more of the following structures: a second isolation region in the second embodiment, a third isolation region in the third embodiment, and heat dissipation.
- the heat dissipation region 340 (refer to FIG. 20) includes: a fourth trench 206-4, the fourth trench 206-4 penetrating the semiconductor substrate 200; a third heat dissipation layer 218, the The third heat dissipation layer 218 fills the fourth trench 206-4.
- the substrate structure may further include one or more of the following structures: a first isolation region in the first embodiment, a third isolation region in the third embodiment, and the foregoing Cooling area.
- the substrate structure may further include the above-described heat dissipation region.
- the semiconductor substrate may include a silicon-on-insulator (SOI) structure.
- the substrate may further include a silicon substrate (eg, a wafer), and may further include Other basic semiconductors or compound semiconductors such as Ge, GeSi, GaAs, InP or SiC.
- the substrate may comprise various doping configurations in accordance with design requirements well known in the art (e.g., p-type substrates or n-type substrates).
- substrate 200 may include an epitaxial layer that may be altered by stress to enhance performance.
- the first dielectric layer, the second dielectric layer, and the third dielectric layer may include an insulating material, and examples of the insulating material include nitrides, oxides, low-k dielectric materials, or other materials. Or a combination thereof, wherein the first heat dissipation layer, the second heat dissipation layer, and the third heat dissipation layer comprise a metal material.
- the semiconductor substrate structure with punch-through isolation has been described in detail above. Since the isolation region is penetrated through the substrate, the device structure can be formed by using the two surfaces of the substrate, thereby improving the utilization ratio of the substrate and improving the device.
- the integration degree in a preferred embodiment, may further include a heat dissipation area to improve the heat dissipation effect of the device.
- the present invention also provides a semiconductor device having the above substrate structure.
- the semiconductor device 300 is formed on the upper surface and/or the lower surface of the substrate structure of any of the above embodiments.
- the semiconductor device can include a transistor, a diode, or other electrical device. The illustration is merely an example, and the invention is not limited thereto.
- a semiconductor substrate 200 is provided, with reference to Fig. 1.
- the semiconductor substrate 200 is the same as that described in the foregoing embodiment and will not be described again.
- a support layer 204 is formed on the semiconductor substrate 200, as shown in FIG.
- the support layer 204 may be formed by depositing a nitride or an oxide such as SiO 2 or Si 3 N 4 on the semiconductor substrate 200.
- the support layer 204 may also be other suitable materials, such as a metal material or other semiconductor material different from the semiconductor substrate material; the thickness of the support layer 204 is sufficient to carry the semiconductor.
- Substrate 200 as an example, the support layer 204 may have a thickness of 50 microns to 200 microns, such as 100 microns.
- the support layer 204 can be formed by a deposition process.
- step S03 a trench is formed which penetrates the semiconductor substrate and exposes the support layer, and fills the trench to form an isolation region.
- a hard mask 202 may be formed on the surface of the semiconductor substrate 200 opposite to the support layer 204.
- the pad oxide layer 202 may be sequentially deposited on the semiconductor substrate 200.
- the pad oxide layer 202-1 may be silicon dioxide or the like, which is generally formed by a thermal oxidation process
- the pad nitride layer 202-2 may be It is silicon nitride, which is generally deposited by chemical vapor deposition, and then patterned by a mask, such as Rffi (Reactive Ion Etching), to form a trenched hard mask 202.
- the semiconductor substrate 200 is etched by using the hard mask 202 as a mask by using an etching technique, such as RIE, and the via layer is formed by using the support layer 204 as a stop layer. Referring to FIG. 3 .
- the trenches may all be the first trench 206-1 exposing the support layer 204, and the first trench 206-1 may be filled with the first dielectric layer 208.
- the isolation region structure 310 that is only filled by the first dielectric layer 208.
- the following steps may be further performed: further removing a portion of the first dielectric layer 208 in the first trench 206-1 to restore a portion of the first trench 206-1, with reference to FIG. 10, in one example, Forming a second dielectric layer 210 on the sidewall of the restored first trench 206-1, and filling a region between the inner walls 210-2 of the second dielectric layer 210 with the first heat dissipation layer 212 to form An isolation structure 320 having a sidewall of the second dielectric layer 210 and a first heat dissipation layer 212 is filled, with reference to FIG.
- a sidewall formed on the sidewall of the restored first trench 206-1 Two heat dissipation layers 214 are formed, and a region between the inner walls 214-2 of the second heat dissipation layer 214 is filled with a third dielectric layer 216 to form an isolation structure 330 with a second heat dissipation layer sidewall 214 and a third dielectric layer 216 filling.
- a third heat dissipation layer 218 is filled in the restored first trench 206-1 to form a heat dissipation region 340.
- there is an isolation area structure one 310, an isolation area structure two 320 and an isolation area structure three 330 Refer to Figure 13 for the substrate structure.
- each of the isolated isolation structures may be removed as needed to recover a portion of the first trench 206-1, and the restored first trench 206-1 is filled with a different shape.
- the material required for each isolation structure can form a plurality of isolation regions on the same semiconductor substrate 200, or a heat dissipation structure for the same semiconductor substrate 200 to have an isolation structure, which is advantageous for design requirements.
- the substrate structure of the isolation region structure 310, the isolation region structure 320, the isolation region structure 330, and the heat dissipation region 340 can be formed by multiple masking, etching, and filling methods.
- a first trench may be formed in the semiconductor substrate 200, and then in the first An isolation region structure 310 is formed in the trench; then, a third trench is formed in a remaining region in the semiconductor substrate 200, and an isolation region structure 330 is formed in the third trench; A fourth trench is formed in a region other than the isolation region structure one 310 and the isolation region structure three 330, and a heat dissipation region 340 is formed in the fourth trench.
- the semiconductor substrate 200 has a combination of an isolation region structure and a heat dissipation region, the formation method thereof is similar, and will not be described again.
- a second trench 206-2 exposing the support layer 204 may be formed, a second dielectric layer 210 is formed on a sidewall of the second trench 206-2, and filled with the first heat dissipation layer 212.
- a method similar to that described in the first embodiment may be employed (filling all of the second trenches first, restoring a portion of the second trenches, and forming other isolation regions in the recovered second trenches) Or a heat dissipating area; or, step etching the trenches to form the isolation structure or the heat dissipating region step by step, further forming at least one of the isolation region structure 310, the isolation region structure 330, and the heat dissipation region 340
- the combined substrate structure is formed to form a substrate structure having an isolation region structure 320 or an isolation region structure 320 with an isolation region structure 310, an isolation region structure 330, and a heat dissipation region 340.
- a third trench 206-3 exposing the support layer 204 may be formed, a second heat dissipation layer 214 is formed on a sidewall of the third trench 206-3, and the third dielectric layer 216 is used to fill the trench.
- a region between the inner walls 214-2 of the second heat dissipation layer 214 is formed to form an isolation region structure 330 having a second heat dissipation layer sidewall and a third dielectric layer filling.
- a method similar to that described in the first embodiment and the second embodiment may be employed, and may be further formed in combination with at least one of the isolation region structure 310, the isolation region structure 320, and the heat dissipation region 340.
- the structure structure of the isolation structure structure 320 and the heat dissipation area 340 is any combination of structures.
- a planarization process is performed to remove the hard mask 202 and other filling materials until the substrate is exposed.
- the first dielectric layer, the second dielectric layer, and the third dielectric layer comprise an insulating material
- examples of the insulating material include nitride, oxide, low-k dielectric material or other materials, or A combination thereof, wherein the first heat dissipation layer, the second heat dissipation layer, and the third heat dissipation layer comprise a metal material.
- the support layer 204 is removed.
- the support layer 204 may be further removed by CMP or wet etching to expose the substrate to form a substrate structure, with reference to Figures 7-9, 14-16.
- the illustrated examples are merely examples, and the present invention is not limited thereto.
- the semiconductor device 300 may be formed on the upper surface and/or the lower surface of any of the above substrate structures, and the semiconductor device may include a transistor, a diode, or Other electrical devices.
- the illustration is merely an example, and the invention is not limited thereto.
- the semiconductor substrate having the punch-through isolation, the semiconductor device, and the method of fabricating the same are described in detail above.
- the isolation region penetrating through the substrate the device structure can be formed by using the two surfaces of the substrate, thereby improving the utilization ratio of the substrate. And improve the integration of the device.
- a heat sink can be further formed to improve the heat dissipation performance of the device.
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Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/376,731 US9607877B2 (en) | 2010-10-21 | 2011-03-04 | Substrate structure, semiconductor device, and method for manufacturing the same |
GB1202556.5A GB2488869B (en) | 2010-10-21 | 2011-03-04 | Substrate structure, semiconductor device, and method for manufacturing the same |
Applications Claiming Priority (2)
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CN201010520798.4 | 2010-10-21 | ||
CN2010105207984A CN102456689A (zh) | 2010-10-21 | 2010-10-21 | 一种衬底结构、半导体器件及其制造方法 |
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WO2012051820A1 true WO2012051820A1 (zh) | 2012-04-26 |
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PCT/CN2011/071224 WO2012051820A1 (zh) | 2010-10-21 | 2011-03-04 | 衬底结构、半导体器件及其制造方法 |
Country Status (3)
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US (1) | US9607877B2 (zh) |
CN (1) | CN102456689A (zh) |
WO (1) | WO2012051820A1 (zh) |
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CN104355284B (zh) * | 2014-10-13 | 2016-06-29 | 华东光电集成器件研究所 | 一种mems器件双面对通介质隔离结构及制备方法 |
US10546816B2 (en) * | 2015-12-10 | 2020-01-28 | Nexperia B.V. | Semiconductor substrate with electrically isolating dielectric partition |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080224257A1 (en) * | 2007-03-12 | 2008-09-18 | Denso Corporation | Semiconductor device |
CN101673701A (zh) * | 2008-09-09 | 2010-03-17 | 中芯国际集成电路制造(北京)有限公司 | 形成浅沟槽隔离结构的方法及浅沟槽隔离结构 |
CN101783314A (zh) * | 2009-01-21 | 2010-07-21 | 台湾积体电路制造股份有限公司 | 形成隔离结构的方法和相应的器件 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5144401A (en) * | 1987-02-26 | 1992-09-01 | Kabushiki Kaisha Toshiba | Turn-on/off driving technique for insulated gate thyristor |
JPH0254554A (ja) * | 1988-08-19 | 1990-02-23 | Fujitsu Ltd | 半導体装置およびその製造方法 |
US5811315A (en) * | 1997-03-13 | 1998-09-22 | National Semiconductor Corporation | Method of forming and planarizing deep isolation trenches in a silicon-on-insulator (SOI) structure |
US6159586A (en) * | 1997-09-25 | 2000-12-12 | Nitto Denko Corporation | Multilayer wiring substrate and method for producing the same |
JPH11186389A (ja) * | 1997-12-24 | 1999-07-09 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6492684B2 (en) * | 1998-01-20 | 2002-12-10 | International Business Machines Corporation | Silicon-on-insulator chip having an isolation barrier for reliability |
US6133610A (en) * | 1998-01-20 | 2000-10-17 | International Business Machines Corporation | Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture |
GB0022329D0 (en) * | 2000-09-12 | 2000-10-25 | Mitel Semiconductor Ltd | Semiconductor device |
JP3510576B2 (ja) * | 2000-09-28 | 2004-03-29 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
GB2372631B (en) * | 2001-02-22 | 2005-08-03 | Mitel Semiconductor Ltd | Semiconductor-on-insulator structure |
CN1476073A (zh) * | 2002-08-12 | 2004-02-18 | 矽统科技股份有限公司 | 浅沟槽隔离构造及其制造方法 |
US7820519B2 (en) * | 2006-11-03 | 2010-10-26 | Freescale Semiconductor, Inc. | Process of forming an electronic device including a conductive structure extending through a buried insulating layer |
US8278731B2 (en) | 2007-11-20 | 2012-10-02 | Denso Corporation | Semiconductor device having SOI substrate and method for manufacturing the same |
CN101640182B (zh) * | 2008-07-31 | 2011-05-04 | 中芯国际集成电路制造(北京)有限公司 | 形成浅沟槽隔离结构的方法及半导体器件的制造方法 |
CN101777513A (zh) * | 2009-01-09 | 2010-07-14 | 中芯国际集成电路制造(上海)有限公司 | 改善栅氧化层生长的方法以及浅沟槽隔离工艺的制作方法 |
JP5438384B2 (ja) * | 2009-06-05 | 2014-03-12 | 新光電気工業株式会社 | 樹脂基板における高周波線路構造及びその製造方法 |
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2010
- 2010-10-21 CN CN2010105207984A patent/CN102456689A/zh active Pending
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2011
- 2011-03-04 US US13/376,731 patent/US9607877B2/en active Active
- 2011-03-04 WO PCT/CN2011/071224 patent/WO2012051820A1/zh active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080224257A1 (en) * | 2007-03-12 | 2008-09-18 | Denso Corporation | Semiconductor device |
CN101673701A (zh) * | 2008-09-09 | 2010-03-17 | 中芯国际集成电路制造(北京)有限公司 | 形成浅沟槽隔离结构的方法及浅沟槽隔离结构 |
CN101783314A (zh) * | 2009-01-21 | 2010-07-21 | 台湾积体电路制造股份有限公司 | 形成隔离结构的方法和相应的器件 |
Also Published As
Publication number | Publication date |
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US9607877B2 (en) | 2017-03-28 |
US20120261790A1 (en) | 2012-10-18 |
CN102456689A (zh) | 2012-05-16 |
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