WO2012026182A1 - 半導体発光素子の実装方法 - Google Patents
半導体発光素子の実装方法 Download PDFInfo
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- WO2012026182A1 WO2012026182A1 PCT/JP2011/063168 JP2011063168W WO2012026182A1 WO 2012026182 A1 WO2012026182 A1 WO 2012026182A1 JP 2011063168 W JP2011063168 W JP 2011063168W WO 2012026182 A1 WO2012026182 A1 WO 2012026182A1
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims description 105
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000000919 ceramic Substances 0.000 abstract description 20
- 150000004767 nitrides Chemical class 0.000 description 34
- 230000015572 biosynthetic process Effects 0.000 description 14
- 229910052594 sapphire Inorganic materials 0.000 description 6
- 239000010980 sapphire Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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Definitions
- the present invention relates to a mounting method of a flip-chip mounting type semiconductor light emitting element.
- FIG. 5 is a cross-sectional view of the LED chip 1 using a sapphire substrate.
- the LED chip 1 includes a sapphire substrate 2, an n-type nitride semiconductor layer 3, a p-type nitride semiconductor layer 4, a negative electrode 5, and a positive electrode 6.
- a forward voltage between the negative electrode 5 and the positive electrode 6, in the active layer 4a in the vicinity of the boundary between the n-type nitride semiconductor layer 3 and the p-type nitride semiconductor layer 4 electrons and holes Combine to emit light.
- Negative electrode 5 is formed on the upper surface of n-type nitride semiconductor layer 3, while positive electrode 6 is the upper surface of p-type nitride semiconductor layer 4 stacked on the upper surface of n-type nitride semiconductor layer 3. Therefore, there is a height difference H between the upper surface of the negative electrode 5 and the upper surface of the positive electrode 6. For this reason, when the LED chip 1 is mounted on the ceramic substrate by the flip chip mounting method, there are the following problems.
- FIG. 6 is a cross-sectional view showing a state in which the LED chip 1 is mounted on the ceramic substrate 9 via the two bumps 10a and 10b.
- the bumps 10a and 10b have the same size, the bump 10a is formed on the negative electrode 5 of the LED chip 1, and the bump 10b is formed on the positive electrode 6 of the LED chip 1.
- the heights of the surfaces of the bumps 10a and 10b are also different. Therefore, when the LED chip 1 is flip-chip mounted on the ceramic substrate 9 in the state shown in FIG. 6, the LED chip 1 is inclined with respect to the ceramic substrate 9 and the directivity of the emitted light from the LED chip 1 is deteriorated. .
- FIG. 7 is a graph showing the relationship between the load applied to the entire LED chip 1 and the deformation amount of the bumps 10a and 10b.
- the bump 10b when the bump 10b is deformed by 10 ⁇ m, it is necessary to apply a load of about 14 N / mm 2 to the entire LED chip 1, whereas when the bump 10a is deformed by 10 ⁇ m, the entire LED chip 1 is about 20 N / mm 2 . It is necessary to apply a load.
- the load applied to the entire LED chip 1 is increased by about 1.5 times. Therefore, when the bumps 10a and 10b are crushed to absorb the difference in height between the bumps 10a and 10b, there is a problem that a large load is applied to the element below the positive electrode 6 and the element is damaged.
- the tip of the capillary is melted at the tip of the metal wire to form a ball (bump), and the ball is fixed to the electrode surface and then the electrode surface.
- a method is described in which the height of the ball is made uniform by sliding the tip of the capillary on the ball substantially in parallel.
- JP 2002-118137 A (published April 19, 2002)”
- Patent Document 1 has a problem that it takes a long time to create bumps because the tip of the capillary slides on the ball after the ball is fixed to the electrode surface.
- the present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a method for mounting a semiconductor light emitting device having excellent light emitting characteristics and productivity.
- a method for mounting a semiconductor light emitting device includes a first conductive semiconductor layer and a second conductive semiconductor layer laminated on a part of the upper surface of the first conductive semiconductor layer.
- a first electrode part formed on another part of the upper surface of the first conductive type semiconductor layer, and a second electrode part formed on the upper surface of the second conductive type semiconductor layer.
- a semiconductor light emitting device mounting method for mounting a semiconductor light emitting device on a substrate via a bump with respect to a mold semiconductor layer, the semiconductor light emitting device having a top surface of the second electrode portion higher than the top surface of the first electrode portion, A resist is laminated on the first electrode portion and the second electrode portion, a first opening is formed in a portion of the resist corresponding to the first electrode portion, and the resist is formed on the second electrode portion.
- An opening forming step of forming a second opening in a corresponding portion, and the first opening And a bump forming step for forming the first bump and the second bump, a resist removing step for removing the resist, and a bonding for bonding the first bump and the second bump to the substrate, respectively.
- a cross-sectional area of the first opening is larger than a cross-sectional area of the second opening.
- the semiconductor light emitting device has a structure in which the upper surface of the second electrode portion is higher than the upper surface of the first electrode portion, bumps having the same height are formed on the first electrode portion and the second electrode portion. In the case of bonding to the substrate, the semiconductor light emitting element is inclined with respect to the substrate.
- each of the portions corresponding to the first electrode portion and the second electrode portion of the resist has the first.
- An opening and a second opening are formed, and the cross-sectional area of the first opening is larger than the cross-sectional area of the second opening.
- the formation speed of the first bump is higher than the formation speed of the second bump, so that the first bump can be formed higher than the second bump. Therefore, the height difference between the upper surface of the first bump and the upper surface of the second bump can be made smaller than the height difference between the upper surface of the first electrode portion and the upper surface of the second electrode portion.
- bumps having different heights can be formed only by changing the cross-sectional areas of the resist openings, so that the bumps are formed in a short time unlike the invention according to Patent Document 1. can do. Therefore, it is possible to provide a method for mounting a semiconductor light emitting device having excellent light emission characteristics and productivity.
- a resist is stacked on the first electrode portion and the second electrode portion, and a portion corresponding to the first electrode portion of the resist is formed.
- the cross-sectional area of the part is larger than the cross-sectional area of the second opening. Therefore, it is possible to provide a method for mounting a semiconductor light emitting device having excellent light emission characteristics and productivity.
- FIGS. 1 to 5 An embodiment of the present invention will be described with reference to FIGS. 1 to 5 as follows.
- FIG. 1 is a diagram illustrating a mounting method according to the present embodiment. Specifically, FIG. 1A is a cross-sectional view showing a state in which bumps 11 and 12 are formed on the LED chip 1, and FIG. 1B is a view from the electrode side of the LED chip 1 in this state. FIG. 1C is a cross-sectional view showing a state in which the LED chip 1 shown in FIG.
- the LED chip 1 is the same as that shown in FIG. That is, as shown in FIG. 5, the LED chip (semiconductor light emitting device) 1 includes a sapphire substrate 2, an n-type nitride semiconductor layer (first conductivity type semiconductor layer) 3, and a p-type nitride semiconductor layer (second conductivity type). A semiconductor layer 4, a negative electrode (first electrode portion) 5, and a positive electrode (second electrode portion) 6 are provided. The n-type nitride semiconductor layer 3 is laminated on the sapphire substrate 2, and one end of the upper surface is exposed.
- the p-type nitride semiconductor layer 4 is stacked on a part of the upper surface of the n-type nitride semiconductor layer 3, and the negative electrode 5 is formed on the other part of the upper surface of the n-type nitride semiconductor layer 3. Yes.
- the positive electrode 6 is formed on the upper surface of the p-type nitride semiconductor layer 4.
- Negative electrode 5 is formed on the upper surface of n-type nitride semiconductor layer 3, while positive electrode 6 is the upper surface of p-type nitride semiconductor layer 4 stacked on the upper surface of n-type nitride semiconductor layer 3. Therefore, there is a height difference H between the upper surface of the negative electrode 5 and the upper surface of the positive electrode 6. For this reason, when bumps having the same height are formed on the negative electrode 5 and the positive electrode 6 and bonded to the ceramic substrate, the LED chip 1 is inclined with respect to the ceramic substrate.
- bumps 11 are formed on the negative electrode 5 as bumps for flip-chip mounting the LED chip 1
- the positive A bump 12 is formed on the electrode 6, and the height of the bump 11 is larger than the height of the bump 12 with respect to the size of the bumps 11 and 12.
- the cross-sectional area of the bump 11 is larger than the cross-sectional area of the bump 12.
- the upper surface of the bump 11 and the upper surface of the bump 12 have substantially the same height with respect to the n-type nitride semiconductor layer 3. Therefore, as shown in FIG. 1C, when the LED chip 1 is flip-chip mounted on the ceramic substrate 9, the n-type nitride semiconductor layer 3 and the p-type nitride semiconductor layer 4 of the LED chip 1 are formed on the ceramic substrate 9. Parallel to. Therefore, the directivity of the emitted light from the LED chip 1 is improved.
- the bumps 11 and 12 for flip-chip mounting the LED chip 1 are formed by Au plating by an electrolytic plating method.
- FIG. 2 shows the LED chip 1 before bump formation.
- the power supply metal 15 is formed on the surface of the LED chip 1 on the electrode side by sputtering.
- the power supply metal 15 includes an Au film serving as a seed layer and a barrier film that prevents diffusion of Au into the ceramic substrate.
- a resist 16 is stacked on the negative electrode 5 and the positive electrode 6 and, as shown in FIG. 2C, patterning is performed to form an opening 16a (first portion) in a portion corresponding to the negative electrode 5 of the resist 16. 1 opening) is formed, and an opening 16b (second opening) is formed in a portion corresponding to the positive electrode 6 of the resist 16 (opening forming step).
- the openings 16a and 16b are formed so that the cross-sectional area of the opening 16a is larger than the cross-sectional area of the opening 16b.
- the formation speed of the bumps 11 is higher than the formation speed of the bumps 12, so that the bumps 11 can be formed higher than the bumps 12.
- FIG. 3 is a graph showing the relationship between the sectional area ratio of the opening 16a to the opening 16b and the height ratio of the bump 11 to the bump 12. As shown by the solid line, it can be seen that when the resist 16 is sufficiently thick, the height ratio increases as the cross-sectional area ratio increases.
- the cross-sectional areas of the openings 16a and 16b are selected based on the height difference between the negative electrode 5 and the positive electrode 6. Specifically, the sectional areas of the openings 16a and 16b are set so that the height difference between the bump 11 and the bump 12 is equal to the height difference between the negative electrode 5 and the positive electrode 6. For example, the cross-sectional area of the opening 16b is set to about 300 to 5000 ⁇ m 2 . Thereby, as shown in FIG. 2E, the upper surface of the bump 11 and the upper surface of the bump 12 have substantially the same height with respect to the n-type nitride semiconductor layer 3.
- the height ratio of the bumps 11 and 12 hardly changes even if the cross-sectional area ratio of the openings 16a and 16b increases. Therefore, in the bump forming step shown in FIG. 2D, the height of each upper surface of the bump 11 and the bump 12 with respect to the n-type nitride semiconductor layer 3 and the height of the upper surface of the resist 16 with respect to the n-type nitride semiconductor layer 3 It is desirable that the difference between the two is 10 ⁇ m or more. Thereby, the height of the bumps 11 and 12 can be easily controlled.
- the height of the bumps 11 and 12 with respect to the n-type nitride semiconductor layer 3 is controlled by controlling the height of the bumps 11 and 12. Can be aligned. Thereby, it becomes possible to mount the LED chip 1 on the ceramic substrate 9 without deteriorating contact resistance and mechanical strength, and the directivity of the emitted light from the LED chip 1 is improved.
- FIG. 4 is a view showing a modification of the mounting method according to the present embodiment.
- FIG. 4A is a cross-sectional view showing a state in which one bump 11 and three bumps 12 are formed on the LED chip 1
- FIG. 4B shows the state.
- FIG. 4C is a cross-sectional view showing a state in which the LED chip 1 shown in FIG. 4A is mounted on the ceramic substrate 9.
- the configuration shown in FIG. 4 is the same as the configuration shown in FIG. 1 except that three bumps 12 are formed on the positive electrode 6 of the LED chip 1.
- the sectional area of the bump 12 is smaller than the sectional area of the bump 11.
- the load on the bump 11 and the load on the bump 12 are substantially equal. Therefore, in the state shown in FIG. 1C, the bump 12 is more easily deformed than the bump 11.
- the bonding area between the bump 12 and the positive electrode 6 is small, the bonding strength may be insufficient or the contact resistance may increase.
- the number of the openings 16b is the number of the openings in the opening forming step shown in FIG. What is necessary is just to make it more than the number of 16a.
- the number of bumps 11 is one, but a plurality of bumps 11 may be formed.
- the number of openings 16b is set to a number that minimizes the difference between the sum of the cross-sectional areas of the openings 16a and the sum of the cross-sectional areas of the openings 16b. To do. For example, when there is one opening 16a and the ratio of the cross-sectional area of the opening 16a to the cross-sectional area of the opening 16b is 7: 3, two openings 16b are formed. When the ratio is 8: 3, three openings 16b are formed.
- the number of openings 16a and 16b (that is, the number of bumps 11 and 12) is set so that the difference between the sum of the cross-sectional areas of the bumps 11 and the sum of the cross-sectional areas of the bumps 12 is small.
- the number of openings 16a and 16b that is, the number of bumps 11 and 12
- the difference between the sum of the cross-sectional areas of the bumps 11 and the sum of the cross-sectional areas of the bumps 12 is small.
- the cross-sectional area of the opening 16a is 10 times or less the cross-sectional area of the opening 16b.
- the upper limit of the height ratio of the bumps 11 and 12 is about 1.2. Therefore, the LED chip 1 to which the mounting method according to this embodiment is applied has an elevation difference H (see FIG. 5) between the upper surface of the negative electrode 5 and the upper surface of the positive electrode 6 with respect to the n-type nitride semiconductor layer 3. It is desirable that it is 2 ⁇ m or less.
- the bump is formed by the electrolytic plating method, but the bump may be formed by using another method such as a pad method.
- the LED chip 1 has a structure in which the positive electrode 6 is positioned higher than the negative electrode 5, but the structure in which the negative electrode 5 is positioned higher than the positive electrode 6 may be used.
- the n-type nitride semiconductor layer 3 is laminated on the upper surface of the p-type nitride semiconductor layer 4, the positive electrode 6 is formed on the upper surface of the p-type nitride semiconductor layer 4, and the upper surface of the n-type nitride semiconductor layer 3.
- the negative electrode 5 is formed on the surface.
- the mounting method of the semiconductor light emitting device includes the first conductive semiconductor layer, the second conductive semiconductor layer laminated on a part of the upper surface of the first conductive semiconductor layer, and the first conductive layer.
- a first electrode portion formed on another part of the upper surface of the conductive semiconductor layer; and a second electrode portion formed on the upper surface of the second conductive semiconductor layer, the first conductive semiconductor layer comprising:
- a semiconductor light emitting device mounting method in which a semiconductor light emitting device in which a top surface of the second electrode portion is higher than a top surface of the first electrode portion is mounted on a substrate via a bump, the first electrode A resist is laminated on the part and the second electrode part, a first opening is formed in a part of the resist corresponding to the first electrode part, and a part of the resist corresponding to the second electrode part is formed.
- An opening forming step for forming the second opening, the inside of the first opening, and the second A bump forming step for forming the first bump and the second bump in the mouth portion, a resist removing step for removing the resist, and a bonding step for bonding the first bump and the second bump to the substrate, respectively.
- the cross-sectional area of the first opening is larger than the cross-sectional area of the second opening.
- the semiconductor light emitting device has a structure in which the upper surface of the second electrode portion is higher than the upper surface of the first electrode portion, bumps having the same height are formed on the first electrode portion and the second electrode portion. In the case of bonding to the substrate, the semiconductor light emitting element is inclined with respect to the substrate.
- each of the portions corresponding to the first electrode portion and the second electrode portion of the resist has the first.
- An opening and a second opening are formed, and the cross-sectional area of the first opening is larger than the cross-sectional area of the second opening.
- the formation speed of the first bump is higher than the formation speed of the second bump, so that the first bump can be formed higher than the second bump. Therefore, the height difference between the upper surface of the first bump and the upper surface of the second bump can be made smaller than the height difference between the upper surface of the first electrode portion and the upper surface of the second electrode portion.
- bumps having different heights can be formed only by changing the cross-sectional areas of the resist openings, so that the bumps are formed in a short time unlike the invention according to Patent Document 1. can do. Therefore, it is possible to provide a method for mounting a semiconductor light emitting device having excellent light emission characteristics and productivity.
- the number of the second openings is preferably larger than the number of the first openings.
- the cross-sectional area of the first bump is larger than the case where one each of the first bump and the second bump is formed.
- the difference between the sum and the sum of the cross-sectional areas of the second bumps can be reduced. Therefore, it is possible to improve the bonding strength and reduce the contact resistance.
- the number of the second openings is the number that minimizes the difference between the sum of the cross-sectional areas of the first openings and the sum of the cross-sectional areas of the second openings. It is preferable that
- the upper surface of the first bump and the upper surface of the second bump have substantially the same height as the first conductive semiconductor layer.
- the semiconductor light emitting element can be mounted in parallel to the substrate, the light emission characteristics of the semiconductor light emitting element can be further improved.
- the height of each upper surface of the first bump and the second bump with respect to the first conductivity type semiconductor layer and the first surface of the upper surface of the resist is preferably 10 ⁇ m or more.
- the first bump can be formed more easily than the second bump.
- the cross-sectional area of the first opening is preferably 10 times or less the cross-sectional area of the second opening.
- the height difference between the upper surface of the first electrode portion and the upper surface of the second electrode portion with respect to the first conductive semiconductor layer is preferably 2 ⁇ m or less.
- the mounting method of the present invention is suitable for mounting a semiconductor light emitting element having two electrodes having a height difference on a substrate.
- LED chip semiconductor light emitting device
- N-type nitride semiconductor layer first conductivity type semiconductor layer
- second conductivity type semiconductor layer second conductivity type semiconductor layer
- Active layer 5 Negative electrode (first electrode part) 6 Positive electrode (second electrode part) 9 Ceramic substrate (substrate) 10a Bump 10b Bump 11 Bump (first bump) 12 Bump (second bump) 15 Feed metal 16 Resist 16a Opening (first opening) 16b opening (second opening)
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- Led Devices (AREA)
Abstract
Description
図1は、本実施形態に係る実装方法を示す図である。具体的には、図1の(a)は、LEDチップ1にバンプ11・12を形成した状態を示す断面図であり、図1の(b)は、当該状態におけるLEDチップ1の電極側からの平面図であり、図1の(c)は、図1の(a)に示すLEDチップ1をセラミック基板9に実装した状態を示す断面図である。
続いて、LEDチップ1の実装方法の具体的内容について、図2を参照して説明する。本実施形態では、LEDチップ1をフリップチップ実装するためのバンプ11・12を、電解メッキ法によるAuメッキで形成する。
上記の構成では、LEDチップ1の負電極5上および正電極6上に、それぞれ1つのバンプを形成していた。これに対し、以下では、正電極6上に複数のバンプを形成することにより、接合強度の向上および接触抵抗の低減を実現する構成について説明する。
なお、上述した実施形態では、電解メッキ法によってバンプを形成したが、パッド法などの他の方法を用いてバンプを形成してもよい。また、LEDチップ1は、正電極6が負電極5よりも高い位置にある構造であったが、負電極5が正電極6よりも高い位置にある構造であってもよい。この場合、p型窒化物半導体層4の上面にn型窒化物半導体層3が積層され、p型窒化物半導体層4の上面に正電極6が形成され、n型窒化物半導体層3の上面に負電極5が形成される。
以上のように、本発明に係る半導体発光素子の実装方法は、第1導電型半導体層と、第1導電型半導体層の上面の一部に積層された第2導電型半導体層と、第1導電型半導体層の上面の他の一部に形成された第1電極部と、第2導電型半導体層の上面に形成された第2電極部と、を備え、上記第1導電型半導体層に対して、上記第2電極部の上面が上記第1電極部の上面より高い位置にある半導体発光素子を、バンプを介して基板に実装する半導体発光素子の実装方法であって、上記第1電極部上および上記第2電極部上にレジストを積層して、当該レジストの上記第1電極部に対応する部分に第1開口部を形成し、当該レジストの上記第2電極部に対応する部分に第2開口部を形成する開口部形成工程と、上記第1開口部内および上記第2開口部内にそれぞれ、第1バンプおよび第2バンプを形成するバンプ形成工程と、上記レジストを除去するレジスト除去工程と、上記第1バンプおよび上記第2バンプを上記基板にボンディングするボンディング工程と、を有し、上記第1開口部の断面積は、上記第2開口部の断面積よりも大きいことを特徴としている。
2 サファイア基板
3 n型窒化物半導体層(第1導電型半導体層)
4 p型窒化物半導体層(第2導電型半導体層)
4a 活性層
5 負電極(第1電極部)
6 正電極(第2電極部)
9 セラミック基板(基板)
10a バンプ
10b バンプ
11 バンプ(第1バンプ)
12 バンプ(第2バンプ)
15 給電メタル
16 レジスト
16a 開口部(第1開口部)
16b 開口部(第2開口部)
Claims (7)
- 第1導電型半導体層と、
第1導電型半導体層の上面の一部に積層された第2導電型半導体層と、
第1導電型半導体層の上面の他の一部に形成された第1電極部と、
第2導電型半導体層の上面に形成された第2電極部と、を備え、
上記第1導電型半導体層に対して、上記第2電極部の上面が上記第1電極部の上面より高い位置にある半導体発光素子を、バンプを介して基板に実装する半導体発光素子の実装方法であって、
上記第1電極部上および上記第2電極部上にレジストを積層して、当該レジストの上記第1電極部に対応する部分に第1開口部を形成し、当該レジストの上記第2電極部に対応する部分に第2開口部を形成する開口部形成工程と、
上記第1開口部内および上記第2開口部内にそれぞれ、第1バンプおよび第2バンプを形成するバンプ形成工程と、
上記レジストを除去するレジスト除去工程と、
上記第1バンプおよび上記第2バンプを上記基板にボンディングするボンディング工程と、を有し、
上記第1開口部の断面積は、上記第2開口部の断面積よりも大きいことを特徴とする半導体発光素子の実装方法。 - 上記第2開口部の個数が上記第1開口部の個数よりも多いことを特徴とする請求項1に記載の半導体発光素子の実装方法。
- 上記第2開口部の個数は、上記第1開口部の断面積の総和と上記第2開口部の断面積の総和との差が最小となる個数であることを特徴とする請求項2に記載の半導体発光素子の実装方法。
- 上記第1バンプの上面と上記第2バンプの上面とは、上記第1導電型半導体層に対する高さが略同一であることを特徴とする請求項1、2または3に記載の半導体発光素子の実装方法。
- 上記バンプ形成工程において、上記第1バンプおよび上記第2バンプの各上面の上記第1導電型半導体層に対する高さと、上記レジストの上面の上記第1導電型半導体層に対する高さとの差が、10μm以上であることを特徴とする請求項1~4のいずれか1項に記載の半導体発光素子の実装方法。
- 上記第1開口部の断面積は、上記第2開口部の断面積の10倍以下であることを特徴とする請求項1~5のいずれか1項に記載の半導体発光素子の実装方法。
- 上記第1導電型半導体層に対する、上記第1電極部の上面と上記第2電極部の上面との高低差が、2μm以下であることを特徴とする請求項1~6のいずれか1項に記載の半導体発光素子の実装方法。
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US13/697,766 US9048407B2 (en) | 2010-08-26 | 2011-06-08 | Mounting method for semiconductor light emitter using resist with openings of different sizes |
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JP6143104B2 (ja) | 2012-12-05 | 2017-06-07 | 株式会社村田製作所 | バンプ付き電子部品及びバンプ付き電子部品の製造方法 |
JP6229406B2 (ja) * | 2013-09-27 | 2017-11-15 | 日亜化学工業株式会社 | 半導体発光素子及びその製造方法 |
EP3200250B1 (en) * | 2014-09-26 | 2020-09-02 | Toshiba Hokuto Electronics Corp. | Production method for light-emission module |
KR101805074B1 (ko) * | 2016-12-20 | 2017-12-06 | 에스케이씨 주식회사 | 세라믹 다층회로 기판의 제조방법 |
US11024608B2 (en) | 2017-03-28 | 2021-06-01 | X Display Company Technology Limited | Structures and methods for electrical connection of micro-devices and substrates |
WO2019150825A1 (ja) | 2018-02-01 | 2019-08-08 | パナソニックIpマネジメント株式会社 | 半導体装置 |
JP7273280B2 (ja) * | 2018-06-15 | 2023-05-15 | 日亜化学工業株式会社 | 発光モジュールおよび発光モジュールの製造方法 |
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US11101417B2 (en) * | 2019-08-06 | 2021-08-24 | X Display Company Technology Limited | Structures and methods for electrically connecting printed components |
US11316086B2 (en) | 2020-07-10 | 2022-04-26 | X Display Company Technology Limited | Printed structures with electrical contact having reflowable polymer core |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002118137A (ja) * | 2000-07-31 | 2002-04-19 | Nichia Chem Ind Ltd | 半導体発光素子チップとそのバンプ形成方法及びその半導体発光素子チップを用いたディスプレイとセグメント表示部 |
JP2003273408A (ja) * | 2000-07-31 | 2003-09-26 | Nichia Chem Ind Ltd | 発光装置 |
JP2004103975A (ja) * | 2002-09-12 | 2004-04-02 | Citizen Watch Co Ltd | 光半導体素子の製造方法と光半導体素子およびその光半導体素子を実装した光半導体装置 |
JP2004153110A (ja) * | 2002-10-31 | 2004-05-27 | Nichia Chem Ind Ltd | 窒化物系光学素子及びその製造方法 |
JP2005136399A (ja) * | 2003-10-07 | 2005-05-26 | Matsushita Electric Ind Co Ltd | 半導体素子の実装方法、及び半導体素子実装基板 |
JP2006074007A (ja) * | 2004-08-06 | 2006-03-16 | Matsushita Electric Ind Co Ltd | 発光光源、発光光源の製造方法、照明装置及び表示装置 |
WO2009063638A1 (ja) * | 2007-11-15 | 2009-05-22 | Panasonic Corporation | 半導体発光装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63245922A (ja) * | 1987-04-01 | 1988-10-13 | Hitachi Ltd | X線露光用マスク |
JP2897297B2 (ja) * | 1989-12-19 | 1999-05-31 | 富士通株式会社 | 半導体装置の製造方法 |
US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
JP2003142829A (ja) * | 2001-11-07 | 2003-05-16 | Daiwa Kogyo:Kk | 多層配線基板及びその製造方法 |
JP4051273B2 (ja) * | 2002-08-30 | 2008-02-20 | 日本特殊陶業株式会社 | 配線基板及び配線基板の製造方法 |
JP2004335660A (ja) * | 2003-05-06 | 2004-11-25 | Sony Corp | 半導体装置及びその製造方法、並びに配線基板及びその製造方法 |
TW200520123A (en) * | 2003-10-07 | 2005-06-16 | Matsushita Electric Ind Co Ltd | Method for mounting semiconductor chip and semiconductor chip-mounted board |
US7566650B2 (en) * | 2005-09-23 | 2009-07-28 | Stats Chippac Ltd. | Integrated circuit solder bumping system |
KR20090032207A (ko) * | 2007-09-27 | 2009-04-01 | 삼성전기주식회사 | 질화갈륨계 발광다이오드 소자 |
-
2010
- 2010-08-26 JP JP2010189382A patent/JP5226047B2/ja active Active
-
2011
- 2011-06-08 WO PCT/JP2011/063168 patent/WO2012026182A1/ja active Application Filing
- 2011-06-08 US US13/697,766 patent/US9048407B2/en active Active
- 2011-06-08 KR KR1020127031364A patent/KR20130023261A/ko not_active Application Discontinuation
- 2011-06-08 CN CN201180026204.7A patent/CN102918664B/zh active Active
- 2011-06-23 TW TW100122079A patent/TWI429114B/zh active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002118137A (ja) * | 2000-07-31 | 2002-04-19 | Nichia Chem Ind Ltd | 半導体発光素子チップとそのバンプ形成方法及びその半導体発光素子チップを用いたディスプレイとセグメント表示部 |
JP2003273408A (ja) * | 2000-07-31 | 2003-09-26 | Nichia Chem Ind Ltd | 発光装置 |
JP2004103975A (ja) * | 2002-09-12 | 2004-04-02 | Citizen Watch Co Ltd | 光半導体素子の製造方法と光半導体素子およびその光半導体素子を実装した光半導体装置 |
JP2004153110A (ja) * | 2002-10-31 | 2004-05-27 | Nichia Chem Ind Ltd | 窒化物系光学素子及びその製造方法 |
JP2005136399A (ja) * | 2003-10-07 | 2005-05-26 | Matsushita Electric Ind Co Ltd | 半導体素子の実装方法、及び半導体素子実装基板 |
JP2006074007A (ja) * | 2004-08-06 | 2006-03-16 | Matsushita Electric Ind Co Ltd | 発光光源、発光光源の製造方法、照明装置及び表示装置 |
WO2009063638A1 (ja) * | 2007-11-15 | 2009-05-22 | Panasonic Corporation | 半導体発光装置 |
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