WO2012024371A2 - Track and hold architecture with tunable bandwidth - Google Patents

Track and hold architecture with tunable bandwidth Download PDF

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Publication number
WO2012024371A2
WO2012024371A2 PCT/US2011/048037 US2011048037W WO2012024371A2 WO 2012024371 A2 WO2012024371 A2 WO 2012024371A2 US 2011048037 W US2011048037 W US 2011048037W WO 2012024371 A2 WO2012024371 A2 WO 2012024371A2
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WO
WIPO (PCT)
Prior art keywords
coupled
transistor
circuit
adc
electrode
Prior art date
Application number
PCT/US2011/048037
Other languages
English (en)
French (fr)
Other versions
WO2012024371A3 (en
Inventor
Robert F. Payne
Marco Corsi
Original Assignee
Texas Instruments Incorporated
Texas Instruments Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Incorporated, Texas Instruments Japan Limited filed Critical Texas Instruments Incorporated
Priority to JP2013525986A priority Critical patent/JP5940537B2/ja
Priority to CN201180036519.XA priority patent/CN103026630B/zh
Publication of WO2012024371A2 publication Critical patent/WO2012024371A2/en
Publication of WO2012024371A3 publication Critical patent/WO2012024371A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Definitions

  • ADCs analog-to-digital converters
  • TI time-interleaved ADCs
  • FIG. 1 shows a conventional analog-to-digital converter (ADC) 100.
  • ADC 100 generally comprises a track- and-hold (T/H) circuit 102 and a sub- ADC 104 implemented so that, in operation, the ADC 100 can sample an analog input signal X(t) at a plurality of sampling instants and convert the sampled signal into a digital signal Y[n].
  • the T/H circuit 104 generally comprises switches and capacitors. The switch has a non-zero resistance, which causes the T/H circuit 102 to function as a filter (typically a single pole low pass filter).
  • FIG. 2 a model 200 of the ADC 100 is shown.
  • the filter aspects of the ADC 100 are represented by filter 202, while the remainder of the functionality of the ADC 100 is represented by ideal ADC 204.
  • Filter 202 has a transfer function in the time- domain of h a (t) , which can, in turn, be represented in the frequency-domain as:
  • g a is the gain of ADC 100
  • ⁇ ⁇ is the time delay relative to a reference
  • 6> a is the cutoff frequency (bandwidth).
  • This model 200 can be useful when determining mismatches for ADCs from, for example, Texas Instruments (TI).
  • TI ADC 300 generally comprises ADCs 100-1 to 100-M (where each of ADCs 100-1 to 100-M generally has the same structure as ADC 100 from FIG. 1) that are clocked by divider 302 so that the outputs from ADCs 100-1 to 100-M can be multiplexed by multiplexer 304 to produce digital signal Y[n]. Yet, when building TI ADC 300, ADCs 100-1 to 100-M are not identical to each other; there are slight structural and operational variations. These slight variations result in direct current (DC) offset mismatches, timing skew, gain mismatches, and bandwidth mismatches between ADCs 100-1 to 100-M.
  • DC direct current
  • the output spectrum when the input signal is a tone with frequency CO* can be re resented as follows:
  • SFDR Spurious-Free Dynamic Range
  • Ts is the period of clock signal CLK.
  • An example of a simulation of the effect bandwidth mismatch can be seen in FIG. 3B for different gain and skew compensations.
  • the bandwidths of ADCs within the TI ADC should be matched to be within 0.1% to 0.25%.
  • An example embodiment provides an apparatus that comprises a clock divider that receives a clock signal; a plurality analog-to-digital converter (ADC) branches that each receive an analog input signal, wherein each ADC branch includes: a delay circuit that is coupled to the clock divider; an ADC having: a bootstrap circuit that is coupled to the delay circuit; a sampling switch that is coupled to the bootstrap circuit; and a controller that is coupled to the bootstrap circuit to provide a control voltage to the bootstrap circuit so as to control a gate voltage of the sampling switch to adjust the impedance of the sampling switch when the sampling switch is actuated; a sampling capacitor that is coupled to the sampling switch; and a correction circuit that is coupled to the ADC; and a mismatch estimation circuit that is coupled to each delay circuit, each correction circuit, and each controller, wherein the mismatch estimation circuit provides a control signal to each controller to adjust for relative bandwidth mismatches between the ADC branches.
  • ADC analog-to-digital converter
  • the apparatus further comprises a multiplexer that is coupled to each ADC branch.
  • the correction circuit adjusts the output of its ADC to correct for DC offset and gain mismatch.
  • the bootstrap circuit further comprises: a boost capacitor that is charged during a hold phase of the ADC; a transistor having first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the transistor is coupled to the boost capacitor, and wherein the second passive electrode of the transistor is coupled to the sampling switch; a pass gate circuit that is coupled to the delay circuit, that is coupled to the control electrode of the transistor, and that receives the control voltage; and a skew circuit that is coupled to sampling switch and that is controlled by the control voltage.
  • the transistor further comprises a first transistor
  • the pass gate circuit further comprises: a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second transistor is coupled to the controller so as to receive the control voltage, and wherein the control electrode of the second transistor is coupled to the delay circuit, and wherein the second passive electrode of the second transistor is coupled to the control electrode of the first transistor; a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the third transistor is coupled to the second passive electrode of second transistor, and wherein the control electrode of the third transistor is coupled to the delay circuit; and a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fourth transistor is coupled to the control electrode of the first transistor, and wherein the control electrode of the fourth transistor is coupled to the sampling switch, and wherein the second passive electrode of the fourth transistor is coupled to the second
  • the skew circuit further comprises a fifth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the fifth transistor is coupled to the sampling switch, and wherein the control electrode of the fifth transistor is coupled to the controller so as to receive the control voltage.
  • the controller is a digital-to-analog converter (DAC).
  • DAC digital-to-analog converter
  • the controller is a charge pump.
  • an apparatus comprises a clock divider that receives a clock signal; a plurality ADC branches that each receive an analog input signal, wherein each ADC branch includes: a delay circuit that is coupled to the clock divider; an ADC having: a bootstrap circuit that is coupled to the delay circuit; a sampling switch that is coupled to the bootstrap circuit; a controller that is coupled to the bootstrap circuit to provide a control voltage to the bootstrap circuit so as to control a gate voltage of the sampling switch to adjust the impedance of the sampling switch when the sampling switch is actuated; a sampling capacitor that is coupled to the sampling switch; an output circuit that is coupled to the sampling capacitor; and a sub-ADC that is coupled to the output circuit; and an correction circuit that is coupled to the ADC; a mismatch estimation circuit that is coupled to each delay circuit, each correction circuit, and each controller, wherein the mismatch estimation circuit provides a control signal to each controller to adjust for relative bandwidth mismatches between the ADC branches; and a multiplex
  • an apparatus comprises a clock divider that receives a clock signal; a plurality ADC branches that each receive an analog input signal, wherein each ADC branch includes: a delay circuit that is coupled to the clock divider; an ADC having: a bootstrap circuit that is coupled to the delay circuit; a PMOS transistor that is coupled to the bootstrap circuit; a controller that is coupled to the bootstrap circuit to provide a control voltage to the bootstrap circuit so as to control a gate voltage of the sampling switch to adjust the impedance of the sampling switch when the sampling switch is actuated; a sampling capacitor that is coupled to the PMOS transistor at its drain; an output circuit that is coupled to the sampling capacitor; and a sub-ADC that is coupled to the output circuit; and an correction circuit that is coupled to the ADC, wherein the correction circuit adjusts the output of its ADC to correct for DC offset and gain mismatch; a mismatch estimation circuit that is coupled to each delay circuit, each correction circuit, and each controller, wherein the mis
  • the PMOS transistor further comprises a first PMOS transistor
  • the bootstrap circuit further comprises: a boost capacitor that is charged during a hold phase of the ADC; a second PMOS transistor that is coupled to the boost capacitor at its source and the gate of the first PMOS switch at its drain; a pass gate circuit that is coupled to the delay circuit, that is coupled to the gate of the second PMOS transistor, and that receives the control voltage; and a skew circuit that is coupled to sampling switch and that is controlled by the control voltage.
  • the pass gate circuit further comprises: a third PMOS transistor that is coupled to the controller at its source, the delay circuit at its gate, and the gate of the second PMOS transistor at its drain; a first NMOS transistor that is coupled to the drain of the third PMOS transistor at its drain and the delay circuit at its gate; and a second NMOS transistor that is coupled to the drain of the third PMOS transistor at its drain, the source of the first NMOS transistor at its source, and the gate of the first PMOS transistor at its gate.
  • the skew circuit further comprises a third NMOS transistor that is coupled to the gate of the first PMOS transistor at its drain and the controller at its gate.
  • the controller is a DAC or a charge pump.
  • FIG. 1 is a circuit diagram of a conventional ADC
  • FIG. 2 is a block diagram of a model of the ADC of FIG. 1;
  • FIG. 3A is a circuit diagram of a convention TI ADC using the ADC of FIG. 1;
  • FIG. 3B is an example of a simulation showing the effect of bandwidth mismatch on the Spurious-Free Dynamic Range (SFDR) of a TI ADC;
  • FIG. 4 is a circuit diagram of a TI ADC in accordance with an example embodiment of the invention.
  • FIG. 5 is a circuit diagram of the T/H circuit of FIG. 4;
  • FIG. 6 is a circuit diagram of the bootstrap circuit of 5.
  • FIG. 7 is a graph depicting the bandwidth for the T/H circuit of FIG. 5 versus "on" resistance of the sampling switch of the T/H circuit of FIG. 5.
  • the reference numeral 400 generally designates a TI ADC in accordance with an example embodiment of the invention.
  • ADC 400 generally comprises ADC branches 402-1 to 402-M, divider 404, multiplexer or mux 408, and a mismatch estimation circuit 410.
  • Each ADC branch 402-1 to 402-M also generally comprises (respectively) ADC 410-1 to 410-M, correction circuit 416-1 to 416-M, and adjustable delay element or circuit 418-1 to 418-M.
  • each ADC 410-1 to 410-M generally comprises (respectively) a T/H circuit 410-1 to 410-M and a sub-ADC 414-1 to 414-M.
  • TI ADC 400 converts analog input signal X(t) to a digital signal
  • divider 402 divides a clock signal CLK (with a frequency of F s or period of Ts) into M clock signals (each with a frequency of Fs/M) that are staggered by delay circuits 418-1 to 418-M and provided to ADCs 410-1 to 410-M. This allows each of ADCs 410- 1 to 410-M to convert the analog signal X(t) to digital signals Xi(k) to ⁇ ⁇ (3 ⁇ 4.
  • the gain and DC offset adjustments are applied to digital signals Xi(k) to X M (10 by correction circuits 416-1 to 416-M to generate digital signals Y[l] to Y[M], which can then be multiplexed by mux 408 to generate a digital signal Y[N].
  • mismatch estimation circuit 410 calculates and compensates for gain mismatches, DC offset mismatches, timing skews, and bandwidth mismatches.
  • the mismatch estimation circuit 410 is generally a digital signals processor (DSP) or dedicated hardware, which determines the gain mismatches, DC offset mismatches, timing skews, and bandwidth mismatches and which can provide adjustments for gain, DC offset, timing skew, and bandwidth to correction circuits 416-1 to 416- M and T/H circuits 412-1 to 412-M.
  • DSP digital signals processor
  • T/H circuits 412-1 to 412-M (hereinafter referred to as
  • T/H circuit 412 generally comprises a bootstrap circuit 502, a controller 504, a sampling switch SI (which is typically an NMOS transistor or NMOS switch), a sampling capacitor CSAMPLE, and an output circuit 506.
  • the bootstrap circuit 502 controls the actuation and de-actuation of the sampling switch SI based at least in part on a clock signal CLKIN (which is received from a respective delay circuit 418-1 to 418-M) and a control voltage VCNTL from controller 504.
  • the mismatch estimation circuit 406 provides a control signal to the controller 504 (which may be a digital-to-analog converter (DAC) or charge pump) to generate the control voltage VCNTL.
  • the control voltage VCNTL through the bootstrap circuit 502, is able to control the gate voltage of the sampling switch SI to adjust the impedance or "on" resistance of the sampling switch S I when the sampling switch SI is actuated.
  • the bootstrap circuit 502 can be seen in greater detail.
  • inverter 508 turns transistor Ql (which is typically an NMOS transistor) "on,” while pass gate circuit (which generally comprises transistors Q2, Q3, and Q5) maintains transistor Q4 (which is generally a PMOS transistor) in an “off state.
  • signal CLKZ is logic high so that transistors Q8 and Q9 (which are typically NMOS transistors) are in an "on” state and during this logic low period of clock signal CLKIN, supply voltage VDD charges the boost capacitor CBOOST.
  • pass gate circuit turns transistor Q4 "on,” while transistors Ql is turned “off.” At this point, a voltage is applied to the gate of sampling switch SI to turn it "on.”
  • This gate voltage for sampling switch SI is generated at least in part from the discharge of capacitor CBOOST, the input signal IN (which is applied through transistor Q6), and the control voltage VCNTL (which is applied through the pass gate circuit and the skew circuit (which generally comprises transistors Q7 and Q8)).
  • this control voltage VCNTL is applied to the source of transistor Q2 (which is generally a PMOS transistor) and the gate of transistor Q7 (which is generally an NMOS transistor) so as to adjust the gate voltage of sample switch SI.
  • the gate voltage of the sampling switch SI can be easily controlled by varying control voltage VCNTL. Additionally, because the sampling switch SI is generally a NMOS switch operating in a linear region, variation of this gate voltage varies the "on" resistance of the sampling switch SI, which adjusts the filter characteristics (and bandwidth) of the filter created by the sampling switch SI, resistor Rl, and sampling capacitor CS AMPLE.
  • a graph depicting bandwidth of T/H circuit 412 versus "on" resistance for the sampling switch SI can be seen in FIG. 7.
  • the bandwidth for T/H circuit 502 varies between about 2.956GHz at for a VCNTL DAC code of zero to about 3.051GHz for a VCNTL DAC code of 1023 ⁇ .
  • the bandwidths for multiple T/H circuits 412 (such as 412-1 to 412-M) with nominal bandwidths of 3GHz can be adjusted to match one another to between about 0.25% and about 0.1%.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
PCT/US2011/048037 2010-08-17 2011-08-17 Track and hold architecture with tunable bandwidth WO2012024371A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013525986A JP5940537B2 (ja) 2010-08-17 2011-08-17 調整可能な帯域幅を備えたトラックアンドホールドアーキテクチャ
CN201180036519.XA CN103026630B (zh) 2010-08-17 2011-08-17 具有可调谐带宽的跟踪与保持架构

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/857,674 2010-08-17
US12/857,674 US8248282B2 (en) 2010-08-17 2010-08-17 Track and hold architecture with tunable bandwidth

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WO2012024371A2 true WO2012024371A2 (en) 2012-02-23
WO2012024371A3 WO2012024371A3 (en) 2012-04-12

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US (2) US8248282B2 (enrdf_load_stackoverflow)
JP (1) JP5940537B2 (enrdf_load_stackoverflow)
CN (1) CN103026630B (enrdf_load_stackoverflow)
WO (1) WO2012024371A2 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013225838A (ja) * 2012-03-23 2013-10-31 Asahi Kasei Electronics Co Ltd ブートストラップスイッチ回路

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8593181B2 (en) * 2011-08-04 2013-11-26 Analog Devices, Inc. Input switches in sampling circuits
EP2634774B1 (en) * 2012-02-28 2019-09-18 Nxp B.V. Track and hold circuit and method
US8525574B1 (en) * 2012-05-15 2013-09-03 Lsi Corporation Bootstrap switch circuit with over-voltage prevention
KR101925355B1 (ko) 2012-09-27 2018-12-06 삼성전자 주식회사 비디오 신호 처리 장치
KR102077684B1 (ko) * 2013-01-09 2020-02-14 삼성전자주식회사 내부 스큐를 보상하는 반도체 장치 및 그것의 동작 방법
US8866652B2 (en) 2013-03-07 2014-10-21 Analog Devices, Inc. Apparatus and method for reducing sampling circuit timing mismatch
GB201305473D0 (en) 2013-03-26 2013-05-08 Ibm Sampling device with buffer circuit for high-speed adcs
GB2516152A (en) * 2013-05-02 2015-01-14 Skyworks Solutions Inc Mixed mode time interleaved digital-to-analog converter for radio-frequency applications
FR3014268A1 (fr) 2013-12-04 2015-06-05 St Microelectronics Sa Procede et dispositif de compensation du desappariement de bandes passantes de plusieurs convertisseurs analogiques/numeriques temporellement entrelaces
KR102094469B1 (ko) 2013-12-10 2020-03-27 삼성전자주식회사 디지털-아날로그 변환 장치 및 방법
KR102188059B1 (ko) 2013-12-23 2020-12-07 삼성전자 주식회사 Ldo 레귤레이터, 전원 관리 시스템 및 ldo 전압 제어 방법
US9287889B2 (en) * 2014-04-17 2016-03-15 The Board Of Regents, The University Of Texas System System and method for dynamic path-mismatch equalization in time-interleaved ADC
EP2953265B1 (en) 2014-06-06 2016-12-14 IMEC vzw Method and circuit for bandwidth mismatch estimation in an a/d converter
EP2977989B1 (en) 2014-07-25 2019-05-08 IMEC vzw Sample-and-hold circuit for an interleaved analog-to-digital converter
US9401727B1 (en) * 2015-08-27 2016-07-26 Telefonaktiebolaget Lm Ericsson (Publ) Shared circuit configurations for bootstrapped sample and hold circuits in a time-interleaved analog to digital converter
US9419639B1 (en) * 2015-09-23 2016-08-16 Qualcomm Incorporated Low distortion sample and hold switch
CN106341132B (zh) * 2016-08-08 2019-05-24 中国工程物理研究院电子工程研究所 时间交织采样adc的误差盲校正方法
TWI849512B (zh) * 2016-09-12 2024-07-21 美商美國亞德諾半導體公司 自舉式切換電路
CN107294534B (zh) * 2017-05-15 2020-10-23 中山大学 用于窄带信号采样的双通道tiadc频响失配实时校正方法
US10644497B2 (en) 2017-05-17 2020-05-05 International Business Machines Corporation Charge pump for distributed voltage passgate with high voltage protection
CN107359877B (zh) * 2017-06-28 2020-07-10 中国工程物理研究院电子工程研究所 超宽带信号的时间交织采样adc全数字盲补偿方法
WO2019061007A1 (en) * 2017-09-26 2019-04-04 Telefonaktiebolaget Lm Ericsson (Publ) METHOD AND APPARATUS FOR CONTROLLING LED
US11322217B2 (en) 2019-08-27 2022-05-03 Texas Instruments Incorporated Track and hold circuits with transformer coupled bootstrap switch
US11601121B2 (en) * 2020-06-26 2023-03-07 Intel Corporation Bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station and a mobile device
WO2022113269A1 (ja) * 2020-11-27 2022-06-02 日本電信電話株式会社 タイムインターリーブ型ａｄｃ
CN114157298B (zh) * 2021-11-12 2022-11-01 华中科技大学 一种ti-adc带宽不匹配的校准方法和系统
JP2023136003A (ja) * 2022-03-16 2023-09-29 キオクシア株式会社 半導体集積回路、受信装置、及び受信方法
WO2023202782A1 (en) * 2022-04-22 2023-10-26 Telefonaktiebolaget Lm Ericsson (Publ) A sample-and-hold (s/h) transfer function with constant group delay
US11799491B1 (en) * 2022-06-08 2023-10-24 Apple Inc. Bootstrap circuit with boosted impedance
US20240146306A1 (en) * 2022-10-31 2024-05-02 Texas Instruments Incorporated Bootstrapped switch

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5170075A (en) * 1991-06-11 1992-12-08 Texas Instruments Incorporated Sample and hold circuitry and methods
US5500612A (en) 1994-05-20 1996-03-19 David Sarnoff Research Center, Inc. Constant impedance sampling switch for an analog to digital converter
US5621409A (en) 1995-02-15 1997-04-15 Analog Devices, Inc. Analog-to-digital conversion with multiple charge balance conversions
US6255865B1 (en) 1999-11-03 2001-07-03 Nanopower Technologies Inc. Track-and-hold circuit
US6243369B1 (en) 1998-05-06 2001-06-05 Terayon Communication Systems, Inc. Apparatus and method for synchronizing an SCDMA upstream or any other type upstream to an MCNS downstream or any other type downstream with a different clock rate than the upstream
JP4117976B2 (ja) * 1999-06-10 2008-07-16 株式会社ルネサステクノロジ サンプルホールド回路
US6323697B1 (en) * 2000-06-06 2001-11-27 Texas Instruments Incorporated Low distortion sample and hold circuit
US6483448B2 (en) * 2000-06-28 2002-11-19 Texas Instruments Incorporated System and method for reducing timing mismatch in sample and hold circuits using an FFT and decimation
IT1318239B1 (it) * 2000-07-25 2003-07-28 St Microelectronics Srl Circuito autoelevatore nei convertitori statici dc/dc.
US6541952B2 (en) * 2001-02-07 2003-04-01 Texas Instruments Incorporated On-line cancellation of sampling mismatch in interleaved sample-and-hold circuits
CN1327609C (zh) 2001-07-03 2007-07-18 西门子公司 控制高频信号放大的方法和相应的发射/接收单元
US6724236B1 (en) * 2002-10-12 2004-04-20 Texas Instruments Incorporated Buffered bootstrapped input switch with cancelled charge sharing for use in high performance sample and hold switched capacitor circuits
SE525470C2 (sv) * 2003-01-15 2005-03-01 Infineon Technologies Ag Metod och anordning för att uppskatta tidsfel i ett system med tidssammanflätade A/D omvandlare
TW595221B (en) 2003-04-17 2004-06-21 Realtek Semiconductor Corp Analog front-end device having filtering function with tunable bandwidth
JP3752237B2 (ja) * 2003-04-25 2006-03-08 アンリツ株式会社 Ａ／ｄ変換装置
DE60308346D1 (de) * 2003-07-03 2006-10-26 St Microelectronics Srl Mit Spannungserhöhung betriebene Abtastschaltung und zugehöriges Ansteuerverfahren
JP2007501483A (ja) * 2003-08-04 2007-01-25 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ トラック／ホールド回路
US7015842B1 (en) * 2005-01-12 2006-03-21 Teranetics, Inc. High-speed sampling architectures
US7075471B1 (en) * 2005-02-11 2006-07-11 Teranetics, Inc. Double-sampled, time-interleaved analog to digital converter
US7206722B2 (en) * 2005-04-01 2007-04-17 Tektronix, Inc. Oscilloscope having an enhancement filter
US7292170B2 (en) * 2005-06-13 2007-11-06 Texas Instruments Incorporated System and method for improved time-interleaved analog-to-digital converter arrays
US7330140B2 (en) 2005-07-01 2008-02-12 Texas Instruments Incorporated Interleaved analog to digital converter with compensation for parameter mismatch among individual converters
JP4774953B2 (ja) * 2005-11-28 2011-09-21 株式会社日立製作所 時間インターリーブａｄ変換器
CN101001085B (zh) * 2006-12-30 2010-05-12 深圳市芯海科技有限公司 信号采样保持电路
CA2689287C (en) 2007-06-21 2016-04-12 Signal Processing Devices Sweden Ab Compensation of mismatch errors in a time-interleaved analog-to-digital converter
US7724042B2 (en) 2007-07-06 2010-05-25 Texas Instruments Incorporated Reducing power consumption in an amplification stage driving a sample and hold circuit while maintaining linearity
EP2201574B1 (en) * 2007-09-12 2016-03-16 Nxp B.V. Time-interleaved track and hold
CN101217278A (zh) * 2008-01-10 2008-07-09 复旦大学 可抑制采样时钟相位偏差影响的时间交错结构模数转换器
EP2211468B1 (en) * 2009-01-26 2011-07-20 Fujitsu Semiconductor Limited Sampling

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013225838A (ja) * 2012-03-23 2013-10-31 Asahi Kasei Electronics Co Ltd ブートストラップスイッチ回路

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US9013339B2 (en) 2015-04-21
US20130015990A1 (en) 2013-01-17
US20120044004A1 (en) 2012-02-23
JP2013535943A (ja) 2013-09-12
JP5940537B2 (ja) 2016-06-29
CN103026630B (zh) 2016-10-12
WO2012024371A3 (en) 2012-04-12
US8248282B2 (en) 2012-08-21
CN103026630A (zh) 2013-04-03

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