WO2023202782A1

WO2023202782A1 - A sample-and-hold (s/h) transfer function with constant group delay

Info

Publication number: WO2023202782A1
Application number: PCT/EP2022/060734
Authority: WO
Inventors: Mattias PALM; Nikola Ivanisevic; Lars SUNDSTRÖM; Daniele Mastantuono
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 2022-04-22
Filing date: 2022-04-22
Publication date: 2023-10-26

Abstract

An analog-to-digital converter (ADC) apparatus comprises multiple ADC branches, each comprising a sample-and-hold (SH) circuit, a bootstrap circuit, and at least one sub-ADC circuit for generating digital outputs. The ADC apparatus further comprises digital circuitry configured to calculate, based on a digital output signal for at least one of the plurality of ADC branches, a metric indicative of flatness of a signal transfer function for the signal path from the input of the ADC apparatus to the digital output signal. A bootstrap control signal to control a voltage of the adjustable bootstrap circuit is then determined from the calculated metric.

Description

A SAMPLE-AND-HOLD (S/H) TRANSFER FUNCTION WITH CONSTANT GROUP DELAY

TECHNICAL FIELD

This disclosure is generally related to analog-to-digital converter (ADC) circuits and is more particularly related to sample-and-hold (S/H) circuitry in such ADC circuits.

BACKGROUND

Technology for wireless communication continuously evolves, with higher data rates that are partly enabled by the use of progressively increasing channel bandwidths. Additionally, there is a trend that base stations (BS) for cellular communications need to handle increasingly large bandwidths (but not only because of increasing channel bandwidths) to support simultaneous communication on multiple carriers or even multiple bands. Trends across all radio standards call for analog-to- digital converters (ADCs) operating at sampling rates of more than several GHz, for use in both base stations and user equipment (UE).

High sample rates in state-of-the-art ADCs are achieved using a time-interleaved architecture, where multiple sub-ADCs, each operating at a speed that is a fraction of the ADC’s overall speed, are arranged so that their sampling and outputs are interleaved in time. These circuits are referred to as time-interleaved ADCs, time-interleaving ADCs, or, simply, interleaved ADCs.

Each of the several sub-ADCs in a time-interleaved ADC is an ADC in its own right. But, because each sub-ADC need only operate at a fraction (e.g., one-half, one-third, one-fourth, etc.) of the time-interleaved ADCs overall sampling rate, the sub-ADC can be designed with high accuracy and linearity. However, the interleaving of the sub-ADCs creates new challenges. In particular, matching between the sub-ADCs in terms of offset, gain, sampling time and transfer function (magnitude and phase or group delay) is critical, to have low interleaving spurs and to achieve high quality in the converted signal, e.g., high spurious free dynamic range (SFDR).

To ease the requirements on the sub-ADCs, one or multiple sample-and-hold (S/H) circuits are typically placed in front of the sub-ADCs, as shown in Figure 1. This example of a time-interleaved ADC architecture features an input buffer, four S/H circuits, four output buffers, and 4 x n sub- ADCs, where there may be n sub-ADCs in each branch. The routing from the input buffer to the S/H circuits is modeled with inductor L1 . Each branch includes a respective S/H sampling capacitor, with a value Csn, and a S/H switch, driven by respective S/H clock signals S/H clkO, S/H clk1 , S/H clk2, S/H clk3, etc. This architecture shifts the requirements of matched sampling time and transfer function from the sub-ADCs themselves to S/H circuits, in this case each including an S/H switch, S/H capacitor, and output buffer, that are easier to match and, to the extent needed, easier to characterize and correct for, e.g., using digital compensation of the time-interleaved ADCs output.

However, the S/H circuits present a bottleneck with respect to analog linearity in time-interleaving ADCs. In particular, the metal-oxide semiconductor (MOS) transistors typically used to implement the S/H sampling switches can distort the sampled signal, because their on-resistance and channel charge vary with gate-to-source voltage, and thus modulate, i.e., vary, with the analog input signal level. To improve the linearity of this part and thus the SFDR of the entire ADC, bootstrap techniques may be implemented.

The ideal bootstrap concept is illustrated in Figure 2, where the basic idea is to “bootstrap” the gate of S/H switch M1 to the source, via a constant direct-current (DC) voltage (Vdc_boost), at the sampling time, so that the gate voltage varies along with the analog input signal level. In other words, through the bootstrap circuit, the analog input signal Vin is added to Vdc_boost, and applied to the transistor gate, to ideally eliminate the input dependent behavior, thus reducing on-resistance (r_on) modulation and improving the linearity.

The state-of-the-art design practice to improve the linearity is thus to target a bootstrap voltage (Vdc boost) that is as high as possible, to reduce the switch on-resistance, r_on, and widen the band for a given sampling capacitance (Csn). A typical challenge and design tradeoff for bootstrap techniques is to keep the Vdc_boost voltage bootstrapped as close as possible to Vdd, which may be the supply voltage for the ADC circuit or other maximum voltage used within the ADC circuit. A schematic of a state-of-the-art implementation of a bootstrap circuit is shown in Figure 3, which is taken from H. Chen, L. He, H. Deng, Y. Yin and F. Lin, "A high-performance bootstrap switch for low voltage switched-capacitor circuits," 2014 IEEE International Symposium on Radio-Frequency Integration Technology, 2014, pp. 1-3. Note that in this circuit, the signal clk_n_d is simply a delayed version of the inverted clock signal clk_n.

SUMMARY

However, challenges remain in achieving high spurious-free dynamic range (SFDR) in very highspeed time-interleaving ADCs. Two main effects can be highlighted as responsible for reducing the bandwidth and degrading the SFDR by elevating both interleaving spurs and nonlinear distortion. The first is mismatch between the transfer functions on the S/H circuits, with respect to magnitude and group delay over frequency. The transfer functions from node x to node y1 , y2, y3 and y4 must be designed to match as much as possible. The second is that routing from the input buffer in a circuit like that shown in Figure 1 to the four S/H circuits introduces resistive and capacitive parasitic effects that affect the group delay. Also, the parasitic effects can be partially inductive (L1 in Figure 1), which will further increase the ripple in magnitude and group delay over frequency and as a result complicates digital post-correction digital compensation of time-interleaving spurs. This effect can easily become a bottleneck when designing ADCs with an even greater number of time- interleaved S/H circuits, when high SFDR performance and high-frequency operation are needed.

Several embodiments of solutions described herein incorporate a method to minimize magnitude and group delay variation across all S/H circuits of a time-interleaving ADC, by sensing an output distortion-related metric (e.g., SFDR) and acting on an adjustable bootstrapped DC voltage. Using this approach, ripple in magnitude and group delay can be significantly reduced by tuning the on- resistance of the S/H switches to an optimal value. This is achieved by adjusting the Vdc_boost voltage applied to the bootstrapped switch, and thus tuning the switch’s r_on resistance to the optimum value for low distortion, e.g., as quantified by a high SFDR.

An example ADC apparatus according to some of the embodiments described in further detail below includes a plurality of ADC branches, each ADC branch being configured to receive a common analog input signal and output at least one respective digital output signal. Each ADC branch in turn comprises a sample-and-hold (S/H) circuit that comprises a sample-and-hold capacitor and a sample-and-hold switch configured to selectively charge the sample-and-hold capacitor from the analog input signal, under the control of a sample-and-hold switch voltage. Each ADC branch further comprises a bootstrap circuit configured to generate the sample-and-hold switch voltage, based on a bootstrap control signal, such that an adjustable boost voltage portion of the sample-and- hold switch voltage applied to the sample-and-hold switch during charging of the sample-and-hold capacitor depends on the bootstrap control signal, and to provide the sample-and-hold switch voltage to the sample-and-hold circuit of that ADC branch. Finally, each ADC branch comprises at least one sub-ADC circuit configured to convert a voltage output by the sample-and-hold circuit to the respective digital output signal. The ADC apparatus further comprises a digital processing circuit configured to calculate a metric, based on a digital output signal for at least one of the plurality of ADC branches, wherein the metric is indicative of flatness of a signal transfer function for the signal path from the input of the analog input signal for the plurality of the ADC branches to the digital output signal, and determine the bootstrap control signal for at least the first one of the ADC branches, based on the calculated metric.

A corresponding example method described herein is for determining settings for an analog-to- digital converter (ADC) apparatus comprising a plurality of ADC branches, where each ADC branch is configured to receive an analog input signal and output at least one respective digital output signal. Each ADC branch comprises a sample-and-hold circuit that comprises a sample-and-hold capacitor and a sample-and-hold switch configured to selectively charge the sample-and-hold capacitor from the analog input signal, under the control of a sample-and-hold switch voltage, and each ADC branch further comprises a bootstrap circuit configured to generate the sample-and-hold switch voltage, based on a bootstrap control signal, such that an adjustable boost voltage portion of the sample-and-hold switch voltage applied to the sample-and-hold switch during charging of the sample-and-hold capacitor depends on the bootstrap control signal, and apply the sample-and-hold switch voltage to the sample-and-hold switch. Each ADC branch still further comprises at least one sub-ADC circuit configured to convert a voltage output by the sample-and-hold circuit to the respective digital output signal. The example method comprises the steps of calculating a metric based on a digital output signal for at least one of the plurality of ADC branches, where the metric is indicative of flatness of a signal transfer function for the signal path from the input of the analog input signal for the plurality of the ADC branches to the digital output signal, and determining the bootstrap control signal for at least the first one of the ADC branches, based on the calculated metric. Variations of these and other ADC apparatuses, circuits, and methods are detailed below.

Advantages provided by several of the disclosed embodiments may include that parasitic effects in a time-interleaved ADC circuit, including inductive parasitic effects, may be effectively compensated, keeping the group delay through the sample-and-hold circuits relatively flat, or constant. Sample-and- hold bandwidth mismatch can be compensated independently of other compensation, thus simplifying digital correction for mismatch between S/H circuit transfer functions. Matched transfer functions are crucial for having low levels of time-interleaving spurs. This may result in lower complexity overall for digital post-correction of distortion. Embodiments of the techniques described herein may further be used to relax the bootstrap circuit design at high frequencies, in some embodiments, since the attenuation of the bootstrapped voltage due to parasitic capacitances need not be minimized by special techniques, given that the optimum value may be lower than the Vdd supply for the ADC circuit.

BRIEF DESCRIPTION OF THE FIGURES

Figure 1 illustrates an example of a time-interleaved analog-to-digital converter (ADC) circuit with an input buffer, four sample-and-hold (S/H) circuits, four output buffers, and 4 x n sub-ADCs.

Figure 2 illustrates an ideal bootstrap circuit.

Figure 3 shows an example implementation of a bootstrap circuit.

Figures 4A, 4B, and 4C are example bootstrap circuits with variable DC bootstrap voltages, according to several embodiments of the presently disclosed invention.

Figure 5 illustrates an example circuit with a global, common controllable supply voltage, according to some embodiments.

Figure 6 is a process flow diagram illustrating an example method, according to some embodiments of the presently disclosed invention.

Figure 7 illustrates another example method, according to some embodiments of the presently disclosed invention.

Figure 8 illustrates an example processing circuit for measurement and optimization, according to some embodiments.

Figure 9 is a process flow diagram illustrating another example method, according to some embodiments.

DETAILED DESCRIPTION

In the following, some embodiments of the present invention will be described in detail. It is to be understood that the following description is given only for the purpose of illustration and is not to be taken in a limiting sense. The scope of the invention is not intended to be limited by the embodiments described hereinafter with reference to the accompanying drawings, but is intended to be limited only by the appended claims and equivalents thereof.

It is also to be understood that in the following description of the embodiments, unless the context or description indicates otherwise, any direct connection or coupling between functional blocks, devices, components, circuit elements or other physical or functional units shown in the drawings or described herein could also be implemented by an indirect connection or coupling, i.e., a connection or coupling comprising one or more intervening elements. Furthermore, it should be appreciated that functional blocks or units shown in the drawings may be implemented as separate circuits, in some embodiments, but may also be fully or partially implemented in a common circuit in other embodiments. On the other hand, a single functional block may also be implemented using a plurality of separate circuits.

It should be noted that the drawings are provided to give an illustration of some aspects of embodiments of the present invention and are therefore to be regarded as schematic only. The features of the various embodiments described herein may be combined with each other unless specifically noted otherwise. On the other hand, describing an embodiment with a plurality of features is not to be construed as indicating that all those features are necessary for practicing the present invention, as other embodiments may comprise less features and/or alternative features.

Many effects can determine the degradation of spurious-free dynamic range (SFDR) in a time- interleaved analog-to-digital converter (TI-ADC). First is the analog non-linearity that may, e.g. manifest itself as harmonic and intermodulation distortion. Second is how well the bandwidth is matched between the different sample-and-hold (S/H) branches, whether they are implemented one per sub-ADC, or fewer, preceding the sub-ADCs, as shown in Figure 1.

A wider bandwidth behavior is as important as the analog non-linearity for a high SFDR. A critical block for both these performances is the S/H bootstrap design.

With existing solutions, design effort is put into improving, as much as possible, the linearity of the S/H switch Mi through a constant gate-to-supply voltage Vgs, e.g., as shown in the state-of-the-art bootstrap circuit implementation shown in Figure 3, and by increasing as much as possible the S/H bandwidth by reducing the on-resistance r_on of the sampling switch M1 for a given sample-and-hold capacitor capacitance Csn. The higher the bootstrapped voltage at node Vg, the lower the r_on and, when all other factors are equal, the higher the S/H circuit bandwidth.

Looking more in detail at a TI-ADC example like that shown in Figure 1 , which uses four S/H branches, two main effects can be highlighted as responsible for reducing the bandwidth and degrading the SFDR by elevating interleaving spurs:

• the mismatch between the transfer functions among the several S/H branches in magnitude and group delay over frequency. The transfer functions from node x to node y1 , y2, y3 and y4 must be designed to match as good as possible, to reduce the linear distortion caused by this mismatch.

• routing from input buffer to the four S/H circuits introduces resistive and capacitive parasitic that affects the group delay. Also, the parasitic effects can be partially inductive (L1 in Figure 1), which will further increase the ripple in magnitude and group delay over frequency and as a result complicates the digital correction for time-interleaving spurs. This effect can easily become a bottleneck when going towards an even greater number of time-interleaved S/H circuits, high SFDR performance and high frequencies.

Transfer functions with a flat magnitude and constant group delay also have other advantages. For example, in communication systems based on Orthogonal Frequency-Division Multiplexing (OFDM), this variation in the channel transfer function is characterized and compensated for in the digital baseband using channel equalization, by adjusting the magnitude and phase per subcarrier in the frequency domain, based on an estimate of the channel (whether originating from the propagation or filtering in the receiver signal path). With this approach, a high error vector magnitude (EVM) or equivalent signal-to-noise ratio (SNR) metric can be maintained, allowing for high-order modulation.

However, future communications network standards for wireless networks operating around 100 GHz and higher may enable channel bandwidths of more than 10 GHz range and abandon frequency-domain modulation (e.g., OFDM) in favor of time-domain modulation (single-carrier). This may lead to less capable channel equalization, if any is used at all (due to power consumption constraints), and thus generally calls for flatter signal transfer functions in all circuit blocks, including ADCs, to minimize the EVM contribution.

Finally, another driver of TI-ADC performance is the interaction between contributions to the overall transfer function of the ADC or each individual branch and the various nonlinear distortion contributions from, e.g., buffers and S/H circuits. Mathematically the transfer function and nonlinear distortion contributions become intertwined, further complicating the digital post-correction if nonlinear distortion needs to be corrected also.

Solutions to these problems are described herein. These solutions include methods to minimize magnitude and group delay variation across all S/H circuits of a Tl ADC by sensing an output linearity metric (e.g., SFDR) and acting on a bootstrapped DC voltage as defined in Figure 2.

The ripple in magnitude and group delay can be significantly reduced by tuning the on-resistance of the S/H switches to an optimal value. This is achieved by adjusting the Vdc_boost voltage of the bootstrapped switch and thus tuning its r_on resistance to the optimum value for low distortion, e.g., as quantified by a high SFDR.

The solutions described herein balance linearity and bandwidth of S/H bootstrap circuit to reduce time-interleaving spurs in a TI-ADC. The bandwidth of a S/H bootstrap circuit can be viewed in terms of group delay. The flatter the group delay across frequency, the wider the S/H bandwidth. Using a control loop guided by an ADC output linearity metric (e.g., SFDR) and acting on the DC voltage bootstrapped (Vdc_boost), it is possible to find an optimum value of the bootstrapped voltage, lower than Vdd, that improves the flatness of the group delay and still improves distortion, compared to a non-bootstrapped S/H circuit.

In Figure 2, an ideal implementation of a bootstrap circuit is shown. The bootstrapped voltage at the gate V_g is V_g = Vdc_boost + l/,_n, where Vin is the input signal. Usually in the state-of-the-art implementations and to maximize the linearity, Vdc_boost =Vdd. In the solutions described herein, however, Vdc_boost < Vdd, and is adjustable/variable.

More specifically, the bootstrap Vg voltage in S/H circuits is controllable, according to the techniques described herein, to adjust the on-resistance of the bootstrapped switch in order to reduce ripple in S/H transfer function.

Figures 4A, 4B, and 4C illustrate several variants of a bootstrap circuit according to this approach. In each case, the S/H circuit contains a sample-and-hold switch (Mi), a sample-and-hold capacitor Csh, and a bootstrapping circuitry to drive Mi. When Mi is in its closed state (conducting), its gate voltage, V_g, is ideally the sum of the input signal, _n, and a direct-current (DC) voltage (Vdc_boost) ,

V_g ⁼ Vin + Vdc boost , where the bootstrap voltage Vdc_boost is supplied to the gate of the sample-and-hold switch M1 at the appropriate time from the bootstrap capacitor Cb.

Thus, the gate-source voltage of sample-and-hold switch Mi and the corresponding on-resistance is controllable through Vdc_boost. In the illustrated examples, this may be done by charging the bootstrap capacitor Cb to the controllable boost voltage Vdc_boost, using switch M2, from a variable voltage supply, as in Figure 4A. Alternatively, the bootstrap capacitor Cb can be charged to a variable voltage Vdc_boost by charging the capacitor through a variable resistor Rdc_boost, which provides a controllable voltage drop from an ADC power supply voltage Vdd. This is shown in Figure 4B. Another version of this is shown in Figure 4C, where the variable resistance between Vdd and the bootstrap capacitor Cb is implemented by a parallel combination of transistors that can be independently turned on or off with control signals bO, b1 , and b2. The on-resistances of those transistors that are turned on determine the voltage drop from Vdd to the bootstrap capacitor Cb and thus determine the boost voltage Vdc_boost.

In each case, then, the voltage level of the boost voltage Vdc_boost is determined by a bootstrap control signal Vbctrl, which may, in various implementations, be an analog control signal, controlling an adjustable voltage supply or adjustable resistance as shown in Figures 4A and 4B, for example, or a digital control signal, such as the signal comprising bO, b1 , and b2 in Figure 4C. Figures 4A-4C each illustrate an example implementation of the bootstrap circuit for a single branch of a TI-ADC. It will be appreciated that the same implementation may be replicated for each branch, such that each branch has an independently controlled source of the the boost voltage Vdc_boost, which means that the on-resistance of the S/H switch M1 can be independently optimized for each branch.

An alternative to that approach is shown in Figure 5, which illustrates an example implementation where a single source of the the boost voltage Vdc_boost is shared among, i.e., common to, the several branches of the TI-ADC. This simplifies the implementation, but means that optimization of the boost voltage Vdc_boost acts simultaneously on all of the branches at once.

Simulation of circuits having an architecture like that shown in Figure 5 have shown that optimizing the common boost voltage Vdc_boost in such a circuit can dramatically reduce the ripple, across frequency in magnitude and group delay of the transfer-function of the S/H circuits. In a simulated cirucit having a nominal voltage supply of 750 mV, for example, the S/H circuit transfer function had 1 ,5dB and 50 ps peak-to-peak ripples in the magnitude and group delay responses, respectively. When the boost voltage Vdc_boost was reduced, however, a much flatter transfer function was achieved, with a group delay ripple of less than 10 ps peak-to-peak.

With respect to the signal power and linearity of the circuit, across frequency, the signal power varies less over frequency at the optimized value for the boost voltage Vdc_boost, as expected. This is at the cost of higher nonlinear distortion, however, which is dominated by the third-order harmonic distortion. The flatter transfer function, however, eases any digital post-correction for both the harmonic distortion and time-interleaving spurs caused by mismatched S/H transfer functions (mismatch in magnitude and group delay from node x to y1 ...y4). The SFDR of an uncorrected TI- ADC is typically dominated by time-interleaving spurs, rather than harmonic distortion. It is therefore preferable to have a flatter transfer function, at the expense of somewhat increased harmonic distortion, and utilize digital post correction for the remaining error contributions to reach the performance needed.

Determining the appropriate value for the boost voltage Vdc_boost can be done using straightforward optimization routines, e.g., based on applying a test signal to the ADC input. The test signal may be a single tone varied across frequency, a multitone, a modulated signal or any other signal that facilitates measurements to yield a metric that guides an optimization algorithm in iteratively adjusting S/H settings. The choice of optimization algorithm is not important in this context, the area of optimization algorithms is well developed for various scenarios. However, the measurements made may be noisy to some extent that suggest that optimization algorithms with some resilience to measurement noise is preferred. Of course, at the other end of the scale, a brute-force sweep (exhaustive search) of all possible S/H settings may be carried out and then the combination of S/H settings that yields the best result is kept for subsequent operation of the ADC. Note that depending on the architecture of the TI-ADC, the optimization may be carried out separately for each of the branches, for implementations where there is a separately controllable boost voltage Vdc_boost for each branch, or a single time, for a single boost voltage Vdc_boost common to all of the branches. In the former case, the metric to be optimized may be measured separately for each branch. In the latter case, the metric may be measured for a single branch, deemed to be representative of all of the branches, or may be a metric that combines measurements from several or all of the branches.

The overall transfer function of the ADC or the individual transfer functions for respective S/H or branch of the ADC will affect the signal in different ways as it is sampled and converted by the ADC. Any of several metrics may be chosen to perform the optimization, provided that the metric is indicative of flatness of a signal transfer function for the signal path from the input of the analog input signal (Vin) for the ADC branches to the digital output signal produced by one or several of the subADCs. This metric may be a scalar quantity or a vector. It may, for example, represent one or several of:

• Spurious-free dynamic range (SFDR)

• Levels of time-interleaving spurs

• Signal-to-noise and distortion ratio (SNDR)

• Least-square error between transfer function and a reference (targeted) transfer function

Associated with the metric there may be an associated range defining a range of values for when the scalar quantity in the metric is within a specification and when not, for use by the optimization algorithm in determining when the boost voltage Vdc_boost has been sufficiently optimized.

Alternatively, or in addition to the above, there may be an associated reference value for the metric defining an optimal or ideal, possibly unreachable, value for the scalar quantity in the metric.

In various implementations, the optimization algorithm may operate continuously to push the metric towards a reference value, optionally under the constraint that the metric should also be within range of specification. Alternatively, the algorithm may be designed to terminate when the metric is within range of specification or when there is no further improvement of the metric (or metrics) over two or some other predetermined number of iterations.

An example method applied to find proper settings of the S/H circuits, whether common for all S/H circuits or individual, is shown in Figure 6. A signal is input to the ADC, as shown at block 610. At least one metric indicative of the flatness of the transfer function of at least one S/H signal path is measured, as shown at block 620. As shown at block 630, the metric is evaluated to determine whether the optimization goal has been met. If so, then the optimization may end. Otherwise, at least one S/H setting is adjusted, as shown at block 640, and the measurement and evaluation is repeated.

The at least one S/H setting that is adjusted includes the value of the boost voltage Vdc_boost for at least one branch of the TI-ADC. More directly, the optimization algorithm may adjust a bootstrap control signal, e.g., Vbctrl, that controls the supply of the boost voltage Vdc_boost. As was seen in Figures 4A-4C, this may be an analog or digital control signal that controls a variable voltage supply or variable resistance, or a digital control signal that selectively turns on various combinations of switching transistors, to generate a variable resistance that in turn adjusts the boost voltage Vdc_boost value.

A more specific example of measurement and optimization is shown in Figure 7. The S/H settings may, for example, be the voltage or resistance of the S/H supply, individual or the same for all S/H circuits. One or several test tones are generated and connected to the ADC input, as shown at block 710. Fast Fourier transform (FFT) is performed on the ADC output data and the magnitude and group delay of the tones are extracted, as shown at blocks 720 and 730. Optionally, this is repeated for a set of different input tone frequencies to yield a more complete sampling of the magnitude and group delay versus frequency. As shown at block 740, at least one S/H setting is updated based on the magnitude and group delay characteristics, and the procedure is repeated, preferably as part of an optimization algorithm. Again, the optimization is based on at least one metric indicative of the flatness of the transfer function of the S/H signal path for at least one branch of the ADC circuit. In this case the optimization algorithm may, for example, optimize the S/H setting(s) based on at least one of:

• Group delay variability/ripple over a specified set of frequencies

• Magnitude variability/ripple over a specified set of frequencies

• Least-square error between measured group delay and a reference group delay characteristic.

• Least-square error between measured magnitude and a reference magnitude characteristic.

Figure 8 illustrates an example processing circuit 800, for performing the measurement and optimization described above. Processing circuit 800 includes a processor 810 and a memory 820 operatively coupled to the processor 810. Memory 820 may store program instructions for execution by processor 810, with those program instructions being configured to cause the processor 810 to carry out an optimization process like those described above.

The input to processing circuit 800 may comprise the digital signal outputs from a single sub-ADC of the TI-ADC, or from a sub-ADC on each of several branches of the TI-ADC, or from all of the subADCs, in various embodiments. Processor 810 may calculate one or more metric values for any one or several of the metrics described above, based on the digital signal output(s) provided from the sub- ADC(s). This may comprise, for example, performing FFTs on the digital signal output(s) provided from the sub-ADCs, as was discussed in connection with Figure 7, in some embodiments. Based on an evaluation of the calculated metric(s), e.g., as shown at block 630 in Figure 6, the processor 810 may choose to adjust the S/H setting, e.g., as shown at block 640 in Figure 6. This may comprise adjusting the value or values of a bootstrap control signal Vbctrl, as shown in Figure 8. In some embodiments, the bootstrap control signal may be an analog signal, in which case processing circuit might comprise a digital-to-analog converter 830, as shown in the figure. It will be appreciated, of course, that several implementations of processing circuit 800 are possible. Processing circuit 800 may comprise a conventional microprocessor architecture, for example, where memory 820 comprises a combination of random access memory (RAM) and Flash memory, for example. In other embodiments, processing circuit 800 may comprise custom digital logic to carry out some or all of the functions described above. This digital logic may be in the form of an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like, in various embodiments.

An ADC apparatus may then comprise a measurement and evaluation circuit, e.g., like that shown in Figure 8, combined with components of a TI-ADC, where each branch of the TI-ADC is configured to receive a common analog input signal (Vin) and output at least one respective digital output signal (yn) from a respective sub-ADC. (Each branch might have a single sub-ADC, or might have multiple subADCs, as shown in Figure 1.) Each ADC branch includes a sample-and-hold circuit that comprises a sample-and-hold capacitor Csn and a sample-and-hold switch Mi configured to selectively charge the sample-and-hold capacitor Csn from the analog input signal (Vin), under the control of a sample-and- hold switch voltage (V_g).

As was seen in the previous discussion of several examples of the ADC circuit, each branch also comprises a bootstrap circuit configured to generate an adjustable sample-and-hold switch voltage (V_g), such that an adjustable boost voltage portion (Vdc_boost) of the sample-and-hold switch voltage (V_g) applied to the sample-and-hold switch Mi during charging of the sample-and-hold capacitor (Csn) depends on a bootstrap control signal (Vbctrl), and provide the sample-and-hold switch voltage (V_g) to the sample-and-hold circuit. Each branch also includes at least one sub-ADC circuit configured to convert a voltage output by the sample-and-hold circuit to the respective digital output signal (yn).

The ADC apparatus in this example also comprises a digital processing circuit, such as the digital processing circuit 800 shown in Figure 8, where this processing circuit is configured to calculate a metric, based on a digital output signal for at least one of the plurality of ADC branches, where the metric is indicative of flatness of a signal transfer function for the signal path from the input of the analog input signal (Vin) for the plurality of the ADC branches to the digital output signal. The digital processing circuit is further configured to determine the bootstrap control signal (Vbctrl) for at least the first one of the ADC branches, based on the calculated metric, e.g., using an optimization algorithm as discussed above.

As was discussed above, the metric may, in various embodiments, comprise a measure of one or more of any one or more of the following: a transfer function group delay variability over a specified set or range of frequencies; a transfer function magnitude variability over a specified set or range of frequencies; a least-square error between measured transfer function group delay and a reference group delay characteristic, over a specified set or range of frequencies; and a least-square error between measured transfer function magnitude and a reference magnitude characteristic, over a specified set or range of frequencies. In some embodiments, the metric may comprise an estimate of SFDR as measured after digital compensation of the least one digital output signal for circuit nonlinearity.

In some embodiments, the digital processing circuit is configured to determine a common bootstrap control signal, based on the metric, for application to a common variable bootstrap voltage supply circuit configured to generate a common adjustable boost voltage for use by all of the ADC branches. In some of these embodiments, the digital processing circuit determines the common bootstrap control signal based on the metric for only a single one of the plurality of ADC branches. In others, a combined, or composite, metric based on several or all of the branches may be used, and the common bootstrap control signal is determined based on the composite metric.

In other embodiments, the digital processing circuit is configured to determine a separate bootstrap control signal for application to a variable bootstrap voltage supply circuit for each of the ADC branches, based on at least one metric for each respective ADC branch.

In some embodiments, the digital processing circuit is configured to perform an iterative optimization algorithm, by iteratively adjusting the bootstrap control signal for all or each of one or more of the ADC branches, calculating and evaluating the metric for each iteration, and determining a new bootstrap control signal for each or all of the ADC branches, based on the calculating and evaluating. In some embodiments, the digital processing circuit is configured to perform the iterative optimization algorithm for a first one of the plurality of ADC branches, thereby obtaining a reference metric, and is configured to then tune the bootstrap control signal for each of at least one other ADC branch so that a measured metric for that ADC branch matches the reference metric. Variations of these approaches are possible.

As seen in several of the figures discussed above, the bootstrap circuit itself comprises a bootstrap capacitor coupled between a gate and source of the sample-and-hold switch Mi, and switching circuitry configured to (a) selectively charge the bootstrap capacitor to the voltage of said adjustable boost voltage portion Vdc_boost and (b) selectively connect the voltage of the bootstrap capacitor between the gate and source of the sample-and-hold switch Mi. It should be appreciated, then, that the S/H setting that is ultimately adjusted for these embodiments, according to the techniques described herein, is the boost voltage Vdc_boost. As was discussed above, this indirectly adjusts the on- resistance of the S/H switch Mi.

The description of various ADC apparatuses above contemplates that the TI-ADC components and the measurement and optimization circuit are combined, and thus form a unit. With an apparatus like this, the ADC performance can be optimized in the field, to reflect actual operating conditions, and can be repeated periodically or in response to changing events.

As an alternative, the measurement and optimization circuit might be separate from the ADC itself, and used to optimize the ADC circuit performance at the time of manufacture, or at the point of installation. In this case, then, embodiments of the presently disclosed invention might comprise either the TI-ADC with the bootstrap circuits described herein alone, or the measurement and optimization circuit alone.

In either case, the invention described herein includes processes that correspond to the apparatuses described above. These processes include an example method for determining settings for an ADC converter apparatus according to any of the apparatuses described herein. This example method is shown in the process flow diagram of Figure 9, and comprises the step of calculating a metric based on a digital output signal for at least one of the plurality of ADC branches of the ADC apparatus. This is shown at block 910. As discussed above, this metric is indicative of flatness of a signal transfer function for the signal path from the input of the analog input signal (Vin) for the plurality of the ADC branches to the digital output signal from at least one sub-ADC of a branch. The method further comprises, as shown at block 920, determining the bootstrap control signal (Vbctrl) for at least the first one of the ADC branches, based on the calculated metric.

Once again, the metric may comprise a measure of one or more of any one or more of the following: a transfer function group delay variability over a specified set or range of frequencies; a transfer function magnitude variability over a specified set or range of frequencies; a least-square error between measured transfer function group delay and a reference group delay characteristic, over a specified set or range of frequencies; and a least-square error between measured transfer function magnitude and a reference magnitude characteristic, over a specified set or range of frequencies. The metric might instead comprise an estimate of SFDR, as measured after digital compensation of the least one digital output signal for circuit nonlinearity.

In some embodiments, this method comprises determining a common bootstrap control signal, based on the metric, for application to a common variable bootstrap voltage supply circuit configured to generate a common adjustable boost voltage for use by all of the ADC branches. This common bootstrap control signal might be based on the metric for only a single one of the plurality of ADC branches, in some embodiments, or might instead be a composite metric determined from a combination of the digital signal outputs from a plurality of the ADC branches, in others.

In other embodiments, the method may comprise determining a separate bootstrap control signal for application to a variable bootstrap voltage supply circuit for each of the ADC branches, based on at least one metric for each respective ADC branch.

In various embodiments, the method comprises performing an iterative optimization algorithm, by iteratively adjusting the bootstrap control signal for all or each of one or more of the ADC branches, calculating and evaluating the metric for each iteration, and determining a new bootstrap control signal for each or all of the ADC branches, based on this calculating and evaluating. In some embodiments, the digital processing circuit is configured to perform the iterative optimization algorithm for a first one of the plurality of ADC branches, thereby obtaining a reference metric, and to then tune the bootstrap control signal for each of at least one other ADC branch to match the reference metric. Although various implementations are described above in language specific to structural features and/or methodological acts, it is to be understood that the implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing example devices and techniques. The above embodiments serve only as some examples how to implement the present invention and are therefore not to be construed as limiting the scope thereof.

Claims

1 . An analog-to-digital converter (ADC) apparatus, comprising: a plurality of ADC branches, each ADC branch being configured to receive a common analog input signal (Vin) and output at least one respective digital output signal (yn), each ADC branch comprising a sample-and-hold circuit that comprises a sample-and-hold capacitor (Csn) and a sample-and-hold switch (M1) configured to selectively charge the sample- and-hold capacitor (Csn) from the analog input signal (Vin), under the control of a sample-and-hold switch voltage (Vg), a bootstrap circuit configured to generate an adjustable sample-and-hold switch voltage (Vg), such that an adjustable boost voltage portion (Vdc_boost) of the sample-and-hold switch voltage (Vg) applied to the sample-and-hold switch (M1) during charging of the sample-and-hold capacitor (Csn) depends on a bootstrap control signal (Vbctrl), and provide the sample-and-hold switch voltage (Vg) to the sample-and-hold circuit, and at least one sub-ADC circuit configured to convert a voltage output by the sample- and-hold circuit to the respective digital output signal (yn) ; and a digital processing circuit configured to calculate a metric, based on a digital output signal for at least one of the plurality of ADC branches, wherein the metric is indicative of flatness of a signal transfer function for the signal path from the input of the analog input signal (Vin) for the plurality of the ADC branches to the digital output signal, and determine the bootstrap control signal (Vbctrl) for at least the first one of the ADC branches, based on the calculated metric.

2. The ADC apparatus of claim 1 , wherein the metric comprises a measure of one or more of any one or more of the following: a transfer function group delay variability over a specified set or range of frequencies; a transfer function magnitude variability over a specified set or range of frequencies; a least-square error between measured transfer function group delay and a reference group delay characteristic, over a specified set or range of frequencies; and a least-square error between measured transfer function magnitude and a reference magnitude characteristic, over a specified set or range of frequencies.

3. The ADC apparatus of claim 1 , wherein the metric comprises an estimate of spurious-free dynamic range, SFDR, as measured after digital compensation of the least one digital output signal for distortion.

4. The ADC apparatus of any one of claims 1-3, wherein the digital processing circuit is configured to determine a common bootstrap control signal, based on the metric, for application to a common variable bootstrap voltage supply circuit configured to generate a common adjustable boost voltage for use by all of the ADC branches .

5. The ADC apparatus of claim 4, wherein the digital processing circuit is configured to determine the common bootstrap control signal based on the metric for only a single one of the plurality of ADC branches.

6. The ADC apparatus of claim 4, wherein the metric is a composite metric determined from a combination of the digital signal outputs from a plurality of the ADC branches, and the digital processing circuit is configured to determine the common bootstrap control signal based on the composite metric.

7. The ADC apparatus of any one of claims 1-3, wherein the digital processing circuit is configured to determine a separate bootstrap control signal for application to a variable bootstrap voltage supply circuit for each of the ADC branches, based on at least one metric for each respective ADC branch.

8. The ADC apparatus of any of claims 1-7, wherein the digital processing circuit is configured to perform an iterative optimization algorithm, by iteratively adjusting the bootstrap control signal for all or each of one or more of the ADC branches, calculating and evaluating the metric for each iteration, and determining a new bootstrap control signal for each or all of the ADC branches, based on said calculating and evaluating.

9. The ADC apparatus of claim 8, wherein the digital processing circuit is configured to perform the iterative optimization algorithm for a first one of the plurality of ADC branches, thereby obtaining a reference metric, and to tune the bootstrap control signal for each of at least one other ADC branch to match the reference metric.

10. The ADC apparatus of any of claims 1-9, wherein the bootstrap circuit comprises: a bootstrap capacitor coupled between a gate and source of the sample-and-hold switch (M1); switching circuitry configured to (a) selectively charge the bootstrap capacitor to the voltage of said adjustable boost voltage portion (Vdc_boost) and (b) selectively connect the voltage of the bootstrap capacitor between the gate and source of the sample-and- hold switch (M1).

11 . A method for determining settings for an analog-to-digital converter (ADC) apparatus comprising a plurality of ADC branches, wherein each ADC branch is configured to receive an analog input signal (Vin) and output at least one respective digital output signal (yn) and each ADC branch comprises a sample-and-hold circuit that comprises a sample-and-hold capacitor (Csn) and a sample-and-hold switch (M1) configured to selectively charge the sample-and-hold capacitor (Csn) from the analog input signal (Vin), under the control of a sample-and-hold switch voltage (Vg), each ADC branch further comprising a bootstrap circuit configured to generate the sample-and-hold switch voltage (Vg), such that an adjustable boost voltage portion (Vdc_boost) of the sample-and-hold switch voltage (Vg) applied to the sample-and-hold switch (M1) during charging of the sample-and-hold capacitor (Csn) depends on a bootstrap control signal (Vbctrl), and apply the sample-and-hold switch voltage (Vg) to the sample-and-hold switch (M1), each ADC branch still further comprising at least one sub-ADC circuit configured to convert a voltage output by the sample-and-hold circuit to the respective digital output signal (yn) , the method comprising: calculating a metric based on a digital output signal for at least one of the plurality of ADC branches, wherein the metric is indicative of flatness of a signal transfer function for the signal path from the input of the analog input signal (Vin) for the plurality of the ADC branches to the digital output signal; and determining the bootstrap control signal (Vbctrl) for at least the first one of the ADC branches, based on the calculated metric.

12. The method of claim 11 , wherein the metric comprises a measure of one or more of any one or more of the following: a transfer function group delay variability over a specified set or range of frequencies; a transfer function magnitude variability over a specified set or range of frequencies; a least-square error between measured transfer function group delay and a reference group delay characteristic, over a specified set or range of frequencies; and a least-square error between measured transfer function magnitude and a reference magnitude characteristic, over a specified set or range of frequencies.

13. The method of claim 11 , wherein the metric comprises an estimate of spurious-free dynamic range, SFDR, as measured after digital compensation of the least one digital output signal for distortion.

14. The method of any one of claims 11-13, wherein the method comprises determining a common bootstrap control signal, based on the metric, for application to a common variable bootstrap voltage supply circuit configured to generate a common adjustable boost voltage for use by all of the ADC branches.

15. The method of claim 14, wherein the method comprises determining the common bootstrap control signal based on the metric for only a single one of the plurality of ADC branches.

16. The ADC apparatus of claim 14, wherein the metric is a composite metric determined from a combination of the digital signal outputs from a plurality of the ADC branches, and wherein the method comprises determining the common bootstrap control signal based on the composite metric.

17. The method of any one of claims 11-13, wherein the method comprises determining a separate bootstrap control signal for application to a variable bootstrap voltage supply circuit for each of the ADC branches, based on at least one metric for each respective ADC branch.

18. The method of any of claims 11-17, wherein the method comprises performing an iterative optimization algorithm, by iteratively adjusting the bootstrap control signal for all or each of one or more of the ADC branches, calculating and evaluating the metric for each iteration, and determining a new bootstrap control signal for each or all of the ADC branches, based on said calculating and evaluating.

19. The method of claim 18, when depending from any of claims 11-13 and 17, wherein the digital processing circuit is configured to perform the iterative optimization algorithm for a first one of the plurality of ADC branches, thereby obtaining a reference metric, and to tune the bootstrap control signal for each of at least one other ADC branch to match the reference metric.