WO2012022135A1 - 超薄体晶体管及其制作方法 - Google Patents

超薄体晶体管及其制作方法 Download PDF

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Publication number
WO2012022135A1
WO2012022135A1 PCT/CN2011/070686 CN2011070686W WO2012022135A1 WO 2012022135 A1 WO2012022135 A1 WO 2012022135A1 CN 2011070686 W CN2011070686 W CN 2011070686W WO 2012022135 A1 WO2012022135 A1 WO 2012022135A1
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region
gate
layer
buried
sacrificial
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PCT/CN2011/070686
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English (en)
French (fr)
Inventor
梁擎擎
钟汇才
朱慧珑
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中国科学院微电子研究所
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Priority to US13/132,535 priority Critical patent/US20120043624A1/en
Publication of WO2012022135A1 publication Critical patent/WO2012022135A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Definitions

  • the present invention relates to the field of semiconductor technology, and more particularly to an ultrathin body transistor and a method of fabricating the same.
  • the minimum feature size that is, the "geometric line width" of known devices, has become smaller and smaller with the innovation of process technology.
  • the minimum linewidth of MOS transistors is less than 45 nanometers.
  • MOS transistor having a raised source and drain region is disclosed in U.S. Patent Application Serial No. 7,756, 944. Referring to Figure 1, the MOS transistor having a raised source and drain region is shown. The raised source and drain regions 105 are respectively located on the semiconductor substrate 101 on both sides of the gate 103.
  • the MOS transistor When fabricating the MOS transistor, it is necessary to etch a well region on both sides of the sacrificial gate after forming a sacrificial gate to form a source/drain region trench; and then filling the source/drain region trench with ⁇ The silicon material is formed until the raised source and drain regions are formed.
  • the raised source and drain regions introduce a certain stress in the channel region of the MOS transistor, thereby increasing the carrier mobility in the channel region, and the current driving capability of the MOS transistor is significantly improved.
  • the patent also employs a gate replacement process, which refers to removing and resuming the sacrificial gate after the bump source and drain regions are completed.
  • a process for filling a conduction band material to form a gate. The re-formed gate further improves the stress characteristics of the channel region and increases the mobility of carriers in the channel region.
  • the body region of the MOS transistor is thick, and the thicker body region is disadvantageous for suppressing the short channel effect of the device, which limits the further reduction in device size and further improvement in performance.
  • the problem to be solved by the present invention is to provide an ultra-thin body transistor having a thin body region, which can reduce the length of the lateral depletion region generated when the drain is reverse biased, thereby effectively The short channel effect of the device is suppressed.
  • the present invention provides an ultra-thin body transistor, comprising: a semiconductor substrate, a gate structure on the semiconductor substrate, and source and drain regions in a semiconductor substrate on both sides of the gate structure,
  • the gate structure includes a gate dielectric layer, a gate embedded in the gate dielectric layer, and sidewalls on both sides of the gate;
  • the ultra-thin transistor further includes: sequentially located under the gate structure a body region and a buried layer insulating region in the well region, wherein the body region and the buried layer insulating region are respectively connected to the source region and the drain region, and the buried layer insulating region below the body region is the body region and the well region The rest of the area is isolated.
  • the present invention also provides a method for fabricating an ultrathin body transistor, comprising: a region epitaxial layer;
  • Forming a trench isolation region in the semiconductor substrate forming a well region in a semiconductor substrate in the trench isolation region, the trench isolation region and the well region having a depth at least exceeding a depth of the buried layer sacrificial layer; Forming a sacrificial gate dielectric layer, a sacrificial gate and a sacrificial gate protection cap layer on the well region; forming a shallow doped region in the well region on both sides of the sacrificial gate, at the sacrificial gate Side forming sidewalls;
  • the buried dielectric is filled in the buried dielectric to form a buried insulating region.
  • the present invention has the following advantages: 1.
  • the thickness of the body region of the ultra-thin transistor is greatly reduced, which effectively reduces the influence of the lateral depletion region on the effective length of the channel when the drain is reverse biased;
  • the formation of the buried insulating region is self-aligned to the gate, which reduces the parasitic resistance under the sidewall; the transistor body region and the well region of the village are separated by the buried insulating region, which avoids the partial polarization modulation effect on the device performance. influences.
  • Figure 1 shows a MOS transistor having raised source and drain regions
  • Fig. 5 is a flow chart showing an embodiment of a method for fabricating an ultrathin body transistor of the present invention
  • Figs. 6 through 21 are cross-sectional views showing an embodiment of a method for fabricating an ultrathin body transistor of the present invention.
  • the thicker body regions of prior art MOS transistors are not conducive to suppressing the short channel effects of the device, limiting further improvements in device performance.
  • the inventors of the present invention provide a MOS transistor having an ultra-thin body region in which a buried insulating region is formed in a substrate, and the buried insulating region is ultra-thin The body area under the gate of the transistor is isolated from the bottom of the cell, and the thickness of the body region of the ultra-thin transistor is thus greatly reduced, thereby effectively suppressing the influence of the short channel effect on the performance of the device.
  • the ultra-thin body transistor of the present invention forms a gate of the MOS transistor and a gate dielectric layer under the gate by a gate replacement process, and the reformed gate further improves the stress characteristics of the channel region.
  • the carrier mobility of the channel region is increased, thereby enhancing the driving capability of the device.
  • the ultra-thin transistor includes: a semiconductor substrate 201; a well region 202 in the semiconductor substrate 201, a trench isolation region 203 outside the well region 202, and the trench isolation region.
  • the ultra-thin transistor further includes a body region sequentially under the gate 213 Insulated area with buried layer (not shown in Figure 2).
  • the ultrathin transistor further includes dummy gates 215 respectively located on both sides of the source and drain regions thereof, the dummy gates 215 are parallel to the gate electrodes 213, one portion is located on the trench isolation region 203, and the other portion is located On the well region 202.
  • FIG. 3 there is shown a cross-sectional structure of an embodiment of the ultrathin body transistor of the present invention taken along the line AA of Fig. 2.
  • the gate structure of the ultra-thin transistor includes a gate dielectric layer 211, a gate electrode 213 embedded in the gate dielectric layer 211, and sidewalls 209 on both sides of the gate electrode 213.
  • the gate electrode 213 passes through the gate dielectric layer. 211 is isolated from sidewall 209 and well region 202.
  • the surface of the source region 205 and the drain region 206 are convex with respect to the surface of the semiconductor substrate 201; and the body region 207 and the buried insulating region 215 are formed under the gate structure, wherein the body The region 207 and the two ends of the buried insulating region 215 are respectively connected to the source region 205 and the drain region 206.
  • the buried insulating region 215 isolates the body region 207 from the remaining region of the well region 202, the source region 205 and the drain region.
  • the bottom depth of 206 is at least greater than the bottom depth of the buried insulating region 215.
  • FIG. 4 there is shown a cross-sectional structure of an embodiment of the ultrathin transistor of the present invention taken along line BB of Fig. 2.
  • the gate electrode 213 is disposed on the well region 202, and the two ends of the gate electrode 213 are respectively located on the trench isolation regions 203 on both sides of the well region 202. Meanwhile, the buried insulating region 215 and the body region 207 are Both ends are also connected to the trench isolation region 203, respectively.
  • the semiconductor substrate 201 is formed of silicon, germanium, silicon, gallium nitride or other semiconductor materials, and the source region 205 and the drain region 206 are made of silicon or other semiconductors.
  • the epitaxial semiconductor material is formed.
  • the surfaces of source region 205 and drain region 206 may also be flush with other surfaces of well region 202 without being raised, and should not be limited in scope.
  • the source region 205 and the drain region 206 have the same doping type and have opposite doping types from the body region 207; the source region 205 and the drain region 206 both contain shallow doping. a doped region and a deep doped region, the deep doped region being located in the well region 202, and the deep doped region extending to the side Below the wall 209, aligned with the edge of the gate 213; the shallow doped region is located in the well region 202 below the sidewall 209, the depth of which exceeds the depth of the body region 207.
  • the buried insulating region 215 is formed of silicon oxide, the sidewall 209 is formed of silicon nitride, and the buried insulating region 215 has a thickness of 20 nm to 100 nm; and the body region 205 is made of silicon, silicon or silicon. Other semiconductor materials are formed, and the body region 205 has a thickness of 5 nm to 20 nm.
  • the gate dielectric layer 211 is formed using silicon oxide, silicon oxynitride or a high-k dielectric material, and the gate electrode 213 is formed of doped polysilicon, a metal material or other conductive material.
  • the thickness of the body region of the ultra-thin body transistor of the present invention is greatly reduced compared with the MOS transistor of the prior art, which effectively reduces the influence of the lateral depletion region on the effective length of the channel when the drain is reverse biased;
  • the formation of the buried insulating region is self-aligned to the gate, reducing parasitic resistance under the sidewall.
  • the body region and the well region at the bottom of the village are separated by a buried insulating region, thereby avoiding the influence of the village bias modulation effect on the performance of the device.
  • the flow of the ultra-thin transistor manufacturing method includes:
  • Step S402 a semiconductor substrate is provided, where the semiconductor substrate comprises a buried layer sacrificial layer and a body region epitaxial layer on the buried layer sacrificial layer;
  • Step S404 forming a trench isolation region in the semiconductor substrate, forming a well region in the semiconductor substrate in the trench isolation region, the trench isolation region and the well region having a depth at least exceeding the buried layer sacrifice The depth of the layer;
  • Step S406 sequentially forming a sacrificial gate dielectric layer, a sacrificial gate and a sacrificial gate protection cap layer on the well region;
  • Step S408 forming shallow doped regions in the well regions on both sides of the sacrificial gate, and forming sidewalls on both sides of the sacrificial gate;
  • Step S410 forming a source/drain region opening in the semiconductor substrate outside the sacrificial gate sidewall, the depth of the source/drain region opening at least exceeding the depth of the buried sacrificial layer;
  • Step S412 filling the source and drain region openings with heavily doped source and drain materials to form deep doped regions;
  • Step S414 forming an interlayer dielectric layer on the semiconductor substrate, the interlayer dielectric layer covering the deep doped region and the sacrificial gate; Step S416, planarizing the interlayer dielectric layer until the protective cap layer surface of the sacrificial gate is exposed;
  • Step S420 anisotropic etching is located in the trench isolation region below the original sacrificial gate position until the buried sacrificial layer is exposed;
  • Step S422 the buried sacrificial layer is removed, and a buried cavity is formed at the sacrificial layer position of the original buried layer;
  • Step S424 filling the buried layer dielectric with a buried dielectric material to form a buried insulating region; performing step S426, sequentially filling the gate dielectric material with the gate conductive material and filling the gate opening After completion, the gate conductive material is higher than the sidewall;
  • Step S430 is performed to etch the interlayer dielectric layer above the source and drain regions to expose the surface of the source and drain regions, and metal contacts are formed on the surface of the source and drain regions.
  • FIG. 13 illustrate respective stages of fabrication of an ultrathin body transistor fabrication method in accordance with an embodiment of the present invention.
  • FIG. 13 and FIG. 20 are schematic cross-sectional views along the line AA of FIG. 2;
  • FIGS. 15 to 17, and FIG. 19 are schematic cross-sectional views along the line BB of FIG. 2; It is a top view of the bottom of the semiconductor village after the formation of the buried cavity.
  • a semiconductor substrate 501 is provided, and a buried sacrificial layer 503 and a body epitaxial layer 505 are sequentially formed on the semiconductor substrate 501.
  • the body region epitaxial layer 505 is used to form a body region of an ultrathin body transistor, a single crystal structure is required. Therefore, in the present embodiment, the body region epitaxial layer 505 and the buried layer sacrificial layer 503 are both formed by epitaxial processes such as molecular beam epitaxy, atomic layer deposition, chemical vapor deposition, etc., to form the body region epitaxial layer 505 and the buried layer sacrifice. Layer 503.
  • the body region epitaxial layer 505 and the buried layer sacrificial layer 503 each have a single crystal structure.
  • the body region epitaxial layer 505 and the buried sacrificial layer 503 have matching lattice constants to avoid stress mismatch.
  • the semiconductor substrate 501 is formed of silicon, germanium, silicon, gallium nitride or other semiconductor materials; the buried layer sacrificial layer 503 is formed of a semiconductor material such as silicon carbide or germanium silicon.
  • the thickness is from 20 nanometers to 100 nanometers; the body region epitaxial layer 505 is formed of silicon, silicon or other semiconductor material and has a thickness of 5 nanometers to 50 nanometers.
  • a trench isolation region 507 is formed in the semiconductor substrate 501.
  • the trench isolation region 507 passes through the body region epitaxial layer 505 and the buried sacrificial layer 503 to the inside of the semiconductor substrate 501.
  • the trench isolation region 507 employs a shallow trench isolation structure (STI).
  • ion implantation is performed on the semiconductor substrate 501, and a well region 509 is formed in the semiconductor substrate 501 in the trench isolation region 507, the depth of the well region 509 exceeding at least the depth of the buried sacrificial layer 503.
  • the sacrificial gate dielectric layer 511, the sacrificial gate 513 and the sacrificial gate protection cap layer 514 are continuously formed on the body region epitaxial layer 505, and at the same time
  • the trench isolation region 507 and the well region 509 parallel to the gate 513 sequentially form a sacrificial gate dielectric layer 511, a trench protection layer 516 and a trench protection cap layer 518.
  • the sacrificial gate dielectric layer 511 and the sacrificial gate 513 are mostly located in the well region 509, and the two ends of the sacrificial gate 513 are located on the trench isolation region 507 outside the well region 509.
  • the trench protection layer 516 is formed of the same material as the sacrificial gate 513, and the sacrificial gate protection cap layer 514 is formed of the same material as the trench protection cap layer 518.
  • the gate dielectric layer 511 is formed of a dielectric material such as silicon oxide, and the sacrificial gate 513 and the trench protection layer 516 are formed of polysilicon, and the sacrificial gate protection cap layer 514 and the trench are formed.
  • the protective cap layer 518 is made of silicon nitride.
  • the semiconductor substrate 501 is ion-implanted, and shallow doped regions 515 are formed on both sides of the sacrificial gate 513.
  • the shallow doped region 515 may have a depth that exceeds the depth of the bulk epitaxial layer 505 and extends into the buried sacrificial layer 503 or the well region 509.
  • a sidewall dielectric layer is formed on the semiconductor substrate 501, and the sidewall dielectric layer covers the trench isolation region 507, the sacrificial gate protection cap layer 514, the trench protection cap layer 518, and Body region epitaxial layer 505.
  • the sidewall dielectric layer is made of silicon nitride, silicon oxynitride or other dielectric material; in a preferred embodiment, the sidewall dielectric layer is made of a material having a larger etching selectivity than the trench isolation region 507.
  • the trench isolation region 507 is made of silicon oxide
  • the sidewall dielectric layer is made of silicon nitride.
  • the sidewall dielectric layer is anisotropically etched, on the body region epitaxial layer 505 on both sides of the sacrificial gate 513, and the body region epitaxial layer 505 and the trench isolation region 509 on both sides of the trench protection layer 516.
  • a sidewall 517 is formed thereon.
  • the sidewall 517, the sacrificial gate 513, and the trench protective layer 516 are used as masks.
  • the shallow doped region and a portion of the well region 509 under the shallow doped region are anisotropically etched to form a source/drain region opening.
  • the shallow doped region is etched, for example, by an SF 6 gas anisotropic dry process. The anisotropic etching is used to avoid defects caused by lateral etching of the shallow doped regions under the sidewalls 517.
  • the etch depth of the source and drain region openings should not exceed the depth of the bottom of the well region 509 to prevent the subsequently formed source and drain regions from being connected to the semiconductor substrate outside the well region 509.
  • a heavily doped source-drain material is epitaxially grown in the source/drain region opening until the source/drain region opening is filled, and the source-drain material in the source/drain region opening is used as a deep transistor transistor.
  • Doped region 521 Since the other regions on the bottom of the semiconductor substrate are covered with a dielectric material, and only the source and drain regions are open to the semiconductor material, the source and drain materials only fill the source and drain region openings.
  • the formed source and drain regions extend toward the bottom of the sidewall 517 to occupy the position of the buried layer sacrificial layer 503 under the sidewall 517. This causes the subsequent buried sacrificial layer 503 to self-align to the gate 513, thereby reducing the parasitic resistance under the sidewall 503.
  • the heavily doped source-drain material may be formed by in-situ doping, or may be formed by epitaxially intrinsic semiconductor material and then ion-implanting for heavy doping.
  • the source and drain material is formed from the same semiconductor material as the bulk epitaxial layer 505.
  • the shallow doped region 515 and the deep doped region 521 together constitute a source and drain region of the ultrathin body transistor.
  • an interlayer dielectric layer 523 is further formed on the source and drain regions, the sacrificial gate protection cap layer 514, the sidewall 517, and the trench protection cap layer 518.
  • the electrical layer 523 at least exceeds the surface of the sacrificial gate protection cap layer 514.
  • the interlayer dielectric layer 523 is planarized until the surface of the sacrificial gate protection cap layer 514 and the trench protection cap layer 518 are exposed.
  • the interlayer dielectric layer 523 is made of a dielectric material having a larger etching selectivity than the trench isolation region 507, such as silicon nitride.
  • the interlayer dielectric layer 523 serves as a mask for subsequently etching the trench isolation region 507.
  • the sacrificial gate protection cap layer, the sacrificial gate layer, the trench protection layer, the trench protection cap layer, and the sacrificial layer are removed by using the interlayer dielectric layer 523 and the sidewall 517 as a mask.
  • a gate dielectric layer forms a gate opening 520 between sidewalls 517. Since the original sacrificial gate and the trench protective layer partially cover the trench isolation region 507, the removal process exposes the trench isolation region 507 and a portion of the surface of the bulk epitaxial layer 505. Depending on the specific embodiment, it can be removed by a dry etching process.
  • the sacrificial gate protection cap layer, the trench protection cap layer, the sacrificial gate and the trench protection layer, and the sacrificial gate protection cap layer, the trench protection cap layer, and the sacrificial gate may also be removed by a wet etching process. Pole and trench protection layer.
  • the sacrificial gate made of polysilicon may be etched by using a plasma gas containing SF 6 , HBr, Cl 2 and an inert gas; and if the wet etching process is used Then, the sacrificial grid can be etched with a tetramethylammonium hydroxide (TMAH) solution at a temperature of 60 degrees Celsius to 90 degrees Celsius.
  • TMAH tetramethylammonium hydroxide
  • the interlayer dielectric layer 523 and the sidewall 517 are used as a mask, and the exposed portion is partially etched.
  • the trench isolation region 507 is exposed until the side surface of the buried sacrificial layer 503. Since the interlayer dielectric layer 523 and the sidewall 517 are different from the trench isolation region 507, the etching of the trench isolation region 507 does not affect the interlayer dielectric layer 523 and the sidewall 517.
  • the exposed buried sacrificial layer is removed by an isotropic dry etching or wet etching process to form a buried void 525.
  • the buried void 525 causes the bulk epitaxial layer 505 to float.
  • the source and drain regions can be used to support the partially suspended body region epitaxial layer 505.
  • the buried sacrificial layer should have a larger etching selectivity than the semiconductor substrate 501 and the body epitaxial layer 505, the sidewall 517, the source and drain regions, and the trench isolation region 507.
  • the body region epitaxial layer 505 is silicon
  • the sidewall 517 is silicon nitride
  • the trench isolation region 507 is silicon oxide
  • the buried layer sacrificial layer is made of silicon carbide; correspondingly, A mixed solution of hydrochloric acid and hydrofluoric acid etches the buried sacrificial layer.
  • Figure 14 is a plan view of the semiconductor substrate after forming a buried cavity. As shown in FIG. 14, the trench isolation regions in the sidewalls 517 have been removed, and the removed trench isolation regions allow etching gas or corrosive liquid to enter the semiconductor substrate and embed the buried layer. The sacrificial layer is removed, and a buried void 525 is formed.
  • Figure 13 shows the cross-sectional structure of the semiconductor substrate along the AA direction in Figure 14.
  • Fig. 15 shows the cross-sectional structure of the semiconductor substrate along the line BB in Fig. 14.
  • the buried sacrificial layer under the original sacrificial gate position is completely removed, and the body epitaxial layer 505 is suspended on the semiconductor substrate 501.
  • the buried dielectric is filled with a buried dielectric material to form a buried insulating region. 527.
  • the buried insulating region 527 replaces the previous buried sacrificial layer as an isolation structure between the bulk epitaxial layer 505 and the well region 509.
  • a dielectric material is also formed at the sacrificial gate position during the filling of the buried cavity.
  • the overfilled dielectric material may be planarized such that it is flush with the interlayer dielectric layer and sidewalls. Thereafter, the dielectric material at the sacrificial gate location continues to be etched until the bulk epitaxial layer 505 is exposed. In this way, the gate opening is reformed.
  • the buried insulating region 527 needs to be formed by a thin film forming process with a relatively high filling ability such as atomic layer deposition or low-pressure chemical vapor deposition, so as to prevent the buried void from being completely filled and forming defects, thereby affecting the device. performance.
  • the buried insulating region 527 and the interlayer dielectric layer have a material having a large etching selectivity, for example, the buried insulating region 527 is composed of silicon oxide.
  • the buried insulating region 527 has the same thickness as the buried sacrificial layer, that is, 20 nm to 100 nm.
  • a gate dielectric material is deposited in the gate opening 520 to form the gate dielectric layer 529.
  • the gate dielectric material is silicon oxide, silicon oxynitride or a high-k dielectric material.
  • the gate conductive material is continuously filled in the gate opening. After the filling is completed, the gate conductive material is higher than the top of the sidewall.
  • the gate conductive material is planarized until the gate conductive material is flush with the sidewall, and the gate conductive material in the gate opening is a gate or a dummy gate, wherein the gate in the source-drain interval
  • the pole conductive material is the gate 530, and the gate conductive material on the trench isolation region 507 outside the source and drain regions is the dummy gate 531.
  • the interlayer dielectric layer 523 is partially etched to expose the surface of the source and drain regions, and a metal contact 532 is formed on the surface of the source and drain regions.
  • the device structure of the ultrathin body transistor of the present invention is formed. In actual fabrication, it is also necessary to continue to form contact holes to extract the source region, the drain region, and the gate electrode, and details are not described herein.
  • the ultra-thin transistor manufacturing method of the present invention forms a buried insulating region under the body region by forming a buried sacrificial layer in the semiconductor substrate in advance, thereby replacing the buried sacrificial layer.
  • the invention is well compatible with the prior art MOS transistor fabrication process, and is realized by a convenient method. Thinning of the transistor body region.

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Abstract

一种超薄体晶体管及其制作方法。所述超薄体晶体管包括：半导体衬底、所述半导体衬底上的栅极结构以及栅极结构两侧半导体衬底中的源区与漏区，其中，所述栅极结构包括栅介电层、嵌于栅介电层中的栅极以及栅极两侧的侧壁；所述超薄体晶体管还包括：依次位于所述栅极结构下方阱区中的体区与埋层绝缘区，其中，所述体区与埋层绝缘区的两端分别连接源区与漏区，所述体区下方的埋层绝缘区将体区与阱区的其余区域相隔离。本发明超薄体晶体管有效抑制了短沟道效应对器件性能的影响。而本发明的超薄体晶体管制作方法结合栅极替换工艺，使埋层绝缘区的形成自对准于栅极，降低了侧壁下的寄生电阻。

Description

超薄体晶体管及其制作方法
本申请要求于 2010 年 08 月 18 日提交中国专利局、 申请号为 201010257023.2,发明名称为 "超薄体晶体管及其制作方法"的中国专利申请的 优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域， 更具体地， 本发明涉及一种超薄体晶体管及 其制作方法。
背景技术
随着半导体制作技术的不断进步，集成在同一芯片上的元器件数量已从最 初的几十几百个进化到现在的数以百万计。目前 IC的性能和复杂度远非当初所 能想象。 为了满足复杂度和电路密度的要求， 最小的特征尺寸， 也就是公知的 器件的 "几何线宽" 随着工艺技术的革新而越来越小。 如今， MOS晶体管的 最小线宽已经小于 45纳米。
在半导体器件最小线宽不断缩小的情况下， 为了改善 MOS晶体管的短沟 道特性， 各种新型的 MOS器件结构被研发出来。 申请号为 US7569443的美国专 利申请即公开了一种具有凸起源漏区的 MOS晶体管。 参考图 1 , 示出了所述具 有凸起源漏区的 MOS晶体管。 所述凸起源漏区 105分别位于栅极 103两侧的半 导体村底 101上。 在制作所述 MOS晶体管时， 需要在形成牺牲栅极之后刻蚀所 述牺牲栅极两侧的阱区， 以形成源漏区沟槽； 之后， 再在所述源漏区沟槽中填 充锗硅材料直至形成凸起的源漏区。 所述凸起的源漏区在 MOS晶体管的沟道 区引入了一定的应力， 进而使得沟道区载流子迁移率提高， MOS 晶体管的电 流驱动能力得以明显提升。 同时， 为了改善所述 MOS晶体管沟道区的应力特 性， 该专利还采用了栅极替换工艺， 所述栅极替换工艺是指在凸起源漏区制作 完成后，将牺牲栅极移除并重新填充导带材料以形成栅极的工艺方法。所述重 新形成的栅极进一步改善了沟道区的应力特性， 提高了沟道区载流子的迁移 率。
然而， 所述 MOS晶体管的体区较厚， 较厚的体区不利于抑制器件的短沟道效应， 限制 了器件尺寸的进一步缩小和性能的进一步提升。
发明内容 本发明解决的问题是提供一种超薄体晶体管及其制作方法，所述超薄体晶 体管具有较薄的体区， 可以减少漏极反向偏置时产生的横向耗尽区长度，从而 有效抑制了器件的短沟道效应。
为解决上述问题， 本发明提供了一种超薄体晶体管， 包括： 半导体村底、 所述半导体村底上的栅极结构以及栅极结构两侧半导体村底中的源区与漏区， 其特征在于， 所述栅极结构包括栅介电层、嵌于栅介电层中的栅极以及栅极两 侧的侧壁； 所述超薄体晶体管还包括： 依次位于所述栅极结构下方阱区中的体 区与埋层绝缘区， 其中， 所述体区与埋层绝缘区的两端分别连接源区与漏区， 所述体区下方的埋层绝缘区将体区与阱区的其余区域相隔离。
相应的， 本发明还提供了一种超薄体晶体管的制作方法， 包括： 区外延层；
在所述半导体村底中形成沟槽隔离区，在所述沟槽隔离区内的半导体村底 中形成阱区， 所述沟槽隔离区与阱区的深度至少超过埋层牺牲层的深度； 在所述阱区上依次形成牺牲栅介电层、 牺牲栅极与牺牲栅极保护帽层； 在所述牺牲栅极两侧的阱区中形成浅掺杂区，在所述牺牲栅极两侧形成侧 壁；
在牺牲栅极侧壁外的半导体村底中形成源漏区开口，所述源漏区开口的深 度至少超过埋层牺牲层的深度；
在所述源漏区开口中填满重掺杂的源漏材料， 形成深掺杂区；
在所述半导体村底上形成层间介电层，所述层间介电层覆盖深掺杂区与牺 牲栅极；
平坦化所述层间介电层， 直至露出所述牺牲栅极的保护帽层表面； 移除所述牺牲栅极保护帽层、 牺牲栅极、 牺牲栅介电层， 形成栅极开口； 各向异性刻蚀位于原牺牲栅极位置下方的沟槽隔离区，直至露出埋层牺牲 层；
移除所述埋层牺牲层， 在原埋层牺牲层位置形成埋层空洞；
在所述埋层空洞中填满埋层介电材料以形成埋层绝缘区。
与现有技术相比， 本发明具有以下优点： 1. 所述超薄体晶体管的体区厚度大大降低， 这有效降低了漏极反偏时横 向耗尽区对沟道有效长度的影响；
2. 埋层绝缘区的形成自对准于栅极， 降低了侧壁下方的寄生电阻； 晶体管体区与村底的阱区由埋层绝缘区隔离，避免了村偏调制效应对器件性能 的影响。
附图说明
图 1示出了一种具有凸起源漏区的 MOS晶体管；
图 2至图 4示出了本发明超薄体晶体管的一个实施例；
图 5示出了本发明超薄体晶体管制作方法一个实施例的流程示意图； 图 6至图 21示出了本发明超薄体晶体管制作方法一个实施例的剖面示意 图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明 还可以采用其他不同于在此描述的其它方式来实施，因此本发明不受下面公开 的具体实施例的限制。
正如背景技术部分所述， 现有技术 MOS晶体管较厚的体区不利于抑制器 件的短沟道效应， 限制了器件性能的进一步提升。 针对这一问题， 本发明的发 明人提供了一种具有超薄体区的 MOS晶体管， 所述超薄体晶体管的村底中形 成有埋层绝缘区，所述埋层绝缘区将超薄体晶体管栅极下方的体区与村底隔离 开，超薄体晶体管体区的厚度因此大大降低， 进而有效抑制了短沟道效应对器 件性能的影响。
同时，本发明的超薄体晶体管采用栅极替换工艺形成 MOS晶体管的栅极、 以及所述栅极下方的栅介电层，所述重新形成的栅极进一步改善了沟道区的应 力特性， 提高了沟道区的载流子迁移率， 从而使得器件的驱动能力得以增强。
接下来， 结合具体的实施例，对本发明的超薄体晶体管及其制作方法进行 说明。
参考图 2, 示出了本发明超薄体晶体管一实施例的俯视示意图。 如图 2所示， 所述超薄体晶体管包括： 半导体村底 201 ; 所述半导体村底 201 中的阱区 202, 所述阱区 202外的沟槽隔离区 203 , 所述沟槽隔离区 203 围绕阱区 202; 阱区 202上的栅极 213 , 所述栅极 213横跨阱区 202, 其两端 位于沟槽隔离区 203上； 所述栅极 213两侧的半导体村底 201上的栅介电层 211与侧壁 209; 以及所述栅极 213两侧阱区 202中的源区 205与漏区 206; 所述超薄体晶体管还包含有依次位于栅极 213 下的体区与埋层绝缘区 （图 2 中未示出）。 在本实施例中， 所述超薄晶体管还包含有分别位于其源漏区两侧 的伪栅 215 , 所述伪栅 215与栅极 213平行， 一部分位于沟槽隔离区 203上， 另一部分位于阱区 202上。
参考图 3 ,示出了本发明超薄体晶体管一实施例沿图 2中 AA，方向的剖面 结构。 其中， 超薄体晶体管的栅极结构包括栅介电层 211、 嵌于栅介电层 211 中的栅极 213以及栅极 213两侧的侧壁 209, 所述栅极 213通过栅介电层 211 与侧壁 209、 阱区 202相隔离。
在本实施例中， 所述源区 205与漏区 206的表面相对于半导体村底 201 表面凸起； 所述栅极结构下形成有体区 207与埋层绝缘区 215 , 其中， 所述体 区 207与埋层绝缘区 215的两端分别连接源区 205与漏区 206, 所述埋层绝缘 区 215将体区 207与阱区 202的其余区域相隔离， 所述源区 205与漏区 206 底部深度至少超过埋层绝缘区 215的底部深度。
参考图 4, 示出了本发明超薄晶体管一实施例沿图 2中 BB，方向的剖面结 构。 如图 4所示， 所述栅极 213横跨阱区 202上， 其两端分别位于阱区 202 两侧的沟槽隔离区 203上， 同时， 所述埋层绝缘区 215、 体区 207的两端也分 别与沟槽隔离区 203相连接。
在本实施例中， 所述半导体村底 201采用硅、 锗、 错硅、 氮化镓或其他半 导体材料形成， 所述源区 205与漏区 206采用错硅或其他易于在半导体村底 201上外延的半导体材料形成。 依据具体实施例的不同， 所述源区 205与漏区 206的表面也可以与阱区 202的其他表面相平而并不凸起， 不应限制其范围。
与现有 MOS晶体管相类似， 所述源区 205与漏区 206具有相同的掺杂类 型， 并与体区 207具有相反的掺杂类型； 所述源区 205与漏区 206均包含有浅 掺杂区与深掺杂区， 所述深掺杂区位于阱区 202中，且所述深掺杂区延伸至侧 壁 209下方， 与栅极 213的边缘对准； 所述浅掺杂区位于侧壁 209下方的阱区 202中， 其深度超过体区 207的深度。
所述埋层绝缘区 215采用氧化硅形成， 所述侧壁 209采用氮化硅形成， 所 述埋层绝缘区 215的厚度为 20纳米至 100纳米； 所述体区 205采用硅、 错硅 或其他半导体材料形成， 所述体区 205的厚度为 5纳米至 20纳米。
所述栅介电层 211采用氧化硅、 氮氧化硅或高 k介电材料形成， 所述栅极 213采用掺杂的多晶硅、 金属材料或其他导电材料形成。
可以看出， 相较于现有技术的 MOS晶体管， 本发明的超薄体晶体管的体 区厚度大大降低， 这有效降低了漏极反偏时横向耗尽区对沟道有效长度的影 响； 同时，所述埋层绝缘区的形成自对准于栅极，降低了侧壁下方的寄生电阻。 此外， 所述体区与村底的阱区由埋层绝缘区隔离，避免了村偏调制效应对器件 性能的影响。
基于本发明超薄体晶体管的结构，发明人还提供了超薄体晶体管的制作方 法的流程。 参考图 5 , 所述超薄体晶体管制作方法的流程包括：
执行步骤 S402, 提供半导体村底， 所述半导体村底包含有埋层牺牲层与 埋层牺牲层上的体区外延层；
执行步骤 S404, 在所述半导体村底中形成沟槽隔离区， 在所述沟槽隔离 区内的半导体村底中形成阱区，所述沟槽隔离区与阱区的深度至少超过埋层牺 牲层的深度；
执行步骤 S406, 在所述阱区上依次形成牺牲栅介电层、 牺牲栅极与牺牲 栅极保护帽层；
执行步骤 S408 , 在所述牺牲栅极两侧的阱区中形成浅掺杂区， 在所述牺 牲栅极两侧形成侧壁；
执行步骤 S410, 在牺牲栅极侧壁外的半导体村底中形成源漏区开口， 所 述源漏区开口的深度至少超过埋层牺牲层的深度；
执行步骤 S412, 在所述源漏区开口中填满重掺杂的源漏材料， 形成深掺 杂区；
执行步骤 S414, 在所述半导体村底上形成层间介电层， 所述层间介电层 覆盖深掺杂区与牺牲栅极； 执行步骤 S416, 平坦化所述层间介电层， 直至露出所述牺牲栅极的保护 帽层表面；
执行步骤 S418 , 移除所述牺牲栅极保护帽层、 牺牲栅极、 牺牲栅介电层， 形成栅极开口；
执行步骤 S420, 各向异性刻蚀位于原牺牲栅极位置下方的沟槽隔离区， 直至露出埋层牺牲层；
执行步骤 S422, 移除所述埋层牺牲层， 在原埋层牺牲层位置形成埋层空 洞；
执行步骤 S424,在所述埋层空洞中填满埋层介电材料以形成埋层绝缘区； 执行步骤 S426, 在所述栅极开口中依次填充栅极介电材料与栅极导电材 料， 填充完成后所述栅极导电材料高于侧壁；
执行步骤 S428, 平坦化所述栅极导电材料直至所述栅极导电材料与侧壁 平齐， 所述栅极开口中的栅极导电材料即为栅极；
执行步骤 S430, 刻蚀源漏区上方的层间介电层， 露出源漏区表面， 在所 述源漏区表面形成金属接触。
图 6至图 21示出了本发明实施例的超薄体晶体管制作方法各制作阶段。 其中， 图 6至图 13、 图 18以及图 20是沿图 2中 AA，向的剖面结构示意图； 图 15至图 17、 以及图 19是沿图 2中 BB，向的剖面结构示意图； 图 14是形成 埋层空洞后半导体村底的俯视图。
如图 6所示， 提供半导体村底 501 , 在所述半导体村底 501上依次形成埋 层牺牲层 503与体区外延层 505。
由于所述体区外延层 505 用于形成超薄体晶体管的体区， 需要为单晶结 构。 因此， 在本实施例中， 形成所述体区外延层 505与埋层牺牲层 503均采用 分子束外延、 原子层沉积、 化学气相沉积等外延工艺， 以形成体区外延层 505 与埋层牺牲层 503。 所述体区外延层 505与埋层牺牲层 503均具有单晶结构。 优选的， 所述体区外延层 505与埋层牺牲层 503具有匹配的晶格常数， 以避免 应力失配。
在具体实施例中， 所述半导体村底 501采用硅、 锗、 错硅、 氮化镓或其他 半导体材料形成； 所述埋层牺牲层 503采用碳化硅、 锗硅等半导体材料形成， 其厚度为 20纳米至 100纳米； 所述体区外延层 505采用硅、 错硅或其他半导 体材料形成， 其厚度为 5纳米至 50纳米。
如图 7所示， 在所述半导体村底 501中形成沟槽隔离区 507。 所述沟槽隔 离区 507穿过体区外延层 505、 埋层牺牲层 503至半导体村底 501内部。 在具 体实施例中， 所述沟槽隔离区 507采用浅沟槽隔离结构 （ STI )。
接着，对所半导体村底 501进行离子注入，在所述沟槽隔离区 507内的半 导体村底 501中形成阱区 509, 所述阱区 509的深度至少超过埋层牺牲层 503 的深度。
在所述沟槽隔离区 507与阱区 509形成之后， 继续在所述体区外延层 505 上形成牺牲栅介电层 511、 牺牲栅极 513与牺牲栅极保护帽层 514, 同时在与 牺牲栅极 513平行的沟槽隔离区 507与阱区 509的边界依次形成牺牲栅介电层 511、 沟槽保护层 516与沟槽保护帽层 518。 其中， 所述牺牲栅介电层 511与 牺牲栅极 513大部分位于阱区 509内， 所述牺牲栅极 513的两端位于阱区 509 外的沟槽隔离区 507上。所述沟槽保护层 516与牺牲栅极 513采用相同的材料 形成， 所述牺牲栅极保护帽层 514与沟槽保护帽层 518采用相同的材料形成。 在具体实施例中， 所述栅介电层 511采用氧化硅等介电材料形成， 所述牺牲栅 极 513与沟槽保护层 516采用多晶硅形成，所述牺牲栅极保护帽层 514与沟槽 保护帽层 518采用氮化硅。
之后，对所述半导体村底 501进行离子注入，在所述牺牲栅极 513两侧的 形成浅掺杂区 515。 在具体实施例中， 所述浅掺杂区 515的深度可以超过体区 外延层 505的深度， 并延伸至埋层牺牲层 503或阱区 509中。
如图 8所示，在所述半导体村底 501上形成侧壁介电层， 所述侧壁介电层 覆盖沟槽隔离区 507、 牺牲栅极保护帽层 514、 沟槽保护帽层 518以及体区外 延层 505。 所述侧壁介电层采用氮化硅、 氮氧化硅或其他介电材料； 优选的实 施例中， 所述侧壁介电层采用与沟槽隔离区 507具有较大刻蚀选择比的材料， 例如所述沟槽隔离区 507采用氧化硅， 所述侧壁介电层采用氮化硅。 之后， 各 向异性刻蚀所述侧壁介电层， 在牺牲栅极 513两侧的体区外延层 505上、 以及 沟槽保护层 516两侧的体区外延层 505与沟槽隔离区 509上形成侧壁 517。
如图 9所示， 以侧壁 517、 牺牲栅极 513以及沟槽保护层 516为掩膜， 各 向异性刻蚀所述浅掺杂区及所述浅掺杂区下方的部分阱区 509, 形成源漏区开 口。 例如采用 SF6气体各向异性干法刻蚀所述浅掺杂区。 之所以采用各向异性 刻蚀， 是为了避免侧壁 517下方的浅掺杂区被侧向刻蚀而产生的缺陷。
在具体实施例中，所述源漏区开口的刻蚀深度不应超过阱区 509底部的深 度， 以避免后续形成的源漏区与阱区 509外的半导体村底相连接。
接着，在所述源漏区开口中外延重掺杂的源漏材料， 直至填满所述源漏区 开口， 所述源漏区开口中的源漏材料即用于作为超薄体晶体管的深掺杂区 521。 由于所述半导体村底上的其他区域均覆盖有介电材料， 而仅有源漏区开 口为半导体材料， 因此， 所述源漏材料仅填充所述源漏区开口。
在本实施例中， 所述形成的源漏区向侧壁 517的底部延伸， 占据了所述侧 壁 517下方原埋层牺牲层 503的位置。这使得后续埋层牺牲层 503 自对准于栅 极 513 , 从而降低了侧壁 503下方的寄生电阻。
依据具体实施例的不同，所述重掺杂的源漏材料可以采用在位掺杂的方法 形成，也可以先外延本征半导体材料，再进行离子注入进行重掺杂的方法形成。 优选的实施例中， 所述源漏材料与体区外延层 505 采用相同的半导体材料形 成。
如图 10所示， 所述浅掺杂区 515与深掺杂区 521共同构成了超薄体晶体 管的源漏区。 在所述源漏区形成之后， 继续在所述源漏区、 牺牲栅极保护帽层 514、 侧壁 517、 以及沟槽保护帽层 518上形成层间介电层 523 , 所述层间介电 层 523至少超过所述牺牲栅极保护帽层 514的表面。 紧接着， 平坦化所述层间 介电层 523 ,直至露出所述牺牲栅极保护帽层 514与沟槽保护帽层 518的表面。
在本实施例中，所述层间介电层 523采用与沟槽隔离区 507具有较大刻蚀 选择比的介电材料， 例如氮化硅。所述层间介电层 523作为后续刻蚀沟槽隔离 区 507的掩膜。
如图 11所示， 以所述层间介电层 523与侧壁 517为掩膜， 移除所述牺牲 栅极保护帽层、 牺牲栅极、 沟槽保护层、 沟槽保护帽层、 牺牲栅介电层， 形成 位于侧壁 517间的栅极开口 520。 由于原牺牲栅极与沟槽保护层均有部分覆盖 于沟槽隔离区 507上， 因此， 所述移除处理使得沟槽隔离区 507与体区外延层 505的部分表面露出。 依据具体实施例的不同， 既可以采用干法刻蚀工艺移除 所述牺牲栅极保护帽层、 沟槽保护帽层、 牺牲栅极与沟槽保护层， 也可以采用 湿法腐蚀工艺移除所述牺牲栅极保护帽层、 沟槽保护帽层、牺牲栅极与沟槽保 护层。
在采用干法刻蚀工艺处理时， 可以采用包含有 SF6、 HBr、 Cl2及惰性气体 的等离子体气体进行刻蚀所述采用多晶硅构成的牺牲栅极；而若采用湿法腐蚀 工艺处理时， 则可以四甲基氢氧化氨 ( TMAH )溶液进行腐蚀所述牺牲栅极， 所述反应温度为 60摄氏度至 90摄氏度。
如图 12所示， 在完全移除所述牺牲栅极及其下方的牺牲栅介电层之后， 以所述层间介电层 523与侧壁 517为掩膜， 部分刻蚀所述露出的沟槽隔离区 507, 直至所述埋层牺牲层 503的侧面露出。 由于所述层间介电层 523与侧壁 517采用与沟槽隔离区 507不同的介电材料， 所述沟槽隔离区 507的刻蚀不会 影响层间介电层 523与侧壁 517。
如图 13所示， 采用各向同性干法刻蚀或湿法腐蚀工艺， 移除所述露出的 埋层牺牲层，形成埋层空洞 525。所述埋层空洞 525使得体区外延层 505悬空。 但由于源漏区位置的埋层牺牲层在形成源漏区时已被移除，所述源漏区可以用 来支撑部分悬空的体区外延层 505。
在具体实施例中，所述埋层牺牲层应具有相对于半导体村底 501及体区外 延层 505、 侧壁 517、 源漏区以及沟槽隔离区 507较大刻蚀选择比的材料。 在 所述半导体村底 501、 体区外延层 505为硅， 侧壁 517为氮化硅， 沟槽隔离区 507为氧化硅的条件下， 所述埋层牺牲层采用碳化硅； 相应的， 采用盐酸与氢 氟酸的混合溶液腐蚀所述埋层牺牲层。
图 14是形成埋层空洞后所述半导体村底的俯视图。如图 14所示， 所述侧 壁 517内的沟槽隔离区均已被移除，所述移除的沟槽隔离区使得刻蚀气体或腐 蚀液体可以进入半导体村底内， 并将埋层牺牲层移除， 形成了埋层空洞 525。
图 13即为半导体村底沿图 14中 AA，向的剖面结构。 而图 15则示出了所 述半导体村底沿图 14中 BB，向的剖面结构。
如图 15所示， 原牺牲栅极位置下方的埋层牺牲层完全被移除， 体区外延 层 505悬空于所述半导体村底 501上。
如图 16 所示， 在所述埋层空洞中填满埋层介电材料以形成埋层绝缘区 527。 所述埋层绝缘区 527替换了之前的埋层牺牲层， 作为体区外延层 505与 阱区 509间的隔离结构。
为了保证所述埋层绝缘区 527的填充质量， 需要过填充所述埋层空洞， 以 及原牺牲栅极位置。 因此， 在本实施例中， 在所述埋层空洞的填充过程中， 还 会在牺牲栅极位置形成介电材料。对于所述过填充的介电材料， 可以对其进行 平坦化处理， 使得其与层间介电层及侧壁平齐。 之后， 继续刻蚀所述牺牲栅极 位置的介电材料， 直至露出体区外延层 505。 这样， 重新形成了栅极开口。
在实际制作中， 需要采用原子层沉积、低压化学气相淀积等具有较强填充 能力的薄膜制作工艺形成所述埋层绝缘区 527, 避免所述埋层空洞无法完全填 充而形成缺陷，影响器件性能。所述埋层绝缘区 527与层间介电层具有较大刻 蚀选择比的材料， 例如所述埋层绝缘区 527由氧化硅构成。
在本实施例中， 所述埋层绝缘区 527与埋层牺牲层的厚度相同， 即 20纳 米至 100纳米。
如图 17与图 18所示， 在埋层绝缘区 527填充之后， 在所述栅极开口 520 中淀积栅介电材料以构成栅介电层 529。 所述栅介电材料为氧化硅、 氮氧化硅 或高 k介电材料。
如图 19与图 20所示，在形成栅介电层 529之后， 继续在所述栅极开口填 充栅极导电材料， 填充完成后， 所述栅极导电材料的高于侧壁顶部。
接着， 平坦化所述栅极导电材料直至所述栅极导电材料与侧壁平齐， 所述 栅极开口中的栅极导电材料即为栅极或伪栅极，其中位于源漏区间的栅极导电 材料为栅极 530, 位于源漏区外的沟槽隔离区 507 上的栅极导电材料为伪栅 531。
如图 21所示， 部分刻蚀所述层间介电层 523 , 露出源漏区表面， 在所述 源漏区表面形成金属接触 532。
上述步骤实施后， 本发明超薄体晶体管的器件结构即制作形成。在实际制 作中， 还需要继续形成接触孔以引出源区、 漏区及栅极， 在此不再赘述。
本发明的超薄体晶体管制作方法通过预先在半导体村底中形成埋层牺牲 层， 进而替换所述埋层牺牲层的方法来形成位于体区下方的埋层绝缘区。本发 明很好的兼容了现有技术的 MOS晶体管制作工艺， 以筒便易行的方法实现了 晶体管体区的减薄。
应该理解， 此处的例子和实施例仅是示例性的， 本领域技术人员可以在不 背离本申请和所附权利要求所限定的本发明的精神和范围的情况下，做出各种 修改和更正。

Claims

权 利 要 求
1. 一种超薄体晶体管， 包括半导体村底、 所述半导体村底上的栅极结构以及 栅极结构两侧半导体村底中的源区与漏区， 其特征在于， 所述栅极结构包 括栅介电层、 嵌于栅介电层中的栅极以及栅极两侧的侧壁； 所述超薄体晶 体管还包括： 依次位于所述栅极结构下方阱区中的体区与埋层绝缘区， 其 中， 所述体区与埋层绝缘区的两端分别连接源区与漏区， 所述体区下方的 埋层绝缘区将体区与阱区的其余区域相隔离。
2.如权利要求 1 所述的超薄体晶体管， 其特征在于， 所述源区与漏区的表面 相对于半导体村底表面凸起。
3.如权利要求 1 所述的超薄体晶体管， 其特征在于， 所述源区与漏区底部深 度超过埋层绝缘区的底部深度。
4.如权利要求 1 所述的超薄体晶体管， 其特征在于， 所述源区和漏区包含有 浅掺杂区和深掺杂区， 所述浅掺杂区的深度超过所述体区的深度， 所述深 掺杂区延伸至所述侧壁下方。
5.如权利要求 1 所述的超薄体晶体管， 其特征在于， 所述埋层绝缘区采用氧 化硅形成， 所述侧壁采用氮化硅形成。
6.如权利要求 1 所述的超薄体晶体管， 其特征在于， 所述埋层绝缘区的厚度 为 20纳米至 100纳米。
7.如权利要求 1 所述的超薄体晶体管， 其特征在于， 所述体区为单晶结构， 采用硅或错硅形成。
8.如权利要求 1所述的超薄体晶体管， 其特征在于， 所述体区的厚度为 5纳 米至 50纳米。
9.如权利要求 1 所述的超薄体晶体管， 其特征在于， 所述栅介电层采用氧化 硅、 氮化硅或高 k介电材料形成。
10.如权利要求 1 所述的超薄体晶体管， 其特征在于， 所述栅极采用金属材料 或掺杂的多晶硅形成。
11.一种超薄体晶体管的制作方法， 其特征在于， 包括： 区外延层； 在所述半导体村底中形成沟槽隔离区，在所述沟槽隔离区内的半导体村底 中形成阱区， 所述沟槽隔离区与阱区的深度至少超过埋层牺牲层的深度； 在所述阱区上依次形成牺牲栅介电层、 牺牲栅极与牺牲栅极保护帽层； 在所述牺牲栅极两侧的阱区中形成浅掺杂区，在所述牺牲栅极两侧形成侧 壁；
在牺牲栅极侧壁外的半导体村底中形成源漏区开口，所述源漏区开口的深 度至少超过埋层牺牲层的深度；
在所述源漏区开口中填满重掺杂的源漏材料， 形成深掺杂区；
在所述半导体村底上形成层间介电层，所述层间介电层覆盖深掺杂区与牺 牲栅极；
平坦化所述层间介电层， 直至露出所述牺牲栅极的保护帽层表面； 移除所述牺牲栅极保护帽层、 牺牲栅极、 牺牲栅介电层， 形成栅极开口； 各向异性刻蚀位于原牺牲栅极位置下方的沟槽隔离区，直至露出埋层牺牲 层；
移除所述埋层牺牲层， 在原埋层牺牲层位置形成埋层空洞；
在所述埋层空洞中填满埋层介电材料以形成埋层绝缘区。
12.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 所述半导体 村底采用硅、 锗、 错硅或氮化镓形成。
13.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 所述埋层牺 牲层与体区外延层具有单晶结构， 采用外延工艺形成所述单晶结构的埋层 牺牲层与体区外延层。
14.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 所述埋层牺 牲层采用碳化硅或锗硅形成。
15.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 所述埋层牺 牲层的厚度为 20纳米至 100纳米。
16.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 所述体区外 延层采用硅或错硅形成。
17.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 所述体区外 延层的厚度为 5纳米至 50纳米。
18.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 所述浅掺杂 区的深度超过体区外延层底部的深度。
19.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 采用各向异 性刻蚀所述半导体村底以形成源漏区开口， 且所述源漏区开口的刻蚀深度 超过阱区底部的深度。
20.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 所述重掺杂 的源漏材料采用在位掺杂选择性外延的方法形成， 或采用离子注入进行重 掺杂的方法形成。
21.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 采用湿法腐 蚀或各向同性刻蚀的方法移除所述埋层牺牲层并形成埋层空洞。
22.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 采用原子层 沉积或低压化学气相淀积填充所述埋层空洞并形成所述埋层绝缘区。
23.如权利要求 11所述的超薄体晶体管的制作方法， 其特征在于， 采用栅极替 换工艺形成所述超薄体晶体管的栅极结构， 包括：
在所述栅极开口中依次填充栅极介电材料与栅极导电材料，填充完成后所 述栅极导电材料高于侧壁；
平坦化所述栅极导电材料直至所述栅极导电材料与侧壁平齐，所述栅极开 口中的栅极导电材料即为栅极。
24.如权利要求 23所述的超薄体晶体管的制作方法， 其特征在于， 所述栅极介 电材料采用氧化硅、 氮化硅或高 k介电材料。
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