WO2011161759A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2011161759A1 WO2011161759A1 PCT/JP2010/060509 JP2010060509W WO2011161759A1 WO 2011161759 A1 WO2011161759 A1 WO 2011161759A1 JP 2010060509 W JP2010060509 W JP 2010060509W WO 2011161759 A1 WO2011161759 A1 WO 2011161759A1
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- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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Definitions
- the present invention relates to a semiconductor device used in a transmission circuit of a wireless communication device.
- a plurality of amplifier circuits are provided to amplify a radio frequency (RF) transmission signal to a desired output power.
- These amplifier circuits are required to have a sufficiently wide dynamic range with respect to the peak-to-average power ratio (PAPR) of the transmission signal in order to keep the distortion of the transmission signal within the standard.
- PAPR peak-to-average power ratio
- the output signal of the amplifier circuit is distorted, so that the adjacent channel leakage power ratio (ACLR), which is the ratio between the power of the main signal channel and the leakage power of the adjacent channel. This is because Adjacent Channel Leakage Ratio) deteriorates.
- ACLR adjacent channel leakage power ratio
- the PAPR of the transmission signal is closely related to the modulation method and the number of multiplexed data channels, and generally the PAPR increases as the data transfer rate increases. Therefore, in order to suppress the deterioration of the adjacent channel leakage power ratio, the back-off of the amplifier circuit (difference between the saturated output power and the actual operation output power) is appropriately adjusted according to the modulation method and the number of channel multiplexing. There is a need.
- the appropriate back-off magnitude of the power amplification circuit is calculated by analyzing the waveform of the baseband signal. Based on the calculated back-off, the amplitude of the RF signal input to the power amplifier circuit or the power source power supplied to the power amplifier circuit is controlled.
- the maximum value of transmission power is controlled to be uniform among a plurality of modulation schemes.
- the average power of the transmission signal becomes a variable value that differs among a plurality of modulation schemes.
- the gain of the variable gain amplifying circuit is controlled in accordance with a signal designating a modulation method, which is input from a central processing unit (CPU).
- Patent Document 3 Japanese Patent Laid-Open No. 2007-5996 can transmit a signal without distortion in a high-speed communication mode with a relatively high data transfer rate and reduce current consumption of an amplifier circuit in a normal mode with a relatively low data transfer rate A communication device is disclosed.
- the amplifier circuit of the transmission unit is configured by an amplifier connected in multiple stages.
- Each stage amplifier is composed of a linear amplifier whose gain varies depending on the operating current.
- the baseband circuit supplies information on the transmission mode and information on the number of multiplexed data to the amplifier circuit of the transmission unit.
- the amplifier circuit increases the operating current of the amplifier at the final stage to widen the dynamic range.
- the amplifier circuit decreases the gain by reducing the operating current of the amplifier at the previous stage or the first stage, and adjusts the distribution of the gain of the amplifier at each stage so that the gain is constant as the entire amplifier circuit.
- Patent Document 3 is a promising technique in terms of reducing power consumption, it is composed of a linear amplifier in which amplifier circuits are connected in multiple stages. Therefore, there is a problem in terms of noise characteristics. This is because if the amplifier circuit has a multi-stage configuration, the subsequent amplifier amplifies the noise of the amplifier in the previous stage, so that the noise characteristics of the entire amplifier circuit deteriorate. In the case of the high-speed communication mode in which the data transfer rate is higher than that in the normal mode, the noise characteristics are further deteriorated. In this case, the gain and dynamic range are increased by increasing the operating current of the last stage amplifier, and the gain is decreased by decreasing the operating current of the first stage amplifier. This is because the noise characteristics of the entire amplifier circuit are deteriorated.
- frequency division duplex In third generation (3G) mobile communication systems such as W-CDMA (Wideband Code Division Multiple Access) and UMTS (Universal Mobile Telecommunications System), frequency division duplex (FDD) is used for communication between a base station and a mobile station. Frequency Division Duplex) is used. For this reason, in the mobile station (cellular phone), the receiving unit and the transmitting unit operate simultaneously. Therefore, when the noise of the transmission unit is large, it is necessary to suppress the noise by providing a surface acoustic wave (SAW) filter or the like in the reception unit, resulting in an increase in cost.
- SAW surface acoustic wave
- An object of the present invention is to provide a semiconductor device for communication capable of adjusting the gain of an amplifier circuit and reducing power consumption in accordance with the PAPR of a transmission signal and having improved noise characteristics as compared with the prior art. is there.
- a semiconductor device includes a first amplifying unit, a digital / analog converting unit, a modulating unit, a second amplifying unit, and a control unit.
- the first amplification unit receives the first digital baseband signal and amplifies the first digital baseband signal with a first gain to generate a second digital baseband signal.
- the digital / analog conversion unit converts the second digital baseband signal into an analog baseband signal.
- the modulation unit generates a transmission signal by modulating the local oscillation signal with the analog baseband signal.
- the second amplifying unit amplifies the transmission signal with a variable second gain.
- the semiconductor device is capable of transmitting data according to a plurality of transmission modes, and the control unit receives information representing one of the transmission modes and adjusts the first gain according to the transmission mode.
- the gain and power consumption of the second amplifying unit are set to PAPR by providing the first amplifying unit before the digital / analog converting unit and adjusting the amplitude of the digital baseband signal.
- the noise characteristics can be improved as compared with the conventional case.
- FIG. 1 is a block diagram showing a configuration of a wireless communication system 1 according to an embodiment of the present invention. It is a block diagram which shows the specific structure of the front end module 12 of FIG. It is a wave form diagram of the transmission signal in each transmission system. It is a figure which shows an example of the gain characteristic of a transmission circuit. It is a figure which shows the relationship between the gain of RFPGA, and operating current.
- FIG. 2 is a block diagram illustrating detailed configurations of a transmission unit 22 and an HPA module 11 in FIG. 1. 2 is a diagram illustrating an example of a configuration of a DPGA 24.
- FIG. 2 is a diagram illustrating an example of a configuration of an RFPGA 35.
- FIG. 2 is a block diagram showing a configuration of an APC 36.
- FIG. It is a figure which shows typically the example of a certain one table stored in the gain setting part. It is a figure which shows typically the example of the table corresponding to the transmission mode different from FIG. 10 stored in the gain setting part 57.
- FIG. 11 is an example of a table corresponding to temperature information and frequency information different from those in FIG. 10 in the LTE mode or the HSUPA mode. In R99 mode, it is an example of the table corresponding to temperature information and frequency information different from FIG.
- FIG. 1 is a block diagram showing a configuration of a wireless communication system 1 according to an embodiment of the present invention.
- the wireless communication system 1 in FIG. 1 is built in a mobile phone.
- the radio communication system 1 includes an RFIC (Radio-Frequency Integrated Circuit) 10, a baseband IC (Integrated Circuit) 5, an HPA (High Power Amplifier) module 11, a matching circuit 16_1 to 16_n, and a front end.
- a module (FEM: Front End Module) 12 and an antenna 13 are included.
- the RFIC 10 is roughly divided into RF (Radio-Frequency) with a base station via an antenna in accordance with three transmission / reception system standards of “GSM / EDGE”, “WCDMA / HSPA”, and “LTE”.
- RF Radio-Frequency
- a one-chip transceiver IC communication semiconductor integrated circuit that enables transmission and reception of signals.
- GSM Global System for Mobile Communication
- 2G Second generation
- TDD Time Division Duplex
- TDMA Time Division Multiple Access
- EDGE Enhanced Data Rates for GSM Evolution
- 8PSK 8 phase shift keying: 8 Phase Shift Keying
- WCDMA Wideband Code Divided Multiple Access
- 3G Third generation
- UMTS Universal Mobile Telecommunications Systems
- HSPA High Speed Packet Access
- WCDMA Wideband Code Division Multiple Access
- LTE Long Term Evolution
- OFDMA Orthogonal Frequency Division Multiple Access
- SC-FDMA Single Carrier Frequency Division Multiple Access
- the RFIC 10 includes a reception unit (RX) 21, a transmission unit (TX) 22, and a digital RF interface (DigRF IF).
- RX reception unit
- TX transmission unit
- DIgRF IF digital RF interface
- the receiving unit 21 down-converts the received RF signal from the base station received by the antenna 13 into an analog reception baseband signal using a local carrier signal (local oscillation signal).
- the receiving unit 21 further performs analog-to-digital (AD) conversion on the analog reception baseband signal to generate a digital reception baseband signal.
- AD analog-to-digital
- the transmission unit 22 converts the digital transmission baseband signal by DA (Digital-to-Analog) conversion and transmits the analog transmission baseband signal, and uses the local carrier signal to transmit the analog transmission baseband signal to the transmission RF signal. Upconvert. Then, the transmission unit 22 wirelessly transmits a transmission RF signal to the base station via the antenna 13.
- DA Digital-to-Analog
- the digital RF interface 20 is an interface between the RFIC 10 and the baseband IC 5 and conforms to an interface standard established by MIPI Alliance (MIPI: Mobile Industry Processor Interface).
- the RFIC 10 further includes a plurality of output terminals Tx1 to Txn each outputting an RF signal and a plurality of input terminals Rx1 to Rxn each receiving an RF signal. (Tx1, Rx1), ..., (Txn, Rxn), the output terminal and the input terminal are paired, and the output terminal used according to the band (frequency band) in which the RFIC is used and The input terminal pair is determined.
- the baseband IC 5 performs digital demodulation and other signal processing corresponding to each of the three transmission / reception modes on the digital reception baseband signal received from the RFIC 10 to generate reception data (sound, image or other data). .
- the baseband IC 5 further performs digital modulation and other signal processing corresponding to each of the three transmission / reception modes on the transmission data (voice, image, or other data) to generate a digital transmission baseband signal and transfers it to the RFIC 10.
- the mobile phone on which the wireless communication system 1 is mounted has an application processor, a memory, a speaker, a microphone, an input key, and a liquid crystal monitor, each of which exchanges signals with the baseband IC 5. Do.
- HPA module The HPA module 11 has a plurality of HPAs (High Power Amplifiers) 40 provided corresponding to the output terminals Tx1 to Txn, respectively. Each HPA 40 amplifies the transmission RF signal received from the corresponding output terminal via the matching circuit. Each HPA 40 is composed of one semiconductor chip, and these are modularized in a package.
- the matching circuits 16_1 to 16_n are inserted between the output terminals Tx1 to Txn and the plurality of HPAs 40, respectively. In FIG. 2, the matching circuits 16_1 and 16_2 are externally attached to the RF-IC 10, but may be incorporated in the RF-IC 10.
- the front end module 12 selects one of the input / output terminal pairs (Rx1, Tx1) to (Rxn, Txn) and selects the selected input / output terminal pair (Rxi, Txi) (i is 1 or more and n or less) ) And the antenna 13 are connected.
- FIG. 2 is a block diagram showing a specific configuration of the front end module 12 of FIG. 1 and 2, the front-end module 12 includes an antenna switch (AT-SW) 15 and a plurality of duplexers (Rxn, Txn) corresponding to the input / output terminal pairs (Rx1, Tx1) to (Rxn, Txn).
- DPX DPX
- the antenna switch 15 selects one duplexer 14 according to the frequency band to be used, and connects the selected duplexer 14 and the antenna 13.
- the selected duplexer 14 transmits the transmission RF signal from the corresponding output terminal Txi (i is an integer of 1 to n) to the antenna 13 and simultaneously transmits the reception RF signal from the antenna 13 to the corresponding input terminal Rxi. To do.
- the duplexer 14 suppresses the transmission RF signal from leaking to the input terminal Rxi and suppresses the reception RF signal from leaking to the output terminal Txi.
- the FDD scheme is realized for transmission and reception with the base station.
- Each of the antenna switch 15 and the plurality of duplexers 14_1 to 14_n is composed of one semiconductor chip, and these are modularized in one package.
- the transmission unit 22 described with reference to FIG. 1 includes a circuit portion that performs 2G-based GSM / EDGE transmission and a circuit portion that performs transmission in three 3G-based transmission schemes (transmission modes).
- the 3G-based transmission scheme is specifically as follows, and the modulation scheme, multiplexing scheme, and multiple access scheme are different.
- multiplexing method refers to a method of multiplexing and transmitting a plurality of information (data) transmitted by one user
- multiple access refers to information transmitted by each of a plurality of users in different locations
- Data refers to a method of multiplexing and transmitting.
- R99 WCDMA normal mode
- modulation method is QPSK (Quadrature Phase Shift Keying)
- multiplexing method is CDM (Code Division Multiplexing)
- multiple access method is CDMA. is there.
- HSUPA High Speed Uplink Packet Access
- QPSK Quadrature Phase Shift Keying
- 16QAM 16 Quadrature Amplitude Modulation Either one is used.
- 16QAM can carry 4 bits (16 values) of information per symbol, and has a transmission rate twice that of QPSK.
- the multiplexing method is CDM, and the multiple access method is CDMA.
- LTE QPSK, 16QAM, or 64QAM is used depending on the radio wave condition.
- the multiplexing method is SC-FDE (Single Carrier Frequency Domain Equalization), and the multiple access method is SC-FDMA.
- FIG. 3 is a waveform diagram of a transmission signal in each transmission method.
- 3A shows an example of a transmission waveform for R99
- FIG. 3B shows an example of a transmission waveform for HSUPA
- FIG. 3C shows an example of a transmission waveform for LTE.
- HSUPA and LTE indicate a case where the modulation scheme is 16QAM.
- 3A to 3C the positions of the average voltage ave and the peak value pk are indicated by broken lines.
- the peak-to-average power ratio (PAPR) of the transmission signal increases / decreases depending on the modulation method and the number of multiplexing.
- the PAPR of the transmission signal also changes depending on the number of allocated RBs (Resource Blocks).
- the PAPR of the transmission signal is about 3 dB, but in the case of HSPA, the PAPR of the transmission signal is increased to about 7.5 dB.
- the PAPR of the transmission signal increases to about 8.5 dB.
- FIG. 4 is a diagram illustrating an example of gain characteristics of the transmission circuit.
- P1 dB (1 dB compression point: 1 dB gain compression point)
- IP1 dB Input P1 dB
- OP1 dB Output P1 dB
- P1 dB is usually evaluated by a CW (Continuous wave) wave.
- the block that consumes the largest current in the transmission unit is an RF amplifier circuit in the output stage of the RF unit, and a higher operating current is required because higher linearity is required in the later stage.
- the current consumption of an RF variable gain amplifier (PGA) is large because the transmission power control range is wide.
- FIG. 5 is a diagram showing the relationship between the gain of the RFPGA and the operating current.
- an RFPGA in order to change the gain by linear-in-dB, it is necessary to increase the operating current exponentially with respect to the gain. For example, in FIG. 5, the current consumption is doubled when the gain is increased by 6 dB.
- the power consumption of the amplifier circuit can be reduced and the noise characteristics can be improved.
- FIG. 6 is a block diagram showing a detailed configuration of the transmission unit 22 and the HPA module 11 of FIG.
- the transmission unit 22 receives the digital transmission baseband signal generated by the baseband IC 5 of FIG. 1 according to each transmission mode via the digital RF interface 20 of FIG.
- the transmission unit 22 up-converts the received digital transmission baseband signal by a direct conversion method to generate an RF signal.
- the transmission unit 22 can generate RF signals in a plurality of frequency bands in the range of 800 MHz to 2.5 GHz.
- the frequency band (band) is determined by the standard, and “Band 1”, “Band 2”, and “Band 7” are typically used. “Band 1” is the 1920 MHz-1980 MHz band, “Band 2” is the 1850 MHz to 1910 MHz band, and “Band 7” is the 2500 MHz to 2570 MHz band.
- the transmission unit 22 includes a multiplexer (MPX) 23, two digital programmable gain amplifiers (DPGA) 24_1, 24_2, two adders 38_1, 38_2, and 2
- MPX multiplexer
- DPGA digital programmable gain amplifier
- LPF low-pass filter
- APC auto power controller
- the analog baseband circuit 27 is configured by the DAC 25 (25_1, 25_2) and the low-pass filter 26 (26_1, 26_2).
- the digital transmission baseband signal (transmission data) received from the baseband IC 5 via the digital RF interface 20 is 1-bit data in which an in-phase component signal (I signal) and a quadrature component signal (Q signal) are serially transferred. A signal is included.
- the digital transmission baseband signal further includes a 1-bit clock signal that synchronizes the 1-bit data signal and a 1-bit enable signal that permits data capture. .
- the multiplexer 23 separates (multiplexes) the serially transferred I signal and Q signal and converts each of the serial I signal and Q signal into a parallel signal (I signal I_d1, Q signal Q_d1) composed of a plurality of bits. To do.
- the DPGAs 24_1 and 24_2 are amplifiers having variable gains.
- the DPGA 24_1 amplifies the I signal I_d1, which is a parallel digital signal, by digital processing. That is, the DPGA 24_1 converts the value of the I signal I_d1 into a value obtained by multiplying the I signal I_d1 by a gain.
- the DPGA 24_2 amplifies the Q signal Q_d1, which is a parallel digital signal, by digital processing.
- the gain (also referred to as amplification factor) of each DPGA is adjusted based on the gain adjustment signal GCS1. At this time, the two DPGAs 24_1 and 24_2 are adjusted to have the same gain.
- the gain adjustment signal GCS1 is a signal for instructing to adjust the gain to 1 dB
- the gains of the two DPGAs 24_1 and 24_2 are both adjusted to 1 dB.
- the gain adjustment signal GCS1 is supplied from the APC 36.
- FIG. 7 is a diagram illustrating an example of the configuration of the DPGA 24.
- DPGA 24_1 is a digital multiplier that outputs a value obtained by multiplying I signal (digital signal) I_d1 from multiplexer 23 by gain adjustment signal GCS1 from APC.
- the DPGA 24_2 is a digital multiplier that outputs a value obtained by multiplying the Q signal (digital signal) Q_d1 from the multiplexer 23 by the gain adjustment signal GCS1 from the APC 36.
- the values multiplied by the DPGAs 24_1 and 24_2 become signals (digital signals) I_d2 and Q_d2 obtained by amplifying the I signal I_d1 and the Q signal Q_d1 with the gain set by the APC 36, and are sent to the analog baseband circuit 27 in the next stage.
- the DPGAs 24_1 and 24_2 are constituted by multipliers, but a lookup table may be used instead of the multipliers.
- values to be output values obtained by multiplying the values of the I signal I_d1 and the Q signal I_d1 by the gain
- the DPGA outputs signals I_d2 and Q_d2 obtained by multiplying the I signal I_d1 and the Q signal I_d1 by a gain by referring to the lookup table.
- the amplified digital I and Q signals output from DPGA 24_1 and 24_2 are input to adders 38_1 and 38_2 (also collectively referred to as adder 38).
- the adders 38_1 and 38_2 add a correction signal for correcting a DC offset output from a DC offset cancel circuit 37 described later to the digital I signal and Q signal.
- the DAC 25_1 converts the digital I signal output from the adder 38_1 into a differential analog signal.
- a frequency in a band higher than the cutoff frequency is removed by the low-pass filter 26_1.
- the DAC 25_2 converts the digital Q signal output from the adder 38_2 into a differential analog signal.
- the analog Q signal output from the DAC 25_2 has a frequency in a band higher than the cutoff frequency removed by the low-pass filter 26_2.
- the transmitter 22 further includes a plurality of local oscillators 30 (30_1, 30_2), a plurality of 1 ⁇ 2 dividers 31 (31_1, 31_2), a plurality of quadrature modulators 32 (32_1, 32_2), and a plurality of radio frequencies.
- a programmable gain amplifier (RFPGA) 35 35_1, 35_2) (in the case of generic designation or indicating an unspecified one, the local oscillator 30, the 1/2 frequency divider 31, the quadrature modulator 32) , And RFPGA35).
- the local oscillator 30, the 1/2 frequency divider 31, the quadrature modulator 32, and the RFPGA 35 are provided corresponding to the frequency bands (bands) of each transmission mode in principle, but in the case of close frequency bands. May be shared in different frequency bands. Although two elements are shown as representatives in FIG. 6, the number is not limited to two in practice.
- the local oscillator 30 generates a differential local oscillation signal LO (clock signals having the same frequency and a phase difference of 180 degrees) LO.
- the 1/2 divider 31 generates local oscillation signals LOI and LOQ obtained by dividing the frequency of the local oscillation signal LO by 1/2.
- the local oscillation signal LOI is synchronized with the rising edge of the original signal LO
- the local oscillation signal LOQ is synchronized with the falling edge of the original signal LO.
- the local oscillation signal LOQ becomes a signal obtained by shifting the local oscillation signal LOI by 90 degrees.
- the quadrature modulator 32 receives the local oscillation signals LOI and LOQ output from the corresponding 1/2 divider 31, and the analog I signal I_a and Q signal Q_a output from the low-pass filters 26_1 and 26_2.
- the quadrature modulator 32 performs analog modulation of the local oscillation signals LOI and LOQ with the I signal I_a and the Q signal Q_a, so that the I signal I_a and the Q signal Q_a are up-converted to the frequency of the local oscillation signals LOI and LOQ.
- a transmit RF signal is generated.
- the quadrature modulator 32 includes a mixer 33 that mixes the local oscillation signal LOI and the I signal I_a, and a mixer 34 that mixes the local oscillation signal LOQ and the Q signal Q_a.
- the outputs of the mixers 33 and 34 are added and output to the next-stage RFPGA 35 as a transmission RF signal.
- the quadrature modulator 32 for up-conversion is properly used according to the frequency band of the signal transmitted by RFIC.
- the example quadrature modulator 32_1 performs up-conversion to a high frequency band (Band 7) exceeding 2000 MHz, and the quadrature modulator 32_2 performs up-conversion to a plurality of frequency bands (for example, Band 1 and Band 2) below 2000 MHz. Shall.
- the plurality of quadrature modulators 32 operate exclusively. That is, while one quadrature modulator corresponding to the frequency band used by the RFIC is operating, the other quadrature modulators do not operate.
- the RFPGAs 35_1 and 35_2 are provided corresponding to the quadrature modulators 32_1 and 32_2, respectively.
- the RFPGA 35 is a variable gain amplifier that amplifies the transmission RF signal output from the corresponding quadrature modulator 32, and performs an amplification operation when the corresponding quadrature modulator 32 is operating. When one RFPGA corresponding to the frequency band used by the RFIC is operating, the other RFPGAs do not operate.
- the gain of the RFPGA 35 is adjusted based on a gain adjustment signal GCS2 from the APC 36.
- the transmission RF signal amplified by the RFPGA 35_1 is output from the output terminal Tx1, and is input to the corresponding HPA 40_1 through the matching circuit 16_1.
- the transmission RF signal amplified by the RFPGA 35_2 is output from the output terminal Tx2, and is input to the corresponding HPA 40_2 via the matching circuit 16_2.
- Each matching circuit matches the output impedance of the RFPGA and the input impedance of the HPA.
- FIG. 8 is a diagram illustrating an example of the configuration of the RFPGA 35.
- RFPGA 35 includes a resistance ladder 90, a current / voltage conversion unit 91, and a high frequency transformer circuit 94.
- the resistance ladder 90 divides the input voltage Vin input from the quadrature modulator 32.
- the resistance ladder 90 includes a plurality of resistance elements connected in a network. As shown in FIG. 8, one resistive element is provided between adjacent nodes of nodes P0 to P13 and between adjacent nodes of nodes N0 to N13. Between each of the nodes P1 to P12 and N1 to N12 and the virtual AC ground line 80, two resistance elements connected in series are provided. Two resistance elements connected in series are provided between each of the nodes P0, P13, N0, and N13 and the virtual AC ground line 80, and further connected in series with the series body of the two resistance elements. Two resistance elements are provided. The resistance value of each resistance element is R. The input voltage Vin is applied between the nodes P13 and N13.
- the voltage between the nodes Pi and Ni (where i is an integer of 0 or more and 12 or less) becomes a voltage 1/2 between the adjacent nodes Pi + 1 and Ni + 1. Therefore, the voltage between the nodes Pi and Ni (where i is an integer not less than 0 and not more than 12) is equal to a value obtained by dividing the input voltage Vin by 2 to the (13-i) power.
- the current / voltage conversion unit 91 includes 18 transconductance amplifiers TA0 to TA17 (when generically referred to or unspecified, they are described as transconductance amplifiers TA).
- the transconductance amplifier TA0 receives a voltage obtained by dividing the voltage between the nodes P0 and N0 by a resistance element.
- a voltage obtained by dividing the voltage between the nodes Pi and Ni by 1/2 is input to the transconductance amplifier TAi (where i is an integer of 0 to 13). Therefore, the voltage input to the transconductance amplifier TAi (where i is an integer from 0 to 13) is equal to a value obtained by dividing the input voltage Vin by 2 to the power of (14 ⁇ i).
- the input voltage Vin is input to the transconductance amplifiers TA14 to TA17.
- Each of the transconductance amplifiers TA0 to TA17 converts the input voltage into a current and supplies it to the output signal line 92.
- the transconductance amplifiers TA0 to TA14 have the same transconductance gm.
- the transconductances of the transconductance amplifiers TA15 to TA17 have 2 gm, 4 gm, and 8 gm, respectively.
- the operations of the transconductance amplifiers TA0 to TA17 are controlled by control words WC ⁇ 0> to WC ⁇ 17>, respectively.
- Control words WC ⁇ 0> to WC ⁇ 17> correspond to each bit of gain adjustment signal GCS2 which is a multi-bit parallel signal.
- Each transconductance amplifier TA outputs a current corresponding to the input voltage to the output signal line 92 when the corresponding control word is “1”, and outputs a current to the output signal line 92 when the corresponding control word is “0”. Is not output.
- the output signals of the transconductance amplifiers TA0 to TA17 are transmitted to the output terminal Txj (j is an integer between 1 and n) in FIG.
- the high-frequency transformer circuit 94 separates DC components of output signals from the transconductance amplifiers TA0 to TA17 and performs impedance conversion.
- the gain can be adjusted in the range of ⁇ 66 dB to 12 dB in 0.125 dB steps.
- the transconductance gm is set so that the gain of the RFPGA 25 becomes 0 dB.
- the maximum gain of 12 dB is realized when the upper 8 bits of the control word, that is, each of WC ⁇ 17> to WC ⁇ 10> is “1” and the other bits are “0”.
- the minimum gain of ⁇ 66 dB is realized when only WC ⁇ 5> is “1” and the other bits are “0”.
- transmission unit 22 further includes a DC offset cancel circuit 37.
- the DC offset cancel circuit 37 prevents a carrier signal leakage (referred to as carrier leak) that occurs in the quadrature modulators 32_1 and 32_2, that is, a baseband input to the quadrature modulator 32 that causes the carrier leak. It is provided to cancel the difference (offset) in the DC level between the differential signals. Specifically, the DC offset cancel circuit 37 calculates the correction amount using the outputs from the quadrature modulators 32_1 and 32_2 and the local carrier signals LOI and LOQ from the frequency dividers 31_1 and 31_2.
- the DC offset cancel circuit 37 calculates a correction amount that reduces the DC level offset between the differential signals, and supplies the calculated correction amount to the adders 38_1 and 38_2.
- the adders 38_1 and 38_2 add the calculation results of the DC offset cancel circuit 37 to the digital baseband signals output from the two DPGAs 24_1 and 24_2, and output the corrected digital baseband signals.
- a specific configuration of the DC offset cancel circuit 37 is described in, for example, Japanese Patent Application No. 2009-281360.
- FIG. 6 shows the configuration of the HPA module 11 connected to the output terminals Tx1 and Tx2 among the output terminals Tx1 to Txn shown in FIG. 1 via the matching circuits 16_1 and 16_2.
- the HPAs 40_1 and 40_2 are high power amplifiers (HPAs) for amplifying RF signals output from the output terminals Tx1 and Tx2, respectively, and having a variable gain.
- HPAs high power amplifiers
- the quadrature modulator 32 and the RFPGA 35 corresponding to the frequency band used by the RFIC are operating, the HPA corresponding to the frequency band performs an amplification operation, and other HPAs do not operate.
- the transmission RF signal amplified by the HPAs 40_1 and 40_2 is sent to the front end module 12.
- the HPA module 11 further includes a coupler 41 and a detector (DET) 42 provided corresponding to the HPA 40, a switch (SW) 43, and a DC-DC converter 44.
- FIG. 6 shows couplers 41_1 and 41_2 corresponding to the HPAs 40_1 and 41_2, and detectors 42_1 and 42_2 respectively corresponding to the couplers 41_1 and 41_2.
- the coupler 41 detects the RF signal output from the corresponding HPA 40.
- the detector 42 detects the output waveform of the corresponding coupler 41. As a result, the output power of the corresponding HPA 40 is detected by the detector 42.
- As the detector 42 for example, a diode detector is used.
- the switch 43 selects the output of the detector 42 corresponding to the HPA 40 performing the amplification operation from among the plurality of detectors 42, and feeds back the selected output to the transmission unit 22 as the control signal CS2.
- the DC-DC converter 44 converts the voltage level of the gain adjustment signal GCS3 output from the APC 36 and supplies it to each HPA 40.
- the gain of the HPA 40 is adjusted by the gain adjustment signal GCS3.
- the transmission power of each mobile station is adjusted so that the received power at the base station is equal.
- the base station instructs the mobile station to increase the transmission power when the mobile station is far from the base station and to decrease the transmission power when the mobile station is close to the base station. That is, the base station transmits to the mobile station any command of “increase transmission power”, “decrease transmission power”, or “do not increase / decrease transmission power”.
- this command is referred to as “transmission power information”.
- the transmission power amount that the mobile station increases / decreases in response to one command is determined in advance, for example, increasing / decreasing by 0.5 dB, increasing / decreasing by 1 dB, and increasing / decreasing by 2 dB.
- the transmission power information is transmitted from the base station to each mobile station (cellular phone) every 500 ⁇ s in the LTE mode and every 667 ⁇ s in the R99 mode and the HSUPA mode.
- a control channel in addition to a data channel for transmitting and receiving call data and other various data.
- Various control information including transmission power information transmitted from the base station is received by the mobile station via the control channel.
- the various control information received is down-converted by the RFIC 10 and then decoded (demodulated) by the baseband IC 5.
- Transmission power information obtained as a result of demodulation is sent from the baseband IC 5 to the APC 36 of the transmission unit 22 via the digital RF interface 20. Accordingly, the transmission power information received by the APC 36 from the baseband IC 5 is a digital signal that identifies “power increase”, “no increase / decrease”, and “power decrease”.
- the APC 36 provided in the transmission unit 22 of the RFIC 10 receives a control signal CS1 including transmission power information.
- Control signal CS1 includes temperature information, frequency information, transmission mode information, and the like in addition to transmission power information.
- the APC 36 further receives the control signal CS2 output from the detector 42.
- the APC 36 adjusts the gains of the DPGA 24, the RFPGA 35, and the HPA 40 for each specified time set in each transmission mode based on the control signals CS1 and CS2.
- the control based on the control signals CS1 and CS2 will be specifically described.
- FIG. 9 is a block diagram showing the configuration of the APC 36.
- the APC 36 includes first and second registers 50 and 51, an adder 49, a gain setting unit 57, a gain control logic circuit 58, and a digital / analog converter. (DAC) 59.
- DAC digital / analog converter.
- the first register 50 holds the currently set antenna transmission power value. Specifically, the set value of the transmission power is held in the input code format shown in FIGS.
- the adder 49 receives the transmission power information from the baseband IC 5 and performs an addition operation with the set value held in the first register 50 to generate a transmission power value to be newly set.
- the value of the first register 50 is updated every predetermined time (every 500 ⁇ s in the LTE mode, every 667 ⁇ s in the HSPHA mode and the R99 mode) according to the set value of the transmission power output from the adder 49.
- the second register 51 holds the set value of the antenna transmission power transferred from the first register 50.
- the updated transmission power setting value is transferred to the second register 51 as it is.
- the value held in the first register 50 may be transferred to the second register 51 via adders 52 and 53 described later. In this case, at the time of transfer, the other input of the adders 52 and 53 becomes zero.
- the gain setting unit 57 includes, for example, an SRAM (Static Random Access Memory).
- SRAM Static Random Access Memory
- the SRAM stores control data of the DPGA 24, the RFPGA 35, and the HPA 40 that should be set in accordance with the value of the antenna transmission power as a look-up table (LUT).
- LUT look-up table
- a CPU not shown
- a nonvolatile memory may be used instead of the SRAM. If it is a non-volatile memory, the writing process at the time of power-on becomes unnecessary.
- the lookup table consists of multiple tables.
- the gain setting unit 57 specifies one table based on the temperature information, frequency information, and transmission mode information included in the control signal CS1.
- the gain setting unit 57 receives the set value of the transmission power of the antenna held in the second register 51 as an address signal, and transmits the antenna transmission among a plurality of control data held in one specified table. Outputs the control data specified by the power setting value.
- the control code output from the gain setting unit 57 is converted into a control signal code for adjusting the gains of the DPGA 24, the RFPGA 35, and the HPA 40 by the gain control logic circuit 58, and the DPGA 24, the RFPGA 35, and the gain adjustment signals GCS1, GCS2, and GCS3. Each is output to the HPA 40.
- the gain adjustment signal GCS3 is converted to an analog signal by the DAC 59, and then the voltage level is converted by the DC-DC converter 44 before being output to the HPA 40.
- FIG. 10 is a diagram schematically illustrating an example of a single table stored in the gain setting unit 57.
- the gain [dB] of the DPGA 24, the RFPGA 35, and the HPA 40 is related to the transmission power [dBm] of the antenna.
- power attenuation on the path from the DPGA 24 to the RFPGA 35 and the path from the HPA 40 to the antenna is also related, but in the following description, power attenuation on these paths is ignored for the sake of simplicity.
- Vbb ⁇ 13.01 [dBV]
- the antenna transmission power (HPA 40 output power) can be set in a range of ⁇ 50 dB to 23.875 dB with a total of 592 points for each 0.125 dB step.
- the input code in the table has a value of 592 points from H'000 to H'24F corresponding to the setting value of the transmission power of the antenna ("H '" represents hexadecimal notation).
- a control code is set corresponding to each input code.
- the control code is information for specifying a gain (dB) value to be set in each of the DPGA 24, the RFPGA 35, and the HPA 40.
- the gain setting unit 57 Upon receiving the transmission power setting value from the second register 51, the gain setting unit 57 outputs a control code corresponding to the transmission power setting value.
- the gains of DPGA 24, RFPGA 35, and HPA 40 are set to 0 dB, ⁇ 50 dB, and 0 dB, respectively.
- the gain of the HPA 40 is adjusted so as to increase especially when the antenna requires high output transmission power.
- the gain is fixed at 0 dB, and the gain is adjusted from a level 20 to 30 dBm lower than the upper limit (23.875 dBm) of the set transmission power.
- the input code from H'000 to H'18F (400 steps) is fixed to 0 dB, and from H'190 to H'1CF (64 steps) is set to 5 dB.
- From H′1D0 to H′20F (64 steps) is set to 10 dB.
- H'210 to H'24F (64 steps) are set to 15 dB.
- the gain of the RFPGA 35 is set to ⁇ 50 dB when the input code is H′000. From H′000 to H′18F, the input code value increases by 2 dB every 16 steps, and at H′18F, it is set to ⁇ 2.0 dB. When H'190 is reached, it is reduced by 3 dB and set to -5.0 dB. From H′190 to H′1CF, the input code value is increased by 2 dB every 16 steps, and H′1CF is set to 1.0 dB. When H'1D0 is reached, it is reduced by 3 dB and set to -2.0 dB.
- H′24F is set to 7.0 dB. That is, in H′000 to H′24F, the total value of the gains of RFPGA 35 and HPA 40 (the gain of the output voltage of HPA 40 as seen from the input voltage of RFPGA 35) is ⁇ 50 dB (H′000) to 22 dB (H′24F). In this range, the input code value increases by 2 dB steps every 16 steps.
- the gain of DPGA 24 varies in the range of 0 dB to 1.875 dB.
- the gain of the DPGA 24 increases by 0.125 dB every time the input code increases by one step, returns to 0 dB after 1.875 dB, and increases again by 0.125 dB. Accordingly, the gain of DPGA 24 repeats from 0 dB to 1.875 dB every 16 steps as an input code value.
- the gain of the DPGA 24 is adjusted in steps of 0.125 dB
- the gain of the RFPGA 32 is adjusted in steps larger than the DPGA 24 (2.000 dB)
- the gain of the HPA 40 is further increased in steps of 5.000 dB (5.000 dB). It is adjusted with. That is, the upper value (part of 2 dB or more) of the transmission power of the antenna is adjusted by the gain of the HPA 40 and the RFPGA 32, and the lower value (part of 0.000 dB to 1.875 dB) is adjusted by the gain of the DPGA 24. .
- the RFPGA 32 and the HPA 40 are configured by analog circuits, and for example, it is difficult to adjust the gain with a fine step of less than 0.5 dB with high accuracy, and a complicated circuit configuration is required to adjust the gain with high accuracy. To grow.
- amplification by the DPGA 24 is realized by digital calculation, so that the gain can be adjusted accurately with little influence of noise even in a fine step.
- Amplifying operation in a range where high transmission power exceeding 0 dBm is required requires a considerable current, so that the gain is adjusted in cooperation with the HPA 40 of a chip different from the RFIC 10 instead of the RFPGA 32 alone. It is desirable.
- Control based on control signal CS2 Regarding the transmission power of the antenna, there is often an error between the designed value (the value held in the first register 50 in FIG. 9) and the actual transmission value. This is because it is difficult to set the gains as designed in the RFPGA 32 and the HPA 40 which are analog circuits.
- the APC 36 has a mechanism for adjusting the gain by receiving feedback of a signal (control signal CS2) obtained by detecting the output of the operating HPA 40 by the detector 42. .
- APC 36 further includes a low-pass filter 54, an AD converter (ADC) 55, an integrator 56, and adders 52 and 53.
- ADC AD converter
- the input control signal CS2 is converted into a digital signal by the AD converter 55 after the high frequency exceeding the cutoff frequency is removed by the low-pass filter 54.
- the output signal of the AD converter 55 represents the transmission power of the HPA 40.
- the integrator 56 calculates the average power within a predetermined time based on the plurality of digital values sampled by the AD converter 55.
- the adder 52 calculates the difference between the set value of the antenna transmission power held in the first register 50 and the actual transmission power output by the integrator 56. This difference indicates an error between the designed output power and the actual output power.
- the adder 53 adds the error output from the adder 52 to the set value of the antenna transmission power held in the second register 51, and rewrites the second register 51 with the addition result.
- the gains of the DPGA 24, the RFPGA 32, and the HPA 40 are adjusted again with the rewritten setting value of the transmission power of the new antenna.
- the error is adjusted by repeating this feedback control within a predetermined time (within 500 ⁇ s in the LTE mode and within 667 ⁇ s in the R99 mode and the HSUPA mode).
- the actual output power of the HPA 40 is adjusted to the transmission power value to be set held in the first register 50.
- the first register 50 holds the value as it is.
- This feedback control may be performed particularly at a high output where the power consumption is high, for example, at a high transmission power from a level 20 to 30 dB lower (0 dBm level) from the upper limit of the adjusted transmission power.
- the gain setting unit 57 of the APC 36 has different tables depending on the transmission mode. Specifically, a table is prepared in which the gain value of the DPGA 24 is changed according to the transmission mode.
- the gain setting unit 57 receives transmission mode information specifying the transmission mode from the baseband IC, and selects a table corresponding to the transmission mode information.
- transmission mode information specifying the transmission mode from the baseband IC
- FIG. 11 is a diagram schematically illustrating an example of a table stored in the gain setting unit 57 and corresponding to a transmission mode different from that in FIG.
- FIG. 10 is an example of a table when transmitting in LTE mode and HSUPA mode
- FIG. 11 is an example of a table when transmitting in R99 mode.
- the gain of the DPGA 24 for each input code is 2 dB larger and the gain of the RFPGA is 2 dB smaller than the table of FIG. That is, in the case of the table of FIG. 11, the gain of the DPGA 24 changes in the range of 2 dB to 3.875 dB with 0.125 dB as one step. Since the gain value of the HPA 40 in FIG. 11 is the same as that in FIG. 10, the value of the transmission power for the input code does not change between FIG. 10 and FIG.
- the example of FIGS. 10 and 11 is generalized as follows.
- the gain range [dB] set in the LTE mode and the HSUPA mode is G1min to G1max (G1min is the lower limit of the range and G1max is the upper limit of the range), and the width of the step is ⁇ 1 [dB].
- the gain range [dB] set in the R99 mode with a smaller PAPR than in the LTE mode and the HSUPA mode is G2min to G2max (G2min is the lower limit of the range and G2max is the upper limit of the range), and the step width is Let ⁇ 2 [dB].
- the gain is set so that further, G1max ⁇ G2min (3)
- the gain of the DPGA 24 increases as the PAPR of the digital transmission baseband signals I_d1, Q_d1 decreases.
- the peak amplitude of the analog transmission baseband signal output from the DAC 25 is controlled to be as constant as possible.
- the increase / decrease of the gain of the DPGA 24 is adjusted by the gain of the RFPGA 35, and is controlled so that the transmission power from the antenna becomes constant.
- the gain of the DPGA 24 is increased and the gain of the RFPGA 35 is decreased. As a result, even when transmitting a high PAPR signal in a mode capable of high-speed communication, it can be transmitted without distortion.
- the gain of the RFPGA which consumes more current than DPGA, can be reduced, so that the current consumption can be suppressed and the battery of the portable terminal can be saved.
- the linearity of the analog baseband circuit 27 such as the DAC 25 and the low-pass filter 26 is mainly determined by the power supply voltage and the circuit configuration, there is no problem even if the signal amplitude increases.
- the size of the PAPR value depends on the modulation method, the multiplexing method, and the multiple access method, in principle, it depends on at least one of the modulation method, the multiplexing method, and the multiple access method. It can be said that the above merits can be realized by adjusting the gains of DPGA and RFPGA.
- the baseband IC 5 that performs modulation and multiplexing processing generates information indicating at least one of the modulation method, the multiplexing method, and the multiple access method
- the RFIC receives the information and adjusts the gains of the DPGA and the RFPGA, respectively.
- the structure to do may be sufficient.
- the PAPR value differs between a plurality of transmission modes in which at least one of a modulation scheme, a multiplexing scheme, and a multiple access scheme is different, such as LTE, HSUPA, and R99.
- the baseband IC 5 generates information representing one of the modes, and the RFIC receives the information and adjusts the gains of the DPGA and the RFPGA more simply.
- the dynamic range of the DAC 25 can be maximally utilized by adjusting the amplitudes of the digital transmission baseband signals I_d1 and Q_d1 by the DPGA 24. Therefore, the noise characteristics of the output of the DAC 25 (That is, CNR: Carrier-to-Noise Ratio) can be improved. Furthermore, noise characteristics from the DAC 25 to the RFPGA 35 can be improved by increasing the amplitude of the output signal from the DAC 25.
- the DPGA 24 is configured to perform fine adjustment of power control (that is, to adjust the lower digit of the power value to be set). Since the DPGA 24 is a digital process, the power control can be performed with high accuracy with little variation. For example, since the RFPGA is an analog process, the variation becomes large, and the area of the RFPGA becomes large if the variation is suppressed.
- the antenna output power control is realized by adjusting the gain of the DPGA 24 and the RFPGA.
- carrier leakage can be reduced as compared with the RFIC described in JP 2007-5996 A (Patent Document 3).
- the RFPGA is composed of a plurality of amplifiers
- the operating point is changed when the gain of the amplifier in the previous stage is changed, so that the DC offset that causes carrier leakage changes.
- the gain of the DPGA 24 since the gain of the DPGA 24 is adjusted, carrier leak does not increase.
- the gain of the DPGA 24 in the LTE mode and the HSUPA mode is controlled to change within the same range (0 dB to 1.875 dB). Further, the gain change of the DPGA 24 may be different between the LTE mode and the HSUPA mode. Considering that the PAPR in the HSUPA mode is smaller than that in the LTE mode and larger than that in the R99 mode, the minimum and maximum gains of the DPGA 24 in the HSUPA mode are larger than those in the LTE mode and are larger than those in the R99 mode. It may be made smaller.
- the gain range of the DPGA 24 in the HSUPA mode may be 1 dB to 2.875 dB. In that case, it is necessary to readjust the gain setting value of the RFPGA 24 for the input code to a value different from that in FIG.
- control is performed so that the gain of the DPGA 24 changes within a certain range.
- the gain of the DPGA 24 is set to 0 dB in the LTE mode and the HSUPA mode, and the gain of the DPGA 24 is set to 2 dB in the R99 mode so that the gain of the DPGA 24 is set to 2 dB. It may be fixed to. In this case, it is necessary to adjust the gain of the RFPGA 35 in 0.125 dB steps. However, if the RFPGA 35 having the configuration described in FIG. 8 is used, the gain can be adjusted in 0.125 dB steps. However, adjusting the fine steps with the DPGA 24 can reduce the influence of noise and perform gain adjustment with high accuracy.
- the RFIC 10 of the first embodiment has a mechanism for optimally setting the gains of the RFPGA 35 and the HPA 40 according to the environment in which the mobile phone is used. Typical parameters of the usage environment include frequency and temperature.
- the gain characteristic of the output voltage with respect to the input voltage changes according to the frequency and temperature in use. For example, since the HPA gain decreases as the temperature rises, it is necessary to compensate for the decrease in the HPA gain by increasing the set values of the gains of the RFPGA and DPGA. In particular, rough correction for the gain change of the HPA is adjusted by increasing or decreasing the gain of the RFPGA, and fine correction is adjusted by increasing or decreasing the gain of the DPGA. That is, instead of uniquely setting the gains of the RFPGA 35 and the HPA 40 with respect to the set value of the transmission power, it is desirable to change the distribution of gains between the RFPGA 35 and the HPA 40 according to the frequency and temperature.
- the frequency information is information that specifies the frequency of the carrier that the mobile phone uses at the time of actual transmission, that is, the frequency of the local oscillation signal that the quadrature modulator 32 uses for modulation.
- This frequency information is a signal generated in the RFIC based on information from the baseband IC 5, but is also used for control information for setting the frequencies of the local oscillation signals LOI and LOQ input to the quadrature modulator 32. Is done.
- the temperature information is information for specifying the temperature of the RFIC 10 being used. Specifically, the temperature range (eg, -40 ° C to 90 ° C) that guarantees the operation of the RFIC is divided into multiple subranges (eg, 6 subranges in 25 ° C steps), and the temperature range of the RFIC is specified. Information.
- a temperature measurement circuit (not shown) configured by a transistor is provided in the RFIC 10, and temperature information is generated in the RFIC 10 based on the measurement result.
- FIG. 12 is an example of a table corresponding to temperature information and frequency information different from those in FIG. 10 in the LTE mode or the HSUPA mode.
- the DPGA gain range (0 dB to 1.875 dB) is the same as in FIG. 10, but the DPGA corresponding to the input code. Is different from that in FIG.
- the gain of DPGA is 0.750 dB, 0.875 dB, 1.000 dB,..., 1.875 dB, 0.000 dB, 0.125 dB,. It is set to repeat 500 dB and 0.625 dB.
- the gain of the RFPGA is ⁇ 51.0 dB with the input code H′000, and thereafter, the input code increases by 2 dB with H ′ ** A (** is an arbitrary value). Also, when moving from H'18F to H'190, when moving from H'1CF to H'1D0, and when moving from H'20F to H'210, the value increases by 5 dB.
- Such tables are prepared for the number of conditions specified by the frequency information and temperature information (for example, 1000 to 2000).
- FIG. 13 is an example of a table corresponding to temperature information and frequency information different from FIG. 11 in the R99 mode.
- the DPGA gain range (0 dB to 1.875 dB) is the same as that of FIG.
- the value of the gain of DPGA corresponding to is different from that in FIG.
- the gain of DPGA is 2.500 dB, 2.625 dB, 2.750 dB, ..., 3.875 dB, 2.000 dB, 2.125 dB, 2.250 dB, and 2 every 16 steps from the input code H'000. It is set to repeat 375 dB.
- the gain of the RFPGA is ⁇ 51.5 dB with the input code H′000, and thereafter, the input code increases by 2 dB with H ′ ** E (** is an arbitrary value). Also, when moving from H'18F to H'190, when moving from H'1CF to H'1D0, and when moving from H'20F to H'210, the value increases by 5 dB.
- Such tables are prepared for the number of conditions specified by the frequency information and temperature information (for example, 1000 to 2000).
- the table may be appropriately set based on the information related to the parameter.
- the table may be appropriately set based on the information related to the parameter.
- only two tables corresponding to the transmission mode information (for example, the tables in FIGS. 10 and 11) may be prepared.
- FIG. 14 is a block diagram showing a configuration of transmitting section 122 according to Embodiment 2 of the present invention.
- the local oscillators 130_1 and 130_2 in FIG. 14 are different from the local oscillators 30_1 and 30_2 in FIG. 6 in that the magnitude of the drive current that flows during operation can be adjusted according to the current adjustment signals CCS1 and CCS3, respectively.
- the 1/2 dividers 131_1 and 131_2 in FIG. 14 can adjust the magnitude of the drive current that flows during operation according to the current adjustment signals CCS2 and CCS4, respectively, and the 1/2 dividers 31_1 and 31_2 in FIG. And different.
- FIG. 14 generates and outputs current adjustment signals CCS1 to CCS4 corresponding to the transmission mode information in addition to the function of APC 36 in FIG.
- the other points in FIG. 14 are the same as those in FIG. 6, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.
- the noise characteristics are improved by increasing the gain of the DPGA 24. For this reason, there may be a margin in the noise characteristic margin in the R99 mode. In that case, the amount of drive current that flows during the operation of the local oscillator 130 and the 1/2 frequency divider 131 can be reduced to such an extent that a noise characteristic margin can be obtained, and power consumption can be reduced.
- the current adjustment signals CCS1 to CCS4 are not limited to 1 bit but may be multi-bit signals.
- the drive current can be adjusted in multiple steps according to the multi-bit current adjustment signals CCS1 to CCS4.
- Baseband IC 10 RFIC, 11 HPA module, 12 Front-end module, 13 Antenna, 20 Digital RF interface, 21 Receiver, 22, 122 Transmitter, 24 DPGA, 25 DAC, 30, 130 Local oscillator, 31, 131 1/2 divider, 32 quadrature modulator, 35 RFPGA, 36,136 APC (auto power controller), 40 HPA.
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Abstract
Description
[無線通信システムの概略構成]
図1は、この発明の実施の形態による無線通信システム1の構成を示すブロック図である。図1の無線通信システム1は、携帯電話機に内蔵される。無線通信システム1は、RFIC(Radio-Frequency Integrated Circuit)10と、ベースバンドIC(Integrated Circuit)5と、HPA(High Power Amplifier:高出力増幅器)モジュール11と、整合回路16_1~16_nと、フロントエンドモジュール(FEM:Front End Module)12と、アンテナ13とを含む。
RFIC10は、大きく分けて“GSM/EDGE”、“WCDMA/HSPA”、および“LTE”の3つの送受信方式の規格に準拠して、アンテナを介して基地局との間でRF(Radio-Frequency)信号の送信および受信を可能とする1チップのトランシーバIC(通信用半導体集積回路)である。
ベースバンドIC5は、RFIC10から受け取ったデジタル受信ベースバンド信号に対して、上記3つの送受信モードそれぞれに対応したデジタル復調その他の信号処理を行い、受信データ(音声、画像またはその他のデータ)を生成する。ベースバンドIC5は、さらに、送信データ(音声、画像又はその他データ)に上記3つの送受信モードそれぞれに対応したデジタル変調その他の信号処理を行ってデジタル送信ベースバンド信号を生成し、RFIC10に転送する。図1には図示しないが無線通信システム1が搭載される携帯電話機は、アプリケーションプロセッサ、メモリ、スピーカ、マイクロホン、入力キー、液晶モニタを有し、それぞれがベースバンドIC5との間で信号のやりとりを行なう。
HPAモジュール11は、出力端子Tx1~Txnにそれぞれ対応して設けられた複数のHPA(高出力増幅器:High Power Amplifier)40を有する。各HPA40は、対応の出力端子から整合回路を介して受けとった送信RF信号を増幅する。各HPA40は1つ半導体チップで構成されており、これらはパッケージ内にモジュール化されている。整合回路16_1~16_nは、出力端子Tx1~Txnと複数のHPA40との間にそれぞれ挿入される。図2では、整合回路16_1,16_2はRF-IC10に外付けされているが、RF-IC10に内蔵することもできる。
フロントエンドモジュール12は、入力・出力端子ペア(Rx1,Tx1)~(Rxn,Txn)のうちの1組を選択し、選択した入力・出力端子ペア(Rxi,Txi)(iは1以上n以下の整数)と、アンテナ13とを接続する。
図1で説明した送信部22は、2GベースのGSM/EDGEの送信を行なう回路部分と、3Gベースの3つの送信方式(送信モード)の送信を行なう回路部分とを含む。3Gベースの送信方式は具体的に次のとおりであり、変調方式、多重化方式、多元接続方式がそれぞれ異なる。ここで「多重化方式」とは一つのユーザの送信する複数の情報(データ)を多重化して送信する方式を指し、「多元接続」はそれぞれ異なる場所にいる複数のユーザのそれぞれ送信する情報(データ)を多重化して送信する方式を指す。
図6は、図1の送信部22およびHPAモジュール11の詳細な構成を示すブロック図である。
デジタルRFインターフェース20を介してベースバンドIC5から受けたデジタル送信ベースバンド信号(送信データ)には、同相成分信号(I信号)と直交成分信号(Q信号)とがシリアル転送された1ビットのデータ信号が含まれる。この1ビットのデータ信号に付随して、デジタル送信ベースバンド信号には、1ビットのデータ信号が同期する1ビットのクロック信号と、データの取り込みを許可する1ビットのイネーブル信号とがさらに含まれる。
DPGA24_1,24_2(総称する場合、DPGA24とも称する)は、ゲイン(利得)が可変の増幅器である。DPGA24_1は、パラレルのデジタル信号であるI信号I_d1をデジタル処理によって増幅する。すなわち、DPGA24_1は、I信号I_d1にゲインを乗算した値にI信号I_d1の値を変換する。同様に、DPGA24_2は、パラレルのデジタル信号であるQ信号Q_d1をデジタル処理によって増幅する。各DPGAのゲイン(増幅率とも称する)は、ゲイン調整信号GCS1に基づいて調整される。このとき、2つのDPGA24_1,24_2の間では同じゲインとなるように調整される。たとえば、ゲイン調整信号GCS1がゲインを1dBに調整するように指示する信号である場合、2つのDPGA24_1,24_2のいずれのゲインも1dBに調整される。ゲイン調整信号GCS1は、APC36から供給される。
再び図6を参照して、DPGA24_1,24_2から出力された増幅後のデジタルのI信号、Q信号は加算器38_1,38_2(総称する場合、加算器38とも記載する)に入力される。加算器38_1,38_2はデジタルのI信号、Q信号に、後述するDCオフセットキャンセル回路37から出力されたDCオフセットを補正するための補正信号を加算する。
送信部22は、さらに、複数の局部発振器30(30_1,30_2)、複数の1/2分周器31(31_1,31_2)、複数の直交変調器32(32_1,32_2)、および複数の無線周波数プログラマブルゲインアンプ(RFPGA:Radio Frequency Programmable Gain Amplifier)35(35_1,35_2)を含む(総称する場合または不特定のものを示す場合に、局部発振器30、1/2分周器31、直交変調器32、およびRFPGA35と記載する)。局部発振器30、1/2分周器31、直交変調器32は、およびRFPGA35は、原則的には、各送信モードの周波数帯(バンド)に対応して設けられるが、近接した周波数帯の場合は異なる周波数帯で共用される場合もある。図6には各要素が代表として2個ずつ示されているが実際には2個に限られない。
RFPGA35_1,35_2は、直交変調器32_1,32_2にそれぞれ対応して設けられる。RFPGA35は、対応の直交変調器32から出力された送信RF信号を増幅するゲイン可変の増幅器であり、対応の直交変調器32が動作しているときに増幅動作を行なう。RFICが使用する周波数帯に対応する1つのRFPGAが動作しているときは、他のRFPGAは動作しない。RFPGA35のゲインはAPC36からのゲイン調整信号GCS2に基づいて調整される。RFPGA35_1によって増幅された送信RF信号は、出力端子Tx1から出力され、整合回路16_1を介して対応のHPA40_1に入力される。RFPGA35_2によって増幅された送信RF信号は、出力端子Tx2から出力され、整合回路16_2を介して対応のHPA40_2に入力される。各整合回路は、RFPGAの出力インピーダンスとHPAの入力インピーダンスとの整合をとる。
再び図6を参照して、送信部22は、さらに、DCオフセットキャンセル回路37を含む。DCオフセットキャンセル回路37は、直交変調器32_1,32_2に生じるキャリア信号の漏れ(キャリアリークと呼ばれている)を防ぐため、すなわち、キャリアリークの原因である直交変調器32に入力されるベースバンド信号の差動信号間でのDCレベルを相違(オフセット)をキャンセルするために設けられている。具体的には、DCオフセットキャンセル回路37は、直交変調器32_1,32_2からの出力および分周器31_1,31_2からのローカルキャリア信号LOI,LOQを使って補正量を演算する。DCオフセットキャンセル回路37は、差動信号間のDCレベルのオフセットを小さくするような補正量を算出し、算出した補正量を加算器38_1,38_2に供給する。加算器38_1,38_2は、2つのDPGA24_1,24_2の出力するデジタルベースバンド信号に、DCオフセットキャンセル回路37による演算結果を加算して補正後のデジタルベースバンド信号を出力する。DCオフセットキャンセル回路37の具体的な構成は、たとえば、特願2009-281360号に記載される。
図6には、図1に示す出力端子Tx1~Txnのうちの出力端子Tx1,Tx2と整合回路16_1,16_2を介して接続されたHPAモジュール11の構成が示される。HPA40_1,40_2は、それぞれ出力端子Tx1,Tx2から出力されるRF信号を増幅する、ゲインが可変の高出力増幅器(HPA:High Power Amplifier)である。RFICが使用する周波数帯に対応する直交変調器32およびRFPGA35が動作しているときに、その周波数帯に対応するHPAが増幅動作を行ない、他のHPAは動作しない。HPA40_1,40_2によって増幅された送信RF信号は、フロントエンドモジュール12に送られる。
(APCの動作の概要)
CDMA方式の場合のように複数の移動局(携帯電話機)が同一周波数の搬送波を使用する通信方式の場合には、基地局での受信電力が等しくなるように各移動局の送信電力を調整する必要がある。例えば、移動局が基地局から遠い位置にある場合には送信電力を上げ、移動局が基地局から近い位置にある場合には送信電力を下げるように基地局は移動局に対して指令する。すなわち、基地局は移動局に対して、「送信パワーを増加させる」、「送信パワーを減少させる」、および「送信パワーを増減しない」のいずれかの指令を送信する。以下、この指令を「送信パワー情報」と称する。1回の指令(送信パワー情報)に応答して移動局が増減する送信パワー量は、たとえば、0.5dBずつ増減、1dBずつ増減、2dBずつ増減のように予め決められている。送信パワー情報は、LTEモードのとき500μsごとに、R99モードおよびHSUPAモードのときに667μsごとに基地局から各移動局(携帯電話機)に送信される。
図9は、APC36の構成を示すブロック図である。図9を参照して、APC36は、第1および第2のレジスタ50,51と、加算器49と、ゲイン設定部57と、ゲイン制御ロジック回路(Gain control logic)58と、デジタル・アナログ変換器(DAC)59とを含む。
Pt=Gamp+Vbb+13.01 …(1)
と表わされる。図10~図13に示されるテーブルでは、簡単のために、Vbb=-13.01[dBV]としている。Vbbの値は、実際には、ベースバンドIC5の設計によって異なる。
H’000からH’18Fまでは、入力コード値で16ステップごとに2dBずつ増加し、H’18Fでは-2.0dBに設定される。H’190になると3dB減少して-5.0dBに設定される。H’190からH’1CFまでは、入力コード値で16ステップごとに2dBずつ増加し、H’1CFでは1.0dBに設定される。H’1D0になると3dB減少して-2.0dBに設定される。H’1D0からH’24Fまでは、入力コード値で16ステップごとに2dBずつ増加し、H’24Fでは7.0dBに設定される。すなわち、H’000~H’24Fにおいて、RFPGA35とHPA40とのゲインの合計値(RFPGA35の入力電圧からみたHPA40の出力電圧のゲイン)は、-50dB(H’000)~22dB(H’24F)の範囲で入力コード値で16ステップごとに2dBステップずつ増加することになる。
アンテナの送信パワーに関し、設計上の値(図9の第1のレジスタ50に保持される値)と実際の送信時の値とでは誤差が生じることが多い。この理由は、アナログ回路であるRFPGA32およびHPA40は、設計どおりのゲインに設定することが難しいからである。その誤差を調整するために、図9に示すように、APC36は、動作中のHPA40の出力を検波器42で検波した信号(制御信号CS2)のフィードバックを受けて、ゲインを調整する機構をもつ。
図9を参照して、APC36のゲイン設定部57には、送信モードに応じて異なるテーブルが用意されている。具体的には、送信モードに応じて、DPGA24のゲインの値を変更したテーブルが用意されている。ゲイン設定部57は、送信モードを特定する送信モード情報をベースバンドICから受け取り、送信モード情報に対応したテーブルを選択する。以下、具体例を挙げて説明する。
G1max<G2max,G1min<G2min …(2)
となるようにゲインが設定される。さらに、
G1max≦G2min …(3)
G1max-G1min=G2max-G2min …(4)
Δ1=Δ2 …(5)
であることが望ましい。図10、図11の例の場合は、G1min=0dB、G1max=1.875dB、G2min=2dB、G2max=3.875dB、Δ1=Δ2=0.125dBのように設定される。
実施の形態1のRFIC10は、携帯電話機が使用される環境に応じてRFPGA35およびHPA40のゲインを最適に設定するための機構をもつ。使用環境の典型的なパラメータとして周波数および温度が挙げられる。アナログ回路であるRFPGA35およびHPA40では、使用中の周波数および温度に応じて入力電圧に対する出力電圧のゲイン特性が変化する。たとえば、温度が上がるとHPAのゲインは低下するので、HPAのゲインの低下をRFPGAおよびDPGAのゲインの設定値の増加によって補う必要がある。特にHPAのゲイン変化に対する大まかな補正はRFPGAのゲインの増減で調整し、細かい補正はDPGAのゲインの増減で調整する。すなわち、RFPGA35およびHPA40のゲインを送信パワーの設定値に対して一意的に設定するのではなく、周波数および温度に応じてRFPGA35とHPA40との間でゲインの配分を変更することが望ましい。
図14は、この発明の実施の形態2による送信部122の構成を示すブロック図である。図14の局部発振器130_1,130_2は、それぞれ電流調整信号CCS1,CCS3に応じて動作時に流れる駆動電流の大きさが調整できる点で、図6の局部発振器30_1,30_2と異なる。図14の1/2分周器131_1,131_2は、それぞれ電流調整信号CCS2,CCS4に応じて動作時に流れる駆動電流の大きさが調整できる点で、図6の1/2分周器31_1,31_2と異なる。図14のAPC136は、図6のAPC36の機能に加えて、送信モード情報に応じた電流調整信号CCS1~CCS4を生成して出力する。図14のその他の点は図6の場合と同じであるので、同一または相当する部分には同一の参照符号を付して説明を繰返さない。
Claims (15)
- 複数の送信モードに従ってそれぞれデータを送信可能とする半導体装置であって、
第1のデジタルベースバンド信号を受け、前記第1のデジタルベースバンド信号を第1の利得で増幅した第2のデジタルベースバンド信号を生成し、その第1の利得が可変である第1の増幅部(24)と、
前記第1の増幅部(24)によって生成された前記第2のデジタルベースバンド信号をアナログベースバンド信号に変換するデジタル・アナログ変換部(25)と、
前記アナログベースバンド信号によって局部発振信号を変調することによって送信信号を生成する変調部(32)と、
前記送信信号を可変の第2の利得で増幅する第2の増幅部(35)と、
前記複数の送信モードのいずれかを表わす情報を受け、前記情報に応じて前記第1の利得を調整する制御部(36,136)とを備えた半導体装置(10)。 - 前記制御部(36,136)は、さらに、前記情報に応じて前記第2の利得を調整する、請求の範囲第1項に記載の半導体装置(10)。
- 前記制御部(36,136)は、前記第1の利得の最小の変更幅が前記第2の利得の最小の変更幅よりも小さくなるように前記第1および第2の利得を調整する、請求の範囲第2項に記載の半導体装置(10)。
- 前記複数の送信モードのうちの第1の送信モードにおける前記第1のデジタルベースバンド信号のピーク対平均電力比よりも、前記複数の送信モードのうちの第2の送信モードにおける前記第1のデジタルベースバンド信号のピーク対平均電力比が大きく、
前記第1の増幅部(24)が、前記第1の送信モードにおける前記第1のデジタルベースバンド信号、および、前記第2の送信モードにおける前記第1のデジタルベースバンド信号を受けた場合、前記制御部(36,136)は、前記第1の送信モードにおける前記第1の利得を前記第2の送信モードにおける前記第1の利得よりも大きくする、請求の範囲第1項に記載の半導体装置。 - 前記複数の送信モードのうちの第1の送信モードにおける前記第1のデジタルベースバンド信号のピーク対平均電力比よりも、前記複数の送信モードうちの第2の送信モードにおける前記第1のデジタルベースバンド信号のピーク対平均電力比が大きく、
前記第1の増幅部(24)は、前記第1の送信モードにおける前記第1のデジタルベースバンド信号、および、前記第2の送信モードにおける前記第1のデジタルベースバンド信号を受け、
前記制御部(36,136)は、前記第1の送信モードにおいて前記第1の利得を第1の下限値と第1の上限値との間で変化させ、前記第2の送信モードにおいて前記第1の利得を第2の下限値と第2の上限値との間で変化させ、
前記第1の下限値は、前記第2の下限値よりも大きく、
前記第1の上限値は、前記第2の上限値よりも大きい、請求の範囲第1項に記載の半導体装置(10)。 - 前記第1の下限値は、前記第2の上限値以上である、請求の範囲第5項に記載の半導体装置(10)。
- 前記局部発振信号を生成する局部発振回路(130)をさらに備え、
前記制御部(136)は、さらに、前記送信モードに応じて前記局部発振回路(130)に供給する駆動電流の大きさを調整する、請求の範囲第1項に記載の半導体装置(10)。 - 前記第1のデジタルベースバンド信号は、同相成分信号および直交成分信号を含み、
前記第1の増幅部(24)は、前記同相成分信号および前記直交成分信号の各々を前記第1の利得で増幅し、
前記アナログベースバンド信号は、同相成分信号および直交成分信号を含み、
前記半導体装置(10)は、前記局部発振信号を受けて、互いに位相が90度異なる第1および第2の局部発振信号を生成する分周回路(131)をさらに備え、
前記変調部(32)は、前記アナログベースバンド信号の前記同相成分信号および直交成分信号によって、前記第1および第2の局部発振信号を変調することによって前記送信信号を生成し、
前記制御部(136)は、さらに、前記送信モードに応じて前記分周回路に供給する駆動電流の大きさを調整する、請求の範囲第1または7項に記載の半導体装置(10)。 - 前記複数の送信モードは、変調方式、多重化方式および多元接続方式の少なくともいずれか1つがそれぞれで異なっている送信モードである、請求の範囲第1~8項のいずれか1項に記載の半導体装置(10)。
- 第1のデジタルベースバンド信号を受け、前記第1のデジタルベースバンド信号を第1の利得で増幅して第2のデジタルベースバンド信号を生成し、その第1の利得が可変である第1の増幅部(24)と、
前記第1の増幅部(24)によって生成された前記第2のデジタルベースバンド信号をアナログベースバンド信号に変換するデジタル・アナログ変換部(25)と、
前記アナログベースバンド信号によって局部発振信号を変調することによって送信信号を生成する変調部(32)と、
前記送信信号を可変の第2の利得で増幅する第2の増幅部(35)と、
送信すべきデータからベースバンド処理により前記第1のデジタルベースバンド信号を生成した際の変調方式、多重化方式および多元化方式の少なくともいずれか1つに応じて前記第1の利得を調整する制御部(36,136)とを備えた半導体装置(10)。 - 第1のデジタルベースバンド信号を受け、前記第1のデジタルベースバンド信号を第1の利得で増幅した第2のデジタルベースバンド信号を生成する第1の増幅部(24)と、
前記第1の増幅部によって生成された前記第2のデジタルベースバンド信号をアナログベースバンド信号に変換するデジタル・アナログ変換部(25)と、
前記アナログベースバンド信号によって局部発振信号を変調することによって送信信号を生成する変調部(32)と、
前記送信信号を可変の第2の利得で増幅する第2の増幅部(35)と、
前記送信信号が無線で送信されるときの送信電力を調整する制御信号を受け、その制御信号に応じて前記第1および第2の利得を調整する制御部(36,136)とを備えた半導体装置(10)。 - 外部から受信信号を受け、前記受信信号に基づいて前記受信信号の周波数よりも低い周波数のデータ信号を生成する受信回路(21)をさらに備え、
前記制御信号は、前記データ信号に含まれる情報に基づく信号である、請求の範囲第11項に記載の半導体装置(10)。 - 前記受信回路(21)は、前記データ信号をベースバンド処理回路(5)に供給し、
前記制御部(36,136)は、前記制御信号を前記ベースバンド処理回路(5)から受けとる、請求の範囲第12項に記載の半導体装置(10)。 - 前記送信信号は電力増幅器(40)に送信され、
前記制御部(36,136)は、さらに前記電力増幅器(40)の出力が検波された検波信号を受信し、その検波信号に応じても前記第1および第2の利得を調整する、請求の範囲第12項に記載の半導体装置(10)。 - 前記制御部(36,136)は、前記第1の利得の最小の変更幅が前記第2の利得の最小の変更幅よりも小さくなるように前記第1および第2の利得を調整する、請求の範囲第11項に記載の半導体装置(10)。
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