WO2011116642A1 - Mems器件及其形成方法 - Google Patents
Mems器件及其形成方法 Download PDFInfo
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- WO2011116642A1 WO2011116642A1 PCT/CN2011/070627 CN2011070627W WO2011116642A1 WO 2011116642 A1 WO2011116642 A1 WO 2011116642A1 CN 2011070627 W CN2011070627 W CN 2011070627W WO 2011116642 A1 WO2011116642 A1 WO 2011116642A1
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- layer
- gate electrode
- mems device
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- region
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 319
- 239000011229 interlayer Substances 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 34
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 3
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- 238000005468 ion implantation Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
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- 230000002929 anti-fatigue Effects 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- This invention relates to microelectromechanical system processes, and more particularly to MEMS devices and methods of forming same. Background technique
- Microelectromechanical systems technology (MEMS), as an interdisciplinary advanced manufacturing technology that originated in the 1990s, is widely used to improve people's quality of life, improve people's living standards and enhance national strength.
- MEMS Microelectromechanical systems technology
- the micro-electro-mechanical system process has strong multi-disciplinary cross-characteristics.
- silicon-based processes have become the mainstream of micro-electro-mechanical systems, but due to the complexity of micro-electro-mechanical systems, the integration of micro-electro-mechanical systems and semiconductor processes Chemicalization has always been a constraint in the development of microelectromechanical systems.
- the semiconductor process has the advantages of low cost, high precision, and good uniformity. For this reason, the integration of the microelectromechanical system process and the semiconductor process can not only utilize the advantages of the above semiconductor process, but also solve the defects of the semiconductor device formed by the semiconductor process.
- a gate electrode in a MOS transistor as an example, a conventional gate includes a gate dielectric layer; and a gate electrode layer formed on a surface of the gate dielectric layer. More information on the gate can be found in the Chinese patent document with the publication number 1522463.
- the gate dielectric layer material usually uses silicon dioxide
- the gate electrode layer is usually made of a conductive material, such as polysilicon or metal
- the interface state change between the gate electrode layer and the gate dielectric layer is generally liable to cause leakage current, which is changed by the interface state. The resulting leakage current will prevent the transistor from functioning properly.
- the problem addressed by the present invention is to provide a MEMS device with low gate leakage current compatible with existing semiconductor processes and a method of forming the same.
- the present invention provides a MEMS device comprising: a semiconductor substrate; a well region formed in the semiconductor substrate; a source region, a drain region, and a channel region formed in the well region; formed at the source a barrier layer on a surface of the drain region; a gate dielectric layer formed on a surface of the channel region; a gate electrode layer formed over the gate dielectric layer and having a gap with the gate dielectric layer, the gap width corresponding to a width of the channel region .
- the gate electrode layer is a single cladding layer or a multi-layer stacked structure.
- the material of the single cladding gate electrode layer is a conductive material.
- the gate electrode layer structure is a three-layer stacked structure of a metal layer, a silicon oxide layer formed on the surface of the metal layer, and a silicon nitride layer formed on the surface of the silicon oxide layer.
- the isolation layer is a multi-layer stacked structure.
- the isolation layer comprises a protective layer, a barrier layer and an interlayer dielectric layer which are sequentially formed on the surface of the well region.
- the material of the protective layer is silicon oxide.
- the material of the barrier layer is silicon nitride.
- the interlayer dielectric layer material is selected from undoped silicon oxide or doped silicon oxide.
- the width of the gate electrode layer corresponds to the width of the channel region.
- the source and drain regions have a conductivity type opposite the well region.
- the present invention also provides a method of forming a MEMS device, comprising: providing a semiconductor substrate, wherein a well region is formed in the semiconductor substrate, and a source region, a drain region, and a channel region are formed in the well region; Forming an isolation layer on a surface of the semiconductor substrate;
- the filling layer is removed to form a gap between the gate electrode layer and the gate dielectric layer.
- the step of forming the gate electrode layer includes: forming a gate electrode film on the surface of the interlayer dielectric layer and the filling layer; forming a photoresist pattern corresponding to the gate electrode layer on the surface of the gate electrode film And etching the gate electrode film to form a gate electrode layer by using the photoresist pattern as a mask.
- the gate electrode layer exposes a partially filled layer.
- the gate electrode layer is a single cladding layer or a multi-layer stacked structure.
- the material of the single cladding gate electrode layer is a conductive material.
- the electrode layer structure is a three-layer stack structure of a metal layer, a silicon oxide layer formed on the surface of the metal layer, and a silicon nitride layer formed on the surface of the silicon oxide layer.
- the width of the gate electrode layer corresponds to the width of the channel region.
- the material of the filling layer is selected from materials having selective removal characteristics from the gate electrode layer and the gate dielectric layer.
- the invention provides a MEMS device and a method for forming the same, wherein the method for forming a MEMS device is compatible with a conventional semiconductor forming process, and does not need to re-develop a new material and a new preparation process, and the gate electrode layer and the gate dielectric layer of the fabricated MEMS device It has a gap, is not in direct contact, and avoids leakage current caused by interface state change.
- the MEMS device provided by the invention has high withstand voltage performance and low gate electrode leakage current.
- FIG. 1 is a schematic cross-sectional view of an embodiment of a MEMS device
- FIG. 2 is a top plan view of an embodiment of a MEMS device
- FIG. 3 is a flow chart of an embodiment of a method for forming a MEMS device according to the present invention.
- FIGS. 4 to 11 are schematic diagrams showing an embodiment of a method of forming a MEMS device according to the present invention.
- the existing gate structure includes a gate dielectric layer and a gate electrode layer formed on the surface of the gate dielectric layer. Leakage current formed due to the difference in material of the gate dielectric layer and the gate electrode layer may cause the transistor to malfunction.
- the inventors of the present invention provide a MEMS device and a method of forming the same, the formed MEMS device comprising a gate electrode layer having a gap with a gate dielectric layer, which is adsorbed to the gate dielectric layer or suspended in the gate electrode layer by electrostatic adsorption
- the gate dielectric layer is over, thereby controlling the MEMS device to be turned on or off, to avoid leakage current of the gate electrode layer and the gate dielectric layer in the semiconductor device, and the MEMS device and the forming method thereof provided by the invention can be compatible with the semiconductor process, avoiding expensive semiconductor new processes Research and development.
- FIG. 1 is a cross-sectional view of an embodiment of a MEMS device, including: a semiconductor substrate 100; a well region 110 formed in the semiconductor substrate 100; formed in the well region 110. a source region 111, a drain region 112, and a channel region 113; formed in the source region 111, An isolation layer on the surface of the drain region 112.
- the isolation layer may be a single cladding layer or a multi-layer stacked structure.
- the isolation layer material is a dielectric material; the isolation layer is a multi-layer stacked structure.
- the protective layer 120, the barrier layer 130 formed on the surface of the protective layer 120, and the interlayer dielectric layer 140 formed on the surface of the barrier layer 130 are included; in this embodiment, the isolation layer is a multi-layer stacked structure.
- the MEMS device provided by the present invention further includes: an opening 121 formed in the interlayer dielectric layer 140 and exposing the well region 110; a gate dielectric layer 150 formed at the bottom of the opening 121; above the gate dielectric layer 150 and with the gate dielectric layer 150 A gate electrode layer 170 having a gap therebetween, the width of the gap corresponding to the width of the channel region 113.
- FIG. 2 is a top view of an embodiment of the MEMS device
- FIG. 1 is a cross-sectional view of the second embodiment of FIG. 2, which can be found in FIG. It is located on the surface of the interlayer dielectric layer 140 so as to have a gap with the gate dielectric layer 150.
- the gate dielectric layer 150 is covered by the opening 121 and the gate electrode layer 170, which is not shown in FIG.
- the semiconductor substrate 100 may be an n-type silicon substrate, a p-type silicon substrate, or a silicon substrate (SOI) on an insulating layer.
- SOI silicon substrate
- the well region 110 has a first conductivity type, and the first conductivity type may be an n-type or a p-type.
- the following is an example of a first conductivity type being a p-type and a second conductivity type being an n-type.
- the method of forming the well region is formed by a conventional ion implantation process.
- the source region 111 and the drain region 112 have a conductivity type opposite to the well region 110, which is a second conductivity type.
- the formation process of the source region 111 and the drain region 112 can refer to a formation process of the MOS crystal.
- the existing ion implantation process is formed.
- the channel region 113 is a well region between the source region 111 and the drain region 112, and the conductivity type is the first conductivity type.
- the material of the protective layer 120 is selected from silicon oxide
- the material of the barrier layer 130 is selected from silicon nitride
- the material of the interlayer dielectric layer 140 is selected from undoped silicon oxide or doped silicon oxide (BPSG, PSG or BSG)
- the formation process of the protective layer 120, the barrier layer 130 and the interlayer dielectric layer 140 is an existing deposition process, such as chemical vapor deposition; the protective layer 120, the barrier layer 130 and the interlayer dielectric layer 140 constitute isolation Floor.
- the formation process of the opening 121 is an etching process
- the material of the gate dielectric layer 150 is silicon oxide
- the formation process is chemical vapor deposition.
- the gate dielectric layer 150 is deposited in the opening 121.
- the sidewall of the opening 121 and the surface of the interlayer dielectric layer 140 are also formed with a silicon oxide layer, and the silicon oxide layer on the sidewall of the opening 121 and the interlayer dielectric layer 140 may be removed by a removal process.
- the removal or retention is saved in order to save the process.
- the silicon oxide layer is retained to save process steps.
- the gate electrode layer 170 may be a single cladding layer or a multilayer stacked structure. When the gate electrode layer 170 is a single cladding layer, the gate electrode layer 170 is a conductive material, such as polysilicon, doped polysilicon, aluminum, copper. , silver or gold.
- the more preferable gate electrode layer 170 is a three-layer stacked structure of a metal layer, a silicon oxide layer formed on the surface of the metal layer, and a silicon nitride layer formed on the surface of the silicon oxide layer, and the preferred three-layer stacked structure can improve the metal layer. Anti-fatigue properties improve the life of MEMS devices.
- width dl of the gate electrode layer 170 is larger than the width d2 of the channel region 113.
- the channel region 113 forms a conduction channel.
- an opening voltage may be applied to the gate electrode layer 170, and the turn-on voltage may be applied to a separate conductive plug (not shown), and the conductive plug may be disposed in the interlayer dielectric.
- the gate dielectric layer 150 Above the gate electrode layer 170 on the surface of the layer 140, connected to the metal layer of the gate electrode layer 170, when the gate electrode layer 170 applies an on-voltage, the gate dielectric layer 150 may have an opposite charge to the gate electrode layer 170 due to electrostatic induction.
- the dielectric layer 150 and the gate electrode layer 170 are attracted to each other such that the gate electrode layer 170 is deformed into contact with the gate dielectric layer 150 such that the gate electrode layer 170 and the gate dielectric layer 150 have the same potential, and the channel region 113 is opened, so that the MEMS device is turned on;
- the electrode layer 170 removes the turn-on voltage, the gate electrode layer 170 and the gate dielectric layer 150 repel each other with the same charge, and the gate electrode layer 170 restores the initial state of mind from the gate dielectric layer 150, thereby closing the MEMS device.
- a preferred process parameter is that the area of the opening 121 is 0.01 ⁇ ⁇ 2 ⁇ 25 ⁇ ⁇ 2 , and the thickness of the isolation layer is 0.2 ⁇ m ⁇ l ⁇ m, the gate electrode The thickness of the layer 170 is 500 ⁇ to 5000 ⁇ (the specific value of the gate electrode layer 170 is also related to the width of the channel region 113), and the above process parameters can ensure that the MEMS device does not break the gate electrode layer 170.
- Step S101 providing a semiconductor substrate, wherein a well region is formed in the semiconductor substrate, and a source region and a drain region are formed in the well region.
- Step S102 forming an opening in the isolation layer, the opening exposing the channel region and a portion of the source region and the drain region adjacent to the channel region;
- Step S103 forming a gate dielectric layer at the bottom of the opening;
- Step S104 forming a filling layer filling the opening on the surface of the gate dielectric layer;
- Step S105 planarizing the filling layer until the interlayer dielectric layer is exposed;
- Step S106 forming a gate on the surface of the interlayer dielectric layer and the filling layer Electrode layer; Step S107, removing the filling layer.
- step S101 is performed to provide a semiconductor substrate 100, which may be an n-type silicon substrate, a p-type silicon substrate, or a silicon substrate (SOI) on an insulating layer, in this embodiment.
- a semiconductor substrate 100 which may be an n-type silicon substrate, a p-type silicon substrate, or a silicon substrate (SOI) on an insulating layer, in this embodiment.
- a p-type silicon substrate is taken as an example for exemplary explanation.
- a well region 110 is formed in the semiconductor substrate 100.
- the ion type of the well region may be n-type or p-type.
- the well region 110 is an n-type.
- the formation process of the well region 110 is an existing ion implantation, and the type of the ion implantation is n-type.
- the ion type of the semiconductor substrate 100 is p-type
- the ion type of the well region 110 is also When it is p-type, the next process can be directly performed; when the ion type of the semiconductor substrate 100 is p-type, when the ion type of the well region 110 is n-type, an n-type ion can be implanted into the semiconductor substrate 100 by an ion implantation process.
- An n-type well region is formed.
- a sacrificial oxide layer may be formed on the surface of the well region 110 by referring to a standard MOS transistor formation process, and then an ion implantation process is performed on the well region 110 for adjusting the MEMS device. The voltage is turned on and the sacrificial oxide layer is removed after the ion implantation process.
- a source region 111, a drain region 112, and a channel region 113 are formed in the well region 110; the source region 111, the drain region 112, and the channel region 113 pass through the source region 111 and Ion implantation is performed in the drain region 112.
- the ion implantation type of the source region 111 and the drain region 112 is opposite to the ion type of the well region 110, and the well region between the source region 111 and the drain region 112 is a trench. Road area 113.
- a protective layer 120, a barrier layer 130, and an interlayer dielectric layer 140 are sequentially formed on the surface of the semiconductor substrate 100.
- the protective layer 120, the barrier layer 130, and the interlayer dielectric layer 140 constitute an isolation layer, and other implementations
- the isolation layer may also be a single cladding layer.
- the isolation layer material is selected from a dielectric material.
- the protective layer 120 is made of silicon oxide, and the protective layer 120 is used to protect the semiconductor substrate 100 from damage in the subsequent plasma etching; the barrier layer 130 is made of silicon nitride. The barrier layer 130 serves as a stop layer for the etching process to avoid etching damage caused by the etching process.
- the semiconductor substrate 100; the interlayer dielectric layer 140 is made of silicon oxide, phosphorus-doped silicon oxide, or boron-doped silicon oxide, and the interlayer dielectric layer 140 protects the isolation source region 111, the drain region 112, and the trench.
- the first metal plug 111a and the through protective layer 120 and the barrier layer 130 are formed in the interlayer dielectric layer 140 through the protective layer 120 and the barrier layer 130 and are electrically connected to the source region 111.
- the second metal plug 112a is electrically connected to the pole region 112.
- the forming process of the first metal plug 111a and the second metal plug 112a is to form a photoresist pattern corresponding to the first metal plug 111a and the second metal plug 112a on the surface of the interlayer dielectric layer 140;
- the photoresist pattern is a mask, and the interlayer dielectric layer 140 is etched until the surface of the source region 111 and the surface of the drain region 112 are exposed to form a contact hole (not shown); the photoresist pattern is removed; and the conductive material is used;
- the contact holes are filled to form a first metal plug 111a and a second metal plug 112a.
- a buffer layer may be formed on the sidewalls and the bottom of the contact hole by Ti/TiN or Ta/TaN before filling the conductive material.
- an opening 121 is formed in the isolation layer as described in step S102, and the opening 121 exposes the channel region 113 and a portion of the source region 111 and the drain region 112 adjacent to the channel region 113.
- the forming the opening 121 is formed by a plasma etching process.
- the step of specifically forming the opening 121 includes: forming a photoresist pattern corresponding to the opening 121 on the surface of the interlayer dielectric layer 140; Masking, etching the interlayer dielectric layer 140, the protective layer 120 and the barrier layer 130 until the channel region 113 and a portion of the source region 111 and the drain region 112 adjacent to the channel region 113 are exposed, forming an opening 121.
- a gate dielectric layer 150 is formed at the bottom of the opening 121 as described in step S103.
- the material of the gate dielectric layer 150 may be silicon oxide, and the formation process of the gate dielectric layer is chemical vapor deposition. It should be noted that since the formation process is a deposition process, the sidewall of the opening 121 and the surface of the interlayer dielectric layer 140 A silicon oxide layer is also formed, and the sidewall of the opening 121 and the silicon oxide layer on the surface of the interlayer dielectric layer 140 may be removed or retained by an additional removal process. In this embodiment, the sidewall of the opening 121 And the silicon oxide layer on the surface of the interlayer dielectric layer 140 is retained to save process steps.
- a filling layer 160 filling the opening 121 is formed on the surface of the gate dielectric layer 150 as described in step S104.
- the filling layer 160 provides a support platform for the subsequently formed gate electrode layer, and the material of the filling layer 160 is selected from materials having selective removal characteristics from the gate electrode layer and the gate dielectric layer.
- the filling layer 160 is planarized until the interlayer dielectric layer 140 is exposed as described in step S105.
- the surface of the filling layer 160 may be uneven.
- a gate electrode layer 170 is formed on the surface of the interlayer dielectric layer 140 and the filling layer 160 as described in step S106.
- the gate electrode layer 170 may be a single cladding layer or a multi-layer stacked structure.
- the gate electrode layer 170 is made of a conductive material, such as polysilicon, doped polysilicon, aluminum, copper, Silver or gold.
- the more preferable gate electrode layer 170 is a three-layer stacked structure of a metal layer, a silicon oxide layer formed on the surface of the metal layer, and a silicon nitride layer formed on the surface of the silicon oxide layer, and the preferred three-layer stacked structure can improve the metal layer. Anti-fatigue properties improve the life of MEMS devices.
- the step of forming the gate electrode layer 170 includes: forming a gate electrode film (not shown) on the surface of the interlayer dielectric layer 140 and the filling layer 160; forming a surface corresponding to the gate electrode layer on the surface of the gate electrode film a photoresist pattern; etching the gate electrode film to form a gate electrode layer 170 by using the photoresist pattern as a mask.
- FIG. 10 is a plan view of the gate electrode layer 170
- FIG. 9 is a cross-sectional view of FIG. 10 along the direction of bb.
- the gate electrode layer 170 is formed on the surface of the filling layer 160 and exposes a portion of the filling layer 160.
- the gate electrode layer 170 is partially located on the surface of the interlayer dielectric layer 140, similar to a floating bridge shape, and The gate dielectric layer 150 is spaced apart by a fill layer 160.
- the filling layer 160 is removed as described in step S107.
- the process of removing the filling layer 160 is selective etching removal, and the device is placed in an etching solution for selectively removing the filling layer 160, and the etching solution is etched along the filling layer 160 exposed by the gate electrode layer 170 until the filling layer 160 is removed.
- the gate electrode layer 170 is located above the gate dielectric layer 150 and has a gap with the gate dielectric layer 150. It should be noted that the width d1 of the gate electrode layer 170 is larger than the width d2 of the channel region 113. Large, when the MEMS device provided by the present invention is in an on state, the channel region 113 can be turned on.
- the invention provides a MEMS device and a method for forming the same, wherein the method for forming the MEMS device is compatible with the traditional semiconductor forming process, and does not need to re-develop a new material and a new preparation process, and the prepared MEMS device has high withstand voltage performance and the gate electrode is leaked. The current is low.
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Description
MEMS器件及其形成方法
本申请要求于 2010 年 3 月 25 日提交中国专利局、 申请号为 201010135707.5、 发明名称为 "MEMS 器件及其形成方法"的中国专利申请的 优先权, 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及微电子机械系统工艺, 特别涉及 MEMS器件及其形成方法。 背景技术
微电子机械系统工艺 (MEMS )作为起源于上世纪 90年代的跨学科的先 进制造技术, 广泛应用于改善人们生活质量、 提高人们生活水平和增强国力。 微电子机械系统工艺具有强烈的多学科交叉特征, 近年来,基于硅工艺已经成 为微电子机械系统工艺的主流,但是由于微电子机械系统工艺的复杂性,微电 子机械系统工艺与半导体工艺的集成化一直成为微电子机械系统工艺发展中 的制约。
半导体工艺具有成本低、 精度高、 一致性好的优点, 为此, 微电子机械系 统工艺与半导体工艺的集成化不但能够利用上述半导体工艺的优点,还能够解 决半导体工艺形成的半导体器件的缺陷, 以 MOS晶体管中的栅极为例, 传统 的栅极包括,栅介质层;形成在栅介质层表面的栅电极层。在公开号为 1522463 的中国专利文件中可以发现更多有关栅极的资料。但是, 由于栅介质层材料通 常采用二氧化硅, 而栅电极层通常采用导电材料, 例如多晶硅或者金属, 栅电 极层与栅介质层的界面态变化通常容易导致漏电流的产生,由界面态变化产生 的漏电流会让晶体管无法正常工作。
发明内容
本发明解决的问题是提供一种与现有半导体工艺兼容的栅极漏电流低的 MEMS器件及其形成方法。
为解决上述问题, 本发明提供一种 MEMS器件, 包括: 半导体衬底; 形 成在半导体衬底内的阱区; 形成在阱区内的源极区、 漏极区和沟道区; 形成在 源极区、 漏极区表面的隔离层; 形成在沟道区表面的栅介质层; 形成在栅介质 层上方并与栅介质层具有间隙的栅电极层, 所述间隙宽度与沟道区宽度对应。
可选的, 所述栅电极层是单一覆层或者多层堆叠结构。
可选的, 所述单一覆层栅电极层的材料为导电材料。
可选的, 所述栅电极层结构为金属层、形成在金属层表面的氧化硅层和形 成在氧化硅层表面的氮化硅层的三层堆叠结构。
可选的, 所述隔离层是多层堆叠结构。
可选的, 所述隔离层包括依次形成在阱区表面的保护层、 阻挡层和层间介 质层。
可选的, 所述保护层的材料为氧化硅。
可选的, 所述阻挡层的材料为氮化硅。
可选的, 所述层间介质层材料选自未捧杂的氧化硅或者掺杂的氧化硅。 可选的, 栅电极层的宽度与沟道区的宽度对应。
所述源极区和漏极区具有和阱区相反的导电类型。
本发明还提供一种 MEMS器件形成方法, 包括: 提供半导体衬底, 所述 半导体衬底内形成有阱区, 所述阱区内形成有源极区、 漏极区和沟道区; 在所述半导体衬底表面形成隔离层;
在隔离层内形成开口,所述开口暴露出沟道区和与沟道区相邻的部分源极 区、 漏极区;
在所述开口底部形成栅介质层;
形成填平所述开口的填充层;
在所述层间介质层、 填充层表面形成栅电极层;
去除填充层, 使栅电极层与栅介质层形成间隙。
可选的, 所述栅电极层的形成步骤包括: 在所述层间介质层、 填充层表面 形成一层栅电极薄膜;在所述栅电极薄膜表面形成与栅电极层对应的光刻胶图 形; 以所述光刻胶图形为掩膜, 刻蚀所述栅电极薄膜形成栅电极层。
可选的, 所述栅电极层暴露出部分填充层。
可选的, 所述栅电极层是单一覆层或者多层堆叠结构。
可选的, 所述单一覆层栅电极层的材料为导电材料。
可选的, 所述电极层结构为金属层、形成在金属层表面的氧化硅层和形成 在氧化硅层表面的氮化硅层的三层堆叠结构。
可选的, 栅电极层的宽度与沟道区的宽度对应。
可选的,填充层的材料选用与栅电极层和栅介质层具有选择性去除特性的 材料。
本发明提供的一种 MEMS器件及其形成方法,其中 MEMS器件的形成方 法与传统半导体形成工艺兼容, 不需要重新研发新型材料和新的制备工艺,且 制备的 MEMS器件栅电极层与栅介质层具有空隙, 并不直接接触, 避免了界 面态变化导致的漏电流产生, 发明提供的 MEMS器件耐压性能高, 栅电极漏 电流低。
附图说明
通过附图中所示的本发明的优选实施例的更具体说明,本发明的上述及其 它目的、特征和优势将更加清晰。在全部附图中相同的附图标记指示相同的部 分。 并未刻意按实际尺寸等比例缩放绘制附图, 重点在于示出本发明的主旨。
图 1为 MEMS器件一实施例的剖面示意图;
图 2为 MEMS器件一实施例的俯视图;
图 3为本发明 MEMS器件形成方法的一实施例流程图;
图 4至图 11为本发明 MEMS器件形成方法的一实施例过程示意图。
具体实施方式
由背景技术可知,现有的栅极结构包括栅介质层和形成在栅介质层表面的 栅电极层,由于栅介质层和栅电极层材料不同从而形成的漏电流会让晶体管无 法正常工作。
为此,本发明的发明人提供一种 MEMS器件及其形成方法,形成的 MEMS 器件包括与栅介质层有间隙的栅电极层,通过静电吸附作用控栅电极层吸附至 栅介质层或者悬浮在栅介质层上空, 从而控制 MEMS器件开或者关, 避免半 导体器件中栅电极层与栅介质层漏电流, 并且本发明提供的 MEMS器件及其 形成方法能够与半导体工艺兼容, 避免昂贵的半导体新工艺研发。
以下依据附图详细地描述具体实施例,上述的目的和本发明的优点将更加
/目疋。
本发明提供一种 MEMS器件, 参考图 1 , 图 1为 MEMS器件一实施例的 剖面示意图, 包括: 半导体衬底 100; 形成在半导体衬底 100内的阱区 110; 形成在阱区 110内的源极区 111、漏极区 112和沟道区 113;形成在源极区 111、
漏极区 112表面的隔离层, 所述隔离层可以是单一覆层或者多层堆叠结构, 当 隔离层为单一覆层时,隔离层材料为介电材料;所述隔离层为多层堆叠结构时, 包括保护层 120、 形成在保护层 120表面的阻挡层 130、 和形成在阻挡层 130 表面的层间介质层 140; 本实施例中以所述隔离层为多层堆叠结构为例。 本发 明提供的 MEMS器件还包括: 形成在层间介质层 140内并暴露出阱区 110的 开口 121 ; 形成在开口 121底部的栅介质层 150; 位于栅介质层 150上方并与 栅介质层 150之间具有间隙的栅电极层 170, 所述间隙的宽度与沟道区 113宽 度对应。
为方便理解本发明提供的 MEMS器件, 请参考图 2, 图 2为 MEMS器件 一实施例的俯视图, 图 1为图 2沿 a-a, 方向的剖面示意图, 从图 2中可以发 现栅电极层 170部分位于层间介质层 140表面,从而与栅介质层 150具有间隙, 需要说明的是, 所述栅介质层 150被开口 121和栅电极层 170覆盖, 在图 2 上未能示出。
具体的, 所述半导体衬底 100可以为 n型硅衬底、 p型硅衬底或者绝缘层 上的硅衬底(SOI )。
所述阱区 110具有第一导电类型,所述第一导电类型可以为 n型或者 p型, 下面以第一导电类型为 p型、 第二导电类型为 n型为例, 做示范性说明, 所述 阱区的形成方法为现有的离子注入工艺形成。
所述源极区 111和漏极区 112具有和阱区 110相反的导电类型, 为第二导 电类型, 所述源极区 111和漏极区 112的形成工艺可以参考 MOS晶体的形成 工艺, 为现有的离子注入工艺形成, 当源极区 111和漏极区 112形成后, 沟道 区 113为源极区 111和漏极区 112之间的阱区, 导电类型为第一导电类型。
所述保护层 120的材料选自氧化硅, 所述阻挡层 130的材料选自氮化硅, 层间介质层 140材料选自未捧杂的氧化硅或者掺杂的氧化硅( BPSG、 PSG或 者 BSG ), 所述保护层 120、 阻挡层 130和层间介质层 140的形成工艺为现有 的沉积工艺, 例如化学气相沉积; 所述保护层 120、 阻挡层 130和层间介质层 140构成隔离层。
所述开口 121的形成工艺为刻蚀工艺,栅介质层 150的材料为氧化硅,形 成工艺为化学气相沉积, 在本实施例中, 由于栅介质层 150 沉积在开口 121
底部,在沉积栅介质层 150时, 开口 121的侧壁和层间介质层 140表面也会形 成有氧化硅层,位于开口 121侧壁和层间介质层 140表面的氧化硅层可以通过 去除工艺去除或者为了节约工艺而保留,在本实施例中,所述氧化硅层予以保 留, 以节约工艺步骤。所述栅电极层 170可以是单一覆层也可以是多层堆叠结 构, 当栅电极层 170为单一覆层时, 所述栅电极层 170为导电材料, 例如多晶 硅、 掺杂多晶硅、 铝、 铜、 银或者金。
较优选的栅电极层 170结构为金属层、形成在金属层表面的氧化硅层和形 成在氧化硅层表面的氮化硅层的三层堆叠结构,优选的三层堆叠结构能够提高 金属层的抗疲劳特性, 提高 MEMS器件的寿命。
还需要说明的是, 栅电极层 170的宽度 dl要比沟道区 113的宽度 d2, 当
MEMS器件处于开启状态时, 可以保证沟道区 113形成导通沟道。
在本实施例中, 可以通过对栅电极层 170施加一开启电压, 所述开启电压 可以施加于另设的导电插塞(未图示)上, 所述导电插塞可以设置于位于层间 介质层 140表面的栅电极层 170上方, 与栅电极层 170的金属层相连, 当栅电 极层 170施加开启电压后, 栅介质层 150会因为静电感应而带有与栅电极层 170相反的电荷, 栅介质层 150与栅电极层 170互相吸引, 使得栅电极层 170 形变与栅介质层 150接触,使得栅电极层 170与栅介质层 150电势相同,开启 沟道区 113 , 从而 MEMS器件开启; 当栅电极层 170移除开启电压, 栅电极 层 170和栅介质层 150带同种电荷相斥,栅电极层 170恢复初始心态与栅介质 层 150相隔, 从而 MEMS器件关闭。
需要指出的是, 为了使得 MEMS器件正常工作, 较优选的工艺参数为所 述开口 121的面积为 0.01 μ ηι2~25 μ ηι2, 所述隔离层厚度为为 0.2 μ m~l μ m, 栅电极层 170厚度为 500埃〜 5000埃(栅电极层 170具体的取值还和沟道区 113 的宽度有关),上述的工艺参数能够保证 MEMS器件,栅电极层 170不会断裂。
图 3为本发明 MEMS器件形成方法的一实施例流程图,包括:步骤 S101 , 提供半导体衬底, 所述半导体衬底内形成有阱区, 所述阱区内形成有源极区、 漏极区和沟道区;在所述半导体衬底表面形成隔离层,所述隔离层包括保护层、 阻挡层和层间介质层; 所述层间介质层内形成有贯穿保护层、 阻挡层并位于源 极区表面的第一金属插塞和贯穿保护层、阻挡层并位于漏极区表面第二金属插
塞; 步骤 S102, 在隔离层内形成开口, 所述开口暴露出沟道区和与沟道区相 邻的部分源极区、 漏极区; 步骤 S103 , 在所述开口底部形成栅介质层; 步骤 S104, 在栅介质层表面形成填充所述开口的填充层; 步骤 S105 , 平坦化所述 填充层直至暴露出层间介质层; 步骤 S106, 在所述层间介质层、 填充层表面 形成栅电极层; 步骤 S107, 去除填充层。
下面参照附图, 对上述 MEMS器件形成方法加以详细阐述。
首先参照图 4,执行步骤 S101 ,提供半导体衬底 100,所述半导体衬底 100 可以为 n型硅衬底、 p型硅衬底或者绝缘层上的硅衬底(SOI ), 在本实施例中 以 p型硅衬底为例做示范性说明。
所述半导体衬底 100内形成有阱区 110, 所述阱区的离子类型可以为 n型 或者 p型, 在本实施例中以所述阱区 110为 n型为例。 所述阱区 110的形成工 艺为现有的离子注入, 所述离子注入的类型为 n型, 需要指出的是, 当半导体 衬底 100的离子类型为 p型时, 阱区 110的离子类型也为 p型时, 可以直接执 行下一工艺; 当半导体衬底 100的离子类型为 p型时, 阱区 110的离子类型为 n型时,可以采用离子注入工艺在半导体衬底 100注入 n型离子形成 n型阱区。
在形成阱区 110后,还可以参考标准的 MOS晶体管形成工艺,在阱区 110 表面形成一层牺牲氧化层, 然后对阱区 110进行离子注入工艺, 所述离子注入 工艺用于调整 MEMS器件的开启电压,在离子注入工艺后再去除牺牲氧化层。
参考图 4, 所述阱区 110内形成有源极区 111、 漏极区 112和沟道区 113; 所述源极区 111、 漏极区 112和沟道区 113通过在源极区 111和漏极区 112内 进行离子注入,所述源极区 111和漏极区 112的离子注入类型与阱区 110的离 子类型相反, 位于源极区 111和漏极区 112之间的阱区为沟道区 113。
继续参考图 4, 在半导体衬底 100表面依次形成保护层 120、 阻挡层 130 和层间介质层 140, 所述保护层 120、 阻挡层 130和层间介质层 140构成隔离 层, 在其他的实施例中, 所述隔离层也可以为单一的覆层, 当隔离层为单一覆 层时, 隔离层材料选自介电材料。
所述保护层 120材料为氧化硅,所述保护层 120用于保护半导体衬底 100, 避免半导体衬底 100在后续的等离子体刻蚀中受到损伤;所述阻挡层 130材料 为氮化硅, 所述阻挡层 130作为刻蚀工艺的停止层,避免刻蚀工艺过刻蚀损伤
半导体衬底 100; 所述层间介质层 140材料为氧化硅、 掺磷的氧化硅、 掺硼磷 的氧化硅, 所述层间介质层 140保护隔离源极区 111、 漏极区 112、 沟道区 113 和半导体衬底 100, 以及为后续形成的层间金属层提供平台。
依旧参考图 4,所述层间介质层 140内形成有贯穿保护层 120、阻挡层 130 并与源极区 111导通的第一金属插塞 111a和贯穿保护层 120、阻挡层 130并与 漏极区 112导通的第二金属插塞 112a。
所述第一金属插塞 111a和第二金属插塞 112a的形成工艺为在层间介质层 140表面形成与第一金属插塞 111a和第二金属插塞 112a对应光刻胶图形; 以 所述光刻胶图形为掩膜,刻蚀所述层间介质层 140直至暴露出源极区 111表面 和漏极区 112表面, 形成接触孔(未图示); 去除光刻胶图形; 采用导电物质 填充所述接触孔, 形成第一金属插塞 111a和第二金属插塞 112a。 为了避免所 述导电物质向层间介质层 140内扩散, 在填充导电物质之前, 可以采用 Ti/TiN 或者 Ta/TaN在接触孔侧壁和底部形成一层緩沖层。
参考图 5 , 如步骤 S102所述, 在隔离层内形成开口 121 , 所述开口 121 暴露出沟道区 113和与沟道区 113相邻的部分源极区 111、 漏极区 112。
所述形成开口 121的通过等离子体刻蚀工艺形成,具体形成开口 121的步 骤包括: 在所述层间介质层 140表面形成与开口 121对应的光刻胶图形; 以所 述光刻胶图形为掩膜, 刻蚀所述层间介质层 140、 保护层 120和阻挡层 130, 直至暴露出沟道区 113和与沟道区 113相邻的部分源极区 111、 漏极区 112, 形成开口 121。
参考图 6, 如步骤 S103所述, 在所述开口 121底部形成栅介质层 150。 所述栅介质层 150的材料可以为氧化硅,所述栅介质层的形成工艺为化学 气相沉积, 需要指出的是, 由于形成工艺为沉积工艺, 开口 121的侧壁以及层 间介质层 140表面也会形成有氧化硅层,所述开口 121的侧壁以及层间介质层 140 表面的氧化硅层可以通过额外的去除工艺去除也可以保留, 在本实施例 中, 所述开口 121的侧壁以及层间介质层 140表面的氧化硅层予以保留, 以节 约工艺步骤。
参考图 7,如步骤 S104所述,在栅介质层 150表面形成填充所述开口 121 的填充层 160。
所述填充层 160为后续形成的栅电极层提供支撑平台, 且所述填充层 160 的材料选用与栅电极层和栅介质层具有选择性去除特性的材料。
参考图 8, 如步骤 S105所述, 平坦化所述填充层 160直至暴露出层间介 质层 140。
由之前步骤可知, 填充所述开口 121后, 填充层 160的表面会凹凸不平, 为保证后续栅电极层的形成质量, 需要采用平坦化工艺平坦化所述填充层 160 并去除部分的氧化硅层, 直至暴露出层间介质层 140, 所述平坦化工艺可以选 用现有的化学机械抛光工艺, 在这里不再赘述。
参考图 9, 如步骤 S106所述, 在所述层间介质层 140、 填充层 160表面形 成栅电极层 170。
所述栅电极层 170 可以是单一覆层也可以是多层堆叠结构, 当栅电极层 170为单一覆层时,栅电极层 170材料为导电材料,例如多晶硅、掺杂多晶硅、 铝、 铜、 银或者金。
较优选的栅电极层 170结构为金属层、形成在金属层表面的氧化硅层和形 成在氧化硅层表面的氮化硅层的三层堆叠结构,优选的三层堆叠结构能够提高 金属层的抗疲劳特性, 提高 MEMS器件的寿命。
所述栅电极层 170的形成步骤包括: 在所述层间介质层 140、 填充层 160 表面形成一层栅电极薄膜(未图示); 在所述栅电极薄膜表面形成与栅电极层 对应的光刻胶图形; 以所述光刻胶图形为掩膜, 刻蚀所述栅电极薄膜形成栅电 极层 170。
为进一步理解本发明, 请参考图 10, 图 10为形成栅电极层 170后的俯视 图, 图 9为图 10沿 b-b, 方向的剖面示意图, 需要说明的是, 从图 9中观察, 在本步骤中形成的栅电极层 170位于填充层 160表面并暴露部分填充层 160, 但从图 10中可以发现, 所述栅电极层 170有部分位于层间介质层 140表面, 类似于悬浮桥状, 与栅介质层 150间隔有填充层 160。
参考图 11 , 如步骤 S107所述, 去除填充层 160。
所述去除填充层 160的工艺为选择性腐蚀去除,将器件放置于选择性去除 填充层 160的腐蚀溶液中,腐蚀溶液沿栅电极层 170暴露出的填充层 160腐蚀, 直至去除填充层 160。
去除填充层 160后,所述栅电极层 170位于栅介质层 150上方并与栅介质 层 150之间具有空隙,需要说明的是,栅电极层 170的宽度 dl要比沟道区 113 的宽度 d2大, 当本发明提供的 MEMS器件在开启状态, 能够使得沟道区 113 导通。
本发明提供的一种 MEMS器件及其形成方法,其中 MEMS器件的形成方 法与传统半导体形成工艺兼容, 不需要重新研发新型材料和新的制备工艺, 制 备的 MEMS器件耐压性能高, 栅电极漏电流低。
本发明虽然已以较佳实施例公开如上,但其并不是用来限定本发明,任何 本领域技术人员在不脱离本发明的精神和范围内,都可以利用上述揭示的方法 和技术内容对本发明技术方案做出可能的变动和修改, 因此, 凡是未脱离本发 改、 等同变化及修饰, 均属于本发明技术方案的保护范围。
Claims
1. 一种 MEMS器件, 其特征在于, 包括:
半导体衬底;
形成在半导体衬底内的阱区;
形成在阱区内的源极区、 漏极区和沟道区;
形成在源极区、 漏极区表面的隔离层;
形成在沟道区表面的栅介质层;
形成在栅介质层上方并与栅介质层具有间隙的栅电极层,所述间隙宽度与 沟道区对应。
2. 如权利要求 1所述的 MEMS器件, 其特征在于, 所述栅电极层是单一覆 层或者多层堆叠结构。
3. 如权利要求 1所述的 MEMS器件, 其特征在于, 所述单一覆层栅电极层 的材料为导电材料。
4. 如权利要求 2所述的 MEMS器件, 其特征在于, 所述栅电极层结构为金 属层、形成在金属层表面的氧化硅层和形成在氧化硅层表面的氮化硅层的三层 堆叠结构。
5. 如权利要求 1所述的 MEMS器件, 其特征在于, 所述隔离层是单一覆层 或者多层堆叠结构。
6. 如权利要求 5所述的 MEMS器件, 其特征在于, 所述隔离层包括依次形 成在阱区表面的保护层、 阻挡层和层间介质层。
7. 如权利要求 6所述的 MEMS器件, 其特征在于 所述保护层的材料为氧 化硅。
8. 如权利要求 6所述的 MEMS器件 : 其特征在于 : 所述阻挡层的材料为氮 化硅。
9. 如权利要求 6所述的 MEMS器件 : 其特征在于 : 所述层间介质层材料为 未掺杂的氧化硅或者掺杂的氧化硅。
10. 如权利要求 1所述的 MEMS器件 : 其特征在于, 栅电极层的宽度与沟道 区的宽度对应。
11. 如权利要求 1所述的 MEMS器件 : 其特征在于, 所述源极区和漏极区具 有和阱区相反的导电类型。
12. 一种如权利要求 1所述的 MEMS器件的形成方法, 其特征在于, 包括: 提供半导体衬底, 所述半导体衬底内形成有阱区, 所述阱区内形成有源极 区、 漏极区和沟道区;
在所述半导体衬底表面形成隔离层;
在隔离层内形成开口,所述开口暴露出沟道区和与沟道区相邻的部分源极 区、 漏极区;
在所述开口底部形成栅介质层;
形成填平所述开口的填充层;
在所述层间介质层、 填充层表面形成栅电极层;
去除填充层, 使栅电极层与栅介质层形成间隙。
13. 如权利要求 12所述的 MEMS器件的形成方法, 其特征在于, 所述栅电极 层的形成步骤包括: 在所述层间介质层、 填充层表面形成一层栅电极薄膜; 在 所述栅电极薄膜表面形成与栅电极层对应的光刻胶图形;以所述光刻胶图形为 掩膜, 刻蚀所述栅电极薄膜形成栅电极层。
14. 如权利要求 12所述的 MEMS器件的形成方法, 其特征在于, 所述栅电极 层暴露出部分填充层。
15. 如权利要求 12所述的 MEMS器件的形成方法, 其特征在于, 所述栅电极 层是单一覆层或者多层堆叠结构。
16. 如权利要求 12所述的 MEMS器件的形成方法, 其特征在于, 所述单一覆 层栅电极层的材料为导电材料。
17. 如权利要求 15所述的 MEMS器件, 其特征在于, 所述电极层结构为金属 层、形成在金属层表面的氧化硅层和形成在氧化硅层表面的氮化硅层的三层堆 叠结构。
18. 如权利要求 12所述的 MEMS器件, 其特征在于,栅电极层的宽度与沟道 区的宽度对应。
19. 如权利要求 12所述的 MEMS器件的形成方法, 其特征在于, 填充层的材 料选用与栅电极层和栅介质层具有选择性去除特性的材料。
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