TWI234233B - Method of forming self aligned contact - Google Patents

Abstract

A self-aligned contact method includes, firstly, forming a plurality of stack structures on a semiconductor substrate. The stack structures separate each other and each has a first polysilicon, an insulating layer on the first polysilicon and a second polysilicon on the insulating layer. Secondly, a spacer forms on the sidewall of the stack structures, and then a dielectric layer forms on the stack structures, the spacers and the semiconductor substrate. Finally, the portion of the second poly is used as a buffer for forming contact window by removing a portion of the dielectric layer. The contact window is located between two stack structures.

Description

1234233 —---------- V. Description of the invention (1) 1. [Technical field to which the invention belongs] The present invention relates to a method for automatically aligning a contact window, and particularly to a memory cell manufacturing process. Method of automatically aligning the contact window. 2. [Previous technology] Flash memory is a non-vo Utile semiconductor memory device that uses electrons to inject or pull out floating gates for data storage. At present, Is widely used in information, communications and consumer electronics products. And with the increasing demand for memory capacity and the miniaturization of various electronic products, how to create flash memory architectures and arrays with a low degree of chaos, grain volume, and low battery power consumption has become the main research area. . In terms of current technology, the stack gate structure is commonly used in the manufacture of related memories, because the stack gate structure can have a small accumulation area, and can be used with different design methods to solve various traditional Process problems, for example, in US Pat. No. 5,6 5 8, 8 1 3 mentioned the formation of a stacked gate structure to prevent the active area of the Shi Xi substrate from being destroyed when the dielectric layer is etched. In addition, 'automatic alignment contact window technology' (se 1 ^ — a 1 ignedc ο ntact; SAC) is also widely used in the manufacture of various integrated circuit components, used to form small aperture contact windows and reduce Defective rate of contact window etching. Please refer to Figure A for the SAC process applied to the fabrication of general MOS transistor gates. First, a gate dielectric layer 1 10, a polycrystalline silicon layer 1 2 0, and a tungsten silicide layer 1 3 0 are sequentially formed on a silicon wafer substrate ι0.

Page 5 1234233 V. Description of the invention (2) _ Construct the gate of the transistor MOS, and then form a Khard mask (such as Si3N4) on the tungsten silicide layer 13〇, and pass the appropriate diagram— The steps of shadowing and etching the hard curtain are to remove a part of the stacked gates, and a plurality of stacked gate structures separated from each other. Please make a note; the second and second shapes are formed on the side walls of each stacked gate structure—a gap_ to stop the contact window etching and avoid conduction ^, and to use a wide range (such as S bay to cover the entire stack interlayer structure, the gap between the two Finally, as shown in the first C diagram, the contact window is automatically engraved with anisotropy and ~ ^ Iry etching), and the two are equal to the diameter of the inter-stack structure, because Si3N4 is relative to Si 〇22 = 22 select ratio 'make hard curtain cover "and gap I 15. Not easy to be: ^ = a barrier effect, so that the contact window 17〇 can be completely etched pan silicon« substrate 1 00 surface without damaging the stacked gate structure. The precision and miniaturized integrated circuit manufacturing process of Mianlang, the above-mentioned automatic alignment contact surplus technique can not only effectively reduce the wire diameter, but also avoid exposure without etching during the lithography process. Time misalignment (mis-al ignment) and short and open caused by incomplete etching.

Generally, the structure of a flash memory cell is mainly composed of a doped semiconductor substrate, an edge layer, a floating gate, and a control gate (c η ^ Γ 〇 1 g a ^ e). The floating gate is used to inject or remove electrons, and the control gate is used to control the voltage of the element line (b i 1: 1 i n e). Please refer to the second figure, which shows the structure of general P-channel flash memory cells. On a silicon wafer substrate 200, a gate dielectric layer 2 1 0, a first polycrystalline silicon layer 2 2 0,

Page 6 1234233 V. Description of the invention (3) A stacked structure composed of an insulating layer 2 3 0 and a second polycrystalline silicon layer 2 4 0, and a plurality of separated stack gates are formed after appropriate lithography and etching processes. Pole structure 2 5 0. Next, a gap layer 2 60 is formed on the sidewall of each stacked gate structure 250, and a dielectric layer 2 70 is formed to cover the entire stacked gate structure 2 50, and fill the stacked gate structure 2 50 gap. Finally, the contact window 280 is etched. This is the contact window process in the traditional flash memory cell. 3. Summary of the Invention One of the purposes of the present invention is to use a polycrystalline silicon layer that is not used in the memory cell as a buffer layer when the contact window is engraved, that is, to replace the role of the traditional hard curtain layer. Another object of the present invention is to use an auto-aligned contact window method for contact window etching, and use a polycrystalline silicon layer that is not used by memory cells as a buffer layer during contact window etching, so as to reduce the contact window aperture and improve the process. grade. The invention is an automatic alignment contact window technology using a polycrystalline silicon layer as a buffer layer. First, a plurality of stacked structures are formed on a semiconductor substrate. Each stacked structure is separated from each other and includes a first polycrystalline silicon layer, an insulating layer, and a second polycrystalline silicon layer. The insulating layer is formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer is formed over the insulating layer. A gap layer is then formed on the sidewalls of each stacked structure, and a dielectric layer is formed on the plurality of stacked structures, the plurality of gap layers and the semiconductor substrate. A part of the second polycrystalline silicon layer is used as a buffer layer, and a part of the dielectric layer is removed to form a contact window between the two stacked structures.

1234233 V. Description of the invention (4) IV. [Embodiments] Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can be widely implemented in other embodiments. That is, the scope of the present invention is not limited by the proposed embodiments, but should be based on the scope of patent applications filed by the present invention. Moreover, in this specification, different parts of the semiconductor element are not drawn according to dimensions. Certain dimensions have been exaggerated compared to other related dimensions to provide a clearer description and understanding of the invention. The third diagrams A to C show the first embodiment of the present invention. Please refer to the third diagram A. First, a gate dielectric layer 3 1 0 is formed on a semiconductor substrate 300. The semiconductor substrate 3 0 0 can be a doped silicon wafer, and the gate dielectric layer 3 1 0 It can be a silicon dioxide layer (S i 0 2). Next, a first polycrystalline silicon layer 3 2 0 is formed over the gate dielectric layer 3 1 0. The first polycrystalline silicon layer 32 0 can be formed by chemical vapor deposition (CVD for short). It is used as the floating gate in the memory cell, the gate electrode of the general transistor control element, or even not used for control. An insulating layer 3 3 0 is formed on the first polycrystalline silicon layer 3 2 0 to prevent conduction between the two gates. In this embodiment, the insulating layer 3 3 0 is an oxide layer-nitride stone. -Structure composed of oxide-nitride-oxide (referred to as 0N0), such as a Si 02 / Si 3N4 / Si 02 structure, S i 3 Ν 4 in this ΝΟΟ structure is used to increase the ability to isolate impurities to avoid leakage current , And can slightly increase the dielectric constant value, Si 02 is used to improve the nitride

1234233 V. Description of the invention (5) The problem of poor interface properties between (nitride) and Shi Xicai Finally, a second polycrystalline silicon layer 3 4 0 is formed over the insulating layer 3 3 0. This second polycrystalline silicon The layer 3 40 can be formed by chemical vapor deposition, and is used as a control gate in a memory cell or a blank gate not used for control. The gate dielectric layer 3 1 0, the first polycrystalline silicon layer 3 2 0, the insulating layer 3 3 0, and the second poly silicon layer 3 4 0 constitute a stacked structure in the memory cell. In addition, a dielectric layer 3 95 can be formed between the insulating layer 3 3 0 and the second polycrystalline silicon layer 3 4 0 as a mask for etching the insulating layer. Then, the lithography and etching steps of pattern transfer are performed on the stacked structure, and the stacked structures 3 8 0, 3 8 5 and 3 9 0 which are separated from each other are formed by removing part of the stacked structure. The etched portion includes a gate oxide layer 3 1 0, a first polycrystalline silicon layer 3 2 0, an insulating layer 3 3 0, and a second polycrystalline silicon layer 3 4 0, and a portion of the semiconductor substrate is exposed after the etching. The surface of the material 300, the structure after etching is as shown in the third A figure. The above-mentioned lithography and etching steps for pattern transfer of the stacked structure are known techniques, so they will not be described in detail in this embodiment and the drawings. Instead, the stacked structures are formed by etching directly as shown in the drawings. The stacked structures 3 8 0, 3 8 5 and 3 9 0. Among them, the position of the first polycrystalline silicon layer 3 2 0 in the stacked structures 3 8 0 and 3 8 5 may be a gate electrode of a general transistor control element or not used for control, so the second polycrystalline silicon layer 3 The 40 positions are regarded as a dummy gate. On the other hand, the stacked structure 390 is used as a memory cell. The first polycrystalline silicon layer 3 3 0 is used as a floating gate, and the second polycrystalline silicon layer 3 4 0 is used as a control.

1234233 V. Description of the invention (6) 'The use of control gate. After the lithography and etching steps of the pattern transfer are completed, the semiconductor substrate 300 can be ion implanted to form a source and a drain of the memory element. ) On the semiconductor substrate 300. Similarly, the electrical properties of the source, drain, and regions are not shown in the figure. Then please refer to the third figure B. After the ion implantation is completed, in order to avoid the conduction phenomenon on the side walls of the stacked structures 380, 385, and 390, the stack structures 380, 385, and A gap layer 350 is formed on the side wall of 390 as insulation, and can be used as a stop layer when etching the contact window in the future. The gap layer 3 50 is formed by first uniformly forming the gap layer material by chemical vapor deposition on the surfaces, sidewalls, and exposed semiconductor substrates of the stack carryover 3 8 0, 3 8 5 and 3 9 0. On the surface of the material 3000, the surface direction portion can be removed by anisotropic dry etching. In this embodiment, the gap layer 3 5 0 y is considered to be silicon nitride (Si 3 N 4) or a multilayer structure composed of an oxide layer and a nitride layer. Next, a dielectric layer 360 is formed to cover the stacked structures 380, 385, and 390, and fill the gaps between the stacked structures 380, 385, and 390. The dielectric layer 360 can be a silicon dioxide layer. Finally, the step of touching the window 370 for money. It is known from the foregoing that in each f-stack structure, the portion corresponding to the position 32 of the first polycrystalline silicon layer may be a gate electrode of 2 memory_cells or not used for control, especially around the contact window 3 70 Most of the floating gates are not used to inject or eliminate electrons, but are used as a selection gate as a buffer for the remaining floating gates.

1234233 V. Description of the invention (7) ~ ^-The second polycrystalline silicon layer 3 40 located above the selection gate becomes a useless blank gate, such as stacked structures 3 0 0 and 3 8 5. In the present invention, #P in spear uses this unused polycrystalline silicon layer as a buffer layer for contact window etching, so that a larger aperture range can be used to etch a contact window with a small aperture range. It is the use of automatic alignment window technology to reduce the contact window of small area ^ diameter in the lithography process is not easy to expose or easy to make mistakes during etching. As shown in FIG. 3C, the lithography step is first performed on the dielectric layer 3 60, and then the dielectric layer 3 6 0 is etched by using a dry isotropic dry etching to set a larger aperture range. During the etching process, in order to reach the extra etching range ==, the blank gate and gap layer 3 50 used as a buffer will be etched ^, eliminated. However, due to the complex silicon and silicon nitride pairs Because the silicon dioxide has a high etching selectivity t (etching selectivity), the structure of silicon dioxide = two, the layer 3 60 will be easier to etch than the blank gate and the gap layer 3 5 0. Second, even if the position alignment is slightly shifted during the etching, the connection can be successfully completed. ^ No 9 The problem of insufficient etching or over-etching occurs. At most 37, the contact window plug 3 75 is in the contact window 37, so that the contact window plug 3 75 and the semiconductor substrate 300 are electrically connected. Fansai: to illustrate another embodiment of the present invention, as shown in the fourth figure, a semiconductor substrate 400 is simulated according to 4, ^, and ΟΛ is formed in sequence-the gate dielectric layer 410, the first compound crystal layer 4 2 0, the insulating layer 4 3 0, and the first and the pattern transfer of the lithography, the column = the post-crystal stone evening | 440, after appropriate steps, the formation of separation from each other Stacked structure 1234233 V. Description of the invention (8) structure. In addition, a dielectric layer 495 can be formed between the insulating layer 430 and the second polycrystalline silicon layer 440 to serve as a mask for etching the insulating layer. Next, a gap layer 450 is formed on the sidewall of each stacked polycrystalline silicon structure, and a barrier layer 460 is formed on the semiconductor substrate 400, the stacked polycrystalline silicon structure and the gap layer 450, and then A dielectric layer 47 is formed over the barrier layer 46 0 in a blanket manner. Finally, the unused blank gate electrode is used as a buffer layer, and the contact window 480 is etched by the automatic alignment window technology, and a contact window plug 4 8 5 is formed in the contact window 480 to make the contact window The plug 4 8 5 is electrically connected to the semiconductor substrate 4 0 0. The barrier layer 460 may have an oxide layer structure, a nitride layer structure, or a multilayer structure composed of an oxide layer and a nitride layer. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application of the present invention. Changes can be made and implemented without departing from the essence of the invention, and such changes should still fall within the scope of the invention. Therefore, the scope of the present invention is defined by the following patent applications.

Page 121234233 Schematic diagram Schematic diagram t t Λ Wu Ming said that the simple application system S ο Μ volume crystal electricity is shown in the system as shown in Figure C. The first to schematic equation system knowledge window touches the mind Recording memory, remembering flash, and fast technique are shown in the technical display window. Figures 3A to 3C shown in Figure 2 are examples of the automatic alignment window technology of the polycrystalline silicon buffer of the present invention. formula. The fourth figure shows another embodiment of the automatic alignment window technology of the polycrystalline silicon buffer of the present invention. Explanation of symbols: 1 0 0 silicon wafer substrate 1 1 0 gate dielectric layer 1 2 0 polycrystalline silicon layer 1 3 0 stone Xihuan layer 1 4 0 hard curtain layer 1 5 0 gap layer 1 6 0 medium Electrical layer 1 70 Contact window 2 0 Silicon wafer substrate 2 1 0 Gate dielectric layer 2 2 0 First complex silicon layer 2 3 0 Insulating layer 2 4 0 Second complex silicon layer

Page 13 1234233 Brief description of the drawing 2 5 0 Stacked gate structure 2 6 0 Gap layer 2 7 0 Dielectric layer 2 8 0 Contact window 3 0 0 Semiconductor substrate 3 1 0 Gate dielectric layer

3 2 0 first polycrystalline silicon layer 3 3 0 insulating layer 3 4 0 second polycrystalline silicon layer 3 5 0 gap layer 3 6 0 dielectric layer 3 7 0 contact window 3 7 5 contact window plug 3 8 0 stack Structure 3 8 5 Stacked structure 3 9 0 Stacked structure 3 9 5 Dielectric layer 4 0 0 Semiconductor substrate 4 1 0 Gate dielectric layer

4 2 0 First polycrystalline silicon layer 4 3 0 Insulating layer 44 0 Second polycrystalline silicon layer 4 5 0 Gap layer 4 6 0 Barrier layer

Page 14 1234233 Brief description of drawings 4 7 0 Dielectric layer 4 8 0 Contact window 4 8 5 Contact window plug 4 9 5 Dielectric layer

Claims (1)

1234233 6. Scope of patent application 1. A method for forming an automatic alignment contact window, comprising: providing a semiconductor substrate; forming a plurality of stacked structures on the semiconductor substrate, each of the stacked structures being separated from each other and including a first A polycrystalline silicon layer, an insulating layer on the first polycrystalline silicon layer, and a second polycrystalline silicon layer on the insulating layer; forming a gap layer on a sidewall of each of the stacked structures; forming a dielectric An electrical layer on the plurality of stacked structures, the plurality of gap layers and the semiconductor substrate; and Taking part of the second polycrystalline silicon layer as a buffer layer, removing part of the dielectric layer to form a contact window between part of the two stacked structures. 2. The method for forming an auto-aligned contact window as described in item 1 of the patent application scope, wherein the insulating layer includes an oxide layer. 3. The method of forming an auto-aligned contact window as described in item 1 of the scope of the patent application, wherein the insulating layer includes a nitride layer. 4. The method for forming an auto-aligned contact window as described in item 1 of the scope of the patent application, wherein the insulating layer includes an oxide layer-nitride layer-oxide layer (ONO) structure. 5. The method for forming an automatic alignment contact window as described in item 1 of the scope of the patent application, further comprising forming a dielectric layer between the insulating layer and the second polycrystalline silicon layer. Page 16 1234233 6. Scope of patent application 6. The method for forming an auto-aligned contact window as described in item 5 of the scope of patent application, wherein the gate dielectric layer includes a silica. 7. The method of forming an auto-aligned contact window as described in item 1 of the patent application scope, wherein the gap layer includes a nitride layer. 8. The method of forming an auto-aligned contact window as described in item 1 of the patent application scope, wherein the gap layer includes a multi-layer structure composed of an oxide layer and a nitride layer. 9. The method for forming an automatic alignment contact window as described in item 1 of the scope of patent application, wherein the plurality of stacked structures further comprises forming a gate dielectric layer on the semiconductor substrate and the first polycrystalline silicon layer between. 10. The method for forming an automatic alignment contact window as described in item 1 of the scope of patent application, further comprising forming a contact window plug in the contact window, wherein the contact window plug is electrically conductive with the semiconductor substrate. On the connection. 11. An automatic alignment contact window method for polycrystalline silicon buffer, comprising: providing a semiconductor substrate; forming a plurality of stacked structures on the semiconductor substrate, each of the stacked structures being separated from each other and including a first compound crystal A layer, an insulating layer on the first polycrystalline silicon layer, and a second polycrystalline silicon layer on the insulating layer, some of which Page 171234233_ 6. Scope of patent application The plurality of second compound crystal layers are a plurality of dummy gates; a gap layer is formed on a side wall of each of the stacked structures; a barrier is formed Layers on the plurality of stacked structures, the plurality of gap layers and the semiconductor substrate; a blanket (b 1 anket) forms a dielectric layer on the barrier layer; the plurality of blank gates serve as a buffer layer, Removing a portion of the dielectric layer to form a contact window between any two of the stacked structures including the blank gate electrode; and forming a contact window plug in the contact window, wherein the contact window plug and the semiconductor The substrate is electrically connected. 12. The method for automatically aligning a contact window of a polycrystalline silicon buffer according to item 11 of the patent application scope, wherein the insulating layer includes an oxide layer. 13. The method for automatically aligning a contact window of a polycrystalline silicon buffer as described in item 11 of the scope of the patent application, wherein the insulating layer includes an oxide layer-nitride layer-oxide layer (ONO) structure. 14. The method for automatically aligning a contact window of a polycrystalline silicon buffer as described in item 11 of the scope of the patent application, further comprising forming a silicon dioxide layer between the insulating layer and the second polycrystalline layer. 1 5 · Automatic alignment of polycrystalline silicon buffer as described in item 11 of the scope of patent application Page 18 1234233 VI. Scope of Patent Application The contact window method, wherein the gap layer includes a nitride layer. 16. The method for automatically aligning a contact window of a polycrystalline silicon buffer as described in item 11 of the scope of the patent application, wherein the gap layer includes a multilayer structure composed of an oxide layer and a nitride layer. 17. The method for automatically aligning a contact window of a polycrystalline silicon buffer as described in item 11 of the patent application scope, wherein the barrier layer comprises an oxide layer. 18. The method for automatically aligning a contact window of a polycrystalline silicon buffer according to item 11 of the scope of the patent application, wherein the barrier layer includes a nitride layer. 19. The method for automatically aligning a contact window of a polycrystalline silicon buffer according to item 11 of the scope of the patent application, wherein the barrier layer includes a multilayer structure composed of an oxide layer and a nitride layer. Page 19