Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates

Definitions

• the present invention relates to integrated circuit memory devices and, in particular to a 5-transistor non-volatile memory (NVM) cell that facilitates an increase in the voltage difference between the floating gate of a programmed NVM cell in an NVM cell array and the floating gate of a non-programmed NVM cell in the array.
• NVM non-volatile memory
• U.S. Patent No. 7,164,606 Bl which issued on January 16, 2007, to Poplevine et al., discloses an all-PMOS 4-transistor non-volatile memory (NVM) cell that utilizes reverse Fowler-Nordheim tunneling for programming.
• NVM non-volatile memory
• Fig. 1 as disclosed in U.S. Patent No. 7,164,606, in accordance with the method of programming an NVM array that includes all-PMOS 4-transistor NVM cells having commonly-connected floating gates, for each cell in the array that is to be programmed, all of the electrodes of the cell are grounded. Then, an inhibiting voltage V n is applied to the bulk-connected source region V r of the cell's read transistor P r , to the commonly-connected drain, bulk and source regions V e of the cell's erase transistor P e , and to the drain region D r of the read transistor P r . The source region V p and the drain region D p of the cell's programming transistor P w are grounded.
• the bulk V nw of the programming transistor P w is optional; it can be grounded or it can remain at the inhibiting voltage V n .
• the inhibiting voltage V n is applied to electrodes V r , V e and D r and is also applied to electrodes V p , D p and V nw .
• the control voltage V c of the cell's control transistor P c is then swept from 0V to a maximum programming voltage V cmax in a programming time Tprog.
• the control gate voltage V c is then ramped down from the maximum programming voltage V cmax to 0V. All electrodes of the cell and the inhibiting voltage V n are then returned to ground.
• the all-PMOS 4-transistor NVM cell disclosed therein relies on reverse Fowler-Nordheim tunneling for programming. That is, when the potential difference between the floating gate electrode of the programming transistor of an all-PMOS NVM cell and the drain, source and bulk electrodes of the programming transistor exceeds a tunneling threshold voltage, electrons tunnel from the drain and source electrodes to the floating gate, making the floating gate negatively charged.
• the '606 patent provides advantages of both low current consumption, allowing the ability to simultaneously program a large number of cells without the need for high current power sources, and a simple programming sequence.
• the drain and source regions of the read transistor P r and of the programming transistor P w of non-programmed NVM cells in the array are set to a fixed inhibiting voltage V n
• the V e electrode of the erase transistor Pe is set to the inhibiting voltage V n
• the V c electrode of the control transistor P c is ramped up from 0V to Vcmax-
• negative charge is trapped on the floating gate of the non- programmed cells, even though the amount of trapped charge is less than the negative charge that is trapped on the floating gate of the programmed cells.
• the present invention provides a method of programming a non-volatile memory (NVM) cell array that includes a plurality of NVM cells.
• NVM non-volatile memory
• Each NVM cell in the array includes an NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to a storage node, a PMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the storage node, an NMOS data transistor having source, drain and bulk region electrodes and a gate electrode connected to the storage node, the bulk region electrode being connected to a common bulk node, a first NMOS pass gate transistor having a source electrode connected to the drain electrode of the NMOS data transistor, a drain electrode connected to a first array bit line, a bulk region electrode connected to the common bulk node and a gate electrode connected to a first array word line, and a second NMOS pass gate transistor having a drain electrode connected to the source electrode of the NMOS data transistor, a source electrode
• the NVM cell array programming method comprises: for each NVM cell in the array, setting the source, drain, bulk region and gate electrodes of the NMOS control transistor, the PMOS erase transistor and the NMOS data transistor of the NVM cell to 0V; for each cell in the array selected for programming, setting the first array word line to a positive inhibiting voltage and the corresponding second bit line to 0V, or setting the second array word line to the positive inhibiting voltage and the corresponding second bit line to 0V, or both, and setting the common bulk node to 0V; for each cell in the array not selected for programming, setting the first and second array word lines to 0V while setting either the first or second array bit line (or both) to the positive inhibiting voltage or 0V, and setting the common bulk node to Ov; ramping up the control voltage from 0V to a positive control voltage and the erase voltage from 0V to a positive erase voltage for a predefined programming time; ramping down the control voltage from the positive control voltage to 0V and the erase voltage from the positive
• Fig. 1 is a schematic diagram illustrating an all-PMOS 4-tranistor NVM cell.
• Fig. 2 is a schematic diagram illustrating an embodiment of a 5 -transistor NVM cell in accordance with the concepts of the present invention.
• Fig. 3 is a cross-section drawing illustrating the Fig. 1 all-PMOS 4-transistor NVM cell.
• FIG. 4 is a cross-section drawing illustrating a structural embodiment of the Fig. 2 a 5-transistor NVM cell in accordance with the concepts of the present invention.
• FIG. 5 is a cross-section drawing illustrating an alternate structural embodiment of the Fig. 2 5-transistor NVM cell in accordance with the concepts of the present invention.
• Fig. 6 is a schematic diagram illustrating an embodiment of an NVM cell array comprising a plurality of 5-transitor NVM cells of the type illustrated in Fig. 2.
• Fig. 2 shows an embodiment of a 5-transistor non-volatile memory (NVM) cell 200 in accordance with the concepts of the present invention that advantageously modifies the all-PMOS 4-transistor NVM cell 100 shown in Fig. 1. More specifically, the 5-transistor NVM cell 200 replaces the PMOS control transistor P c of the all-PMOS cell 100 with an NMOS control transistor N c having commonly-connected source, drain and bulk region electrodes that receive a control voltage V c ; the gate electrode of the NMOS control transistor N c is connected to a storage node N s .
• NVM non-volatile memory
• the NVM cell 200 also includes a PMOS erase transistor P e having commonly-connected source, drain and bulk region electrodes that receive an erase voltage V e ; the gate electrode of the of the erase transistor P e is connected to the storage node N s .
• the Fig. 2 5-transistor NVM cell 200 replaces the PMOS read transistor P r and the PMOS program transistor P w of the Fig. 1 all-PMOS NVM cell 100 with a single NMOS data transistor N d that has its gate electrode connected to the storage node N s .
• the 5-transistor NVM cell 200 also includes a first NMOS pass gate transistor PGl and a second NMOS pass gate transistor PG2.
• the first NMOS pass gate transistor PGl is connected between the source electrode of the data transistor Nd and a first NVM cell array bit line Bl ; the gate electrode of the first NMOS pass gate transistor PGl is connected to a first NVM cell array word line Wl .
• the second NMOS pass gate transistor PG2 is connected between the drain electrode of the data transistor N d and a second NVM cell array bit line B2; the gate electrode of the second NMOS pass gate transistor PG2 is connected to a second NVMN cell array word line W2.
• the bulk region electrodes of the data transistor N d , the first NMOS pass gate transistor PGl and the second NMOS pass gate transistor are commonly-connected to receive a bulk region programming voltage V pw .
• FIG. 3 shows a cross section of the Fig. 1 all-PMOS 4-transistor NVM cell 100 with large N-well spacing between the PMOS transistors.
• Fig. 4 shows a cross section of the Fig. 2 5-transistor NVM cell 200. As shown by the dashed vertical lines in Figs. 1 and 2, the Fig. 2 5-trannsitor NVM cell 200 has a more compact design than the Fig. 1 all-PMOS NVM cell 100.
• Fig. 4 also shows that the NMOS control transistor N c of the Fig. 2 NVM cell is built in an isolated P-well 400.
• Fig. 1 shows a cross section of the Fig. 1 all-PMOS 4-transistor NVM cell 100 with large N-well spacing between the PMOS transistors.
• Fig. 4 shows a cross section of the Fig. 2 5-transistor NVM cell 200. As shown by the dashed vertical lines in Figs. 1 and 2, the Fig. 2 5-trannsitor NVM cell
• Fig. 4 further shows that the bulk (substrate) regions of the NMOS data transistor N d , the first NMOS pass gate transistor PGl and the second NMOS pass gate transistor PG2 of the NVM cell 200 are commonly connected via the P-substrate 402.
• Fig. 5 shows a cross section of an alternate embodiment of the NVM cell 200 wherein the commonly-connected bulk regions of the NMOS data transistor N d , the first NMOS pass gate transistor PGl and the second NMOS pass gate transistor PG2 are formed in an isolated P-well 500.
• the dashed vertical lines in the Fig. 5 alternate embodiment show that it is the same size as the Fig. 4 embodiment and, thus, more compact than the Fig. 3 all-PMOS cell.
• Fig. 6 shows a plurality of 5-transistor NVM cells 200 of the type described above with respect to Fig. 2 incorporated into a NVM cell array 600.
• All electrodes of the cell 200 are set to 0V.
• the first array word line Wl to a positive inhibiting voltage V n and the corresponding first array bit line Bl to 0V, or set the second array word line W2 to the positive inhibiting voltage V n and the corresponding second bit line B2 to 0V , or both; the bulk region electrode V pw is also set to 0V.
• control voltage V c is then ramped down from maximum positive control voltage V cmax to 0V and the erase voltage V e is ramped down from the maximum positive erase voltage V emax to 0V. All cell electrodes in the array that are set to the positive inhibiting voltage V n are then returned to 0V.
• first array word line Wl and the second array word line W2 For each NVM cell 200 in the array 600 to be read, set the first array word line Wl and the second array word line W2 to the positive inhibiting voltage V n and set the first array bit line Bl and the second array bit line B2 to a voltage difference of about IV (e.g., sufficient enough voltage to be able to read the cell current while preventing disturb to the programmed cells). All other electrodes of the cell are set to 0V.
• V n ⁇ 3.3V
• V n ⁇ 5.0V
• adding the first NMOS pass transistor PG1 and the second NMOS pass transistor PG2 to the NVM cell 200 allows the drain and source regions of the NMOS data transistor Na to be floating for non-programmed cells during the programming sequence, as described above, as opposed to being set to a fixed voltage V n in the case of the Fig. 1 all-PMOS NVM cell 100.
• This allows the drain and source regions of the data transistor Nj to rise above the V n level as the control voltage V c and the erase voltage V e are ramped up from 0V to V cmax and V ema x, respectively, during the programming sequence.
• non-programmed cells retain their initial voltage condition (usually the condition after an erase sequence, which is performed before the programming sequence), which is usually at a level of more than V n above that of programmed NVM cells. This means that the maximum possible voltage difference between the floating gate of a programmed NVM cell and the floating gate of a non- programmed NVM cell is usually more than V n .
• the non-programmed cells with this condition are typically referred to as non-disturbed cells.
• the NVM cell 200 Since the voltage difference between the floating gate of programmed NVM cells and the floating gate of non- programmed NVM cells in the case of the 5-transistor NVM cell 200 is larger than the difference in the case of the all-PMOS NVM cell 100, the NVM cell 200 has superior noise margin and data retention time compared to the NVM cell 100. At the same time, the 5-transistor NVM cell 200 still retains the advantages of the reverse Fowler-Nordheim tunneling programming technique of the Fig. 1 all-PMOS NVM cell 100.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Non-Volatile Memory (AREA)
• Semiconductor Memories (AREA)
• Read Only Memory (AREA)

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• 2010
  • 2010-02-08 US US12/702,061 patent/US8284600B1/en active Active
  • 2010-11-29 CN CN201080063339.6A patent/CN102741936B/zh active Active
  • 2010-11-29 JP JP2012552859A patent/JP5632490B2/ja active Active
  • 2010-11-29 WO PCT/US2010/058214 patent/WO2011096978A2/en not_active Ceased
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