Classifications

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  • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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Definitions

• Disclosed embodiments relate to integrated circuits (ICs) including through- substrate vias, such as through silicon vias.
• ICs integrated circuits
• through- substrate vias such as through silicon vias.
• A is the gate activity factor
• C is the total capacitance load of all gates
• V 2 is the peak-to-peak supply voltage swing
• f is the frequency
• I leak is the leakage current.
• the static power term, Ps VIi eak , is the static power dissipated due to leakage current, I leak -
• IC die Another characteristic of IC die is the uneven distribution of temperature on the die. More and more functional blocks are integrated in a single die in system-on-chip (SOC) designs. Higher power density blocks create an uneven temperature distribution and lead to "hotspots,” also known as “hot blocks,” on the die. Hotspots can lead to a temperature difference of about 5 °C to roughly 30 °C across a die. Since carrier mobility is inversely proportional to temperature, the clock speed is typically designed for the hottest spot on the die. Consequently, thermal design is driven by the temperature of these on-die hotspots. Also, if uniform carrier mobility is not achieved across the IC die due to on-chip temperature variations across the die, this may result in variations in signal speed and in complicating circuit timing control.
• SOC system-on-chip
• Heat spreaders including drop-in heat spreaders, heat sinks, and heat pipes have been used in the past to enhance thermal performances of IC packages.
• another known approach is attaching a high thermal conductivity lid directly to the backside of the die to improve heat spreading.
• a significant problem with known practices is that the frontside of the die where the hot spots are located (e.g., near where transistors switching takes place) must be used for wiring and the heat generated during operation must be channeled out through the full thickness of the substrate of the IC die to its bottom side before being connected to heat dissipation means, and are thus inefficient at dissipating heat.
• IC devices comprising a substrate having a top surface including substrate pads, and a TSV die on the top surface of the substrate.
• the TSV die comprises a top side semiconductor surface including active circuitry and a bottom surface, wherein the top side semiconductor surface includes bonding connectors that are coupled to the substrate pads on the top surface of the substrate.
• a plurality of TSVs are on the IC die that comprise an inner metal core that extend from the top side semiconductor surface to protruding TSV tips that extend out from the bottom surface.
• At least one of the plurality of TSVs are "dummy TSVs" defined herein as TSVs having no electrical function for the IC device. Dummy TSVs have their protruding TSV tips exclusive of any electrical connection thereto. Dummy TSVs may be contrasted to conventional functional TSVs, referred to herein as "active TSVs", which include an electrical connection to the TSV tips for providing an electrical function for the IC device, such as for coupling VDD, VSS or signals from the TSV die to other circuitry (e.g., another IC or discretes) above or below the TSV die.
• active TSVs include an electrical connection to the TSV tips for providing an electrical function for the IC device, such as for coupling VDD, VSS or signals from the TSV die to other circuitry (e.g., another IC or discretes) above or below the TSV die.
• Disclosed embodiments provide a higher thermal conductivity path as compared to the conventional thermal paths through the substrate (e.g., Si) of the TSV die that improves heat transfer from the top side of the die to the bottom side of the die.
• the protruding TSV tips significantly increase the surface area on the bottom side of the TSV die that significantly improves radiative heat transfer and thus heat dissipation.
• the invention recognizes that the inner metal core of the TSVs provide reduced thermal resistance for heat transfer from the top side semiconductor surface and the bottom surface because metals such as copper have a thermal conductivity that is higher as compared to most substrate materials.
• metals such as copper have a thermal conductivity that is higher as compared to most substrate materials.
• copper has a thermal conductivity of about 398 W/m-K, as compared to silicon, for example, that has a thermal conductivity of about 168 W/m-K.
• the thermal conductivity of the substrate may be even less for substrates such as semiconductor on insulator (SOI), GaAS, Ge, SiC, and other semiconductors other than bulk Si.
• FIG. 1 is a side view depiction of an IC device comprising a TSV die on a substrate, where the TSV die includes a plurality of dummy TSVs having protruding tips for enhanced heat transfer from the TSV die, according to a disclosed example embodiment.
• FIG. 2 is a side view depiction of an IC device comprising a top side device on a
• TSV die on a package substrate, where the TSV die includes a plurality of dummy TSVs having protruding tips for enhanced heat transfer and a plurality of conventional active TSVs, and where the top side device is coupled to the TSV die by connection to the active TSVs, according to a disclosed example embodiment.
• FIG. 3 is a depiction of a TSV die where the TSVs comprise a plurality of dummy
• TSVs that are arrayed substantially uniformly throughout the TSV die, according to as disclosed example embodiment.
• FIG. 4 is a simplified cross-sectional depiction of a portion of an IC device comprising a TSV die including a TSV array including an active TSV and a plurality of dummy TSV, and a top side device that is coupled to the TSV die by connection to the active TSV, according to a disclosed example embodiment.
• FIG. 5 is a simplified cross-sectional depiction of a portion of TSV die including a TSV array including top surface offset TSVs, according to a disclosed example embodiment.
• FIG. 1 illustrates an example IC device 100 comprising a TSV die 115 on a substrate 110, where the TSV die 115 includes a plurality of dummy TSVs 120 having protruding TSV tips 121 that provide additional surface area on the bottom surface 106 of the TSV die 115 for enhanced heat transfer from the TSV die, according to a disclosed embodiment.
• TSV die comprises a semiconductor-comprising substrate 105 including a top side semiconductor surface 107 and a bottom surface 106.
• the top side semiconductor surface 107 is shown including bonding connectors 109 shown as pillars (e.g., copper pillars, that may be solder capped), that are connected to bond pads (not shown) on the TSV die 115.
• the substrate 105 can comprise a variety of substrates such as silicon-comprising substrates (e.g., bulk silicon substrate), silicon germanium, silicon carbide, GaN, or a silicon on insulator (SOI) substrate.
• substrates such as silicon-comprising substrates (e.g., bulk silicon substrate), silicon germanium, silicon carbide, GaN, or a silicon on insulator (SOI) substrate.
• dummy TSVs are TSVs having no electrical function for the IC device 100, since their protruding TSV tips are exclusive of any electrically connection thereto. Dummy TSVs may be contrasted to conventional active TSVs which include an electrical connection to the TSV tips for providing an electrical function for the IC device, typically transmitting VSS, VDD or signals to devices above or below the TSV die. As shown in FIG. 1, all the TSVs are dummy TSVs 120.
• the length (or tip height) of the protruding TSV tips 121 is typically from 5 to 50 ⁇ , and the cross- sectional area defining dimension (e.g., diameter) of the TSVs 120 is generally from 8 to 40 ⁇ .
• TSVs are generally described herein as having a circular cross section, TSVs can have other cross- sectional shapes including rectangular or square, for example.
• the substrate 110 is shown as a printed circuit board (PCB) substrate having a ball grid array (BGA) 111.
• substrate 110 can comprise a variety of other substrates, such as an organic substrate, a ceramic substrate, a silicon substrate, or a silicon interposer.
• the substrate 110 includes substrate pads 112 that are coupled to bonding connectors 109 shown as pillars on the TSV die 115.
• the plurality of dummy TSVs 120 are shown comprising an inner metal core 125 that extends from the top side semiconductor surface 107 to protruding TSV tips 121 that extend out from the bottom surface 106.
• the plurality of dummy TSVs 120 are also shown including a dielectric liner 126.
• the dielectric liner 126 is seen to be absent from the TSV tips 121, and is more generally absent from at least 50% of the length of the TSV tips 121.
• FIG. 2 illustrates an IC device 200 comprising a top side device 230 on a TSV die
• Top side device 230 can include at least one IC that is coupled to the plurality of active TSVs 130.
• Top side device 230 can also comprise devices other than ICs, such as comprising capacitors, resistors, etc. to provide a stack referred to in the art as "integrated heterogeneous chip integration".
• IC device 200 and other IC devices herein are shown without a lid. However, in other embodiments a lid is included.
• a lid can be attached in a variety of ways including using thermally conductive adhesive paste, sheet, grease or a thermally conductive adhesive. Solder paste with reflow is another example attachment option.
• FIG. 3 illustrates a TSV die 300 where the TSVs comprise a plurality of dummy
• TSVs 120 that are arrayed substantially uniformly throughout the area (in both the x-direction and the y-direction) of the TSV die 300, according to as disclosed embodiment.
• the TSVs in one particular embodiment can have 25 ⁇ diameters and be positioned to provide a 50 ⁇ center-to-center pitch.
• the dummy TSVs 120 are shown being columnar in shape having a square cross section. For a square die that is 5 mm on a side, such a TSV die can accommodate 10,000 TSVs.
• TSV die 300 includes an array of dummy TSVs that is periodic, the dummy TSVs may also be positioned in a non-periodic pattern.
• dummy filled TSVs may be placed in close proximity to circuit hot spots, where, according to IC modeling or experience, high frequency and intense circuit integration cause extraordinary temperature increases during circuit operation.
• Such dummy TSV placements provide direct, short-cut paths for heat dissipation from the circuit, dummy TSVs can thus keep the IC device operating reliably in safe temperature regions.
• FIG. 4 illustrates a portion of an IC device 400 comprising a TSV die 315 including a TSV array including an active TSV 130 and a plurality of dummy TSVs 120, and a top side device 230 that is coupled to the TSV die 315 by connection to the active TSV 130, according to a disclosed embodiment.
• TSV die 315 comprises a semiconductor substrate 105 having a top surface 107, such as a silicon or silicon germanium surface, and a bottom surface 107.
• TSV die 315 includes a plurality of metal interconnect levels generally comprising copper including an example back end of the line (BEOL) stack comprising first to seventh metal interconnect levels shown as M1-M7.
• BEOL back end of the line
• BEOL arrangement M1-M7 can comprise copper and a top (8 th ) metal level 417 that can comprise aluminum shown used to also form pillar pad 328, so that the BEOL stack can be referred to as an 8 level metal stack.
• a top (8 th ) metal level 417 that can comprise aluminum shown used to also form pillar pad 328, so that the BEOL stack can be referred to as an 8 level metal stack.
• disclosed embodiments can be applied to BEOL stacks generally comprising any number of metal levels, that may or may not have a top metal level 417.
• a pre-metal dielectric (PMD) 239 is shown between the top surface 107 and Ml, and ILD layers comprising ILD1, ILD2, ILD3, ILD4, ILD5 and ILD6 shown comprising dielectric material that is positioned between respective ones of the plurality of metal interconnect levels Ml to M7, with ILD7 between M7 and the top metal level 417 that includes pillar pad 328.
• the ILD material can comprise a low-k dielectric or an ultra low-k dielectric layer, and be different (or the same) material for each of the ILD1, ILD2, ILD3, ILD4, ILD5, ILD6 and ILD7 layers.
• the TSV die 315 shows the TSVs 120, 130 all terminating at Ml that defines their TSV terminating metal interconnect level
• the TSV terminating metal interconnect level can terminate at metal levels above Ml, including the top metal interconnect level (M7 shown in FIG. 4).
• Active circuitry shown as transistor 218 is formed on the top surface 107 adjacent to one of the dummy TSVs 120.
• transistor 218 is coupled to other devices or components on the TSV IC 315 by one of the many possible connection options comprising Ml, M2, M3 and M4, etc. and associated vias as shown in FIG. 4.
• the active TSV 130 can be seen providing a feed through the substrate 105 for connection to top side device 230 on top surface 106 of the TSV die 315, which is coupled to pillar 109 on pillar pad 328, with pillar 109 coupled as shown to a pillar pad 112 on substrate 110.
• the tips 121 of the dummy TSVs 120 can be seen to be electrically unconnected. Since dummy TSVs 120 are shown embedded below and terminating at Ml, the volume above dummy TSVs 120 becomes available for routing interconnect metal lines.
• TSV IC 315 is shown including an M4 routing lines 251 and M6 routing lines 252 above dummy TSVs 120.
• TSVs 120 and 130 comprise TSV inner metal core 125 (e.g., copper) that can be seen to extend from Ml which functions as the TSV terminating metal interconnect level downward through the bottom surface 107.
• the inner metal core 125 is shown surrounded by diffusion barrier metal (e.g., Ta, TaN, Ti, TiN, Mn, or Ru, or combinations thereof) 129 then by an outer dielectric liner (e.g., SiCh, PSG, or SiN, or combinations thereof) 126.
• diffusion barrier metal e.g., Ta, TaN, Ti, TiN, Mn, or Ru, or combinations thereof
• outer dielectric liner e.g., SiCh, PSG, or SiN, or combinations thereof
• the diffusion barrier metal 129 formed on the dielectric liner 126 frames the TSVs 120, 130 and protects against escape of the TSV inner core 125 material into the substrate 105 in the case of highly mobile metal TSV core materials that are known to significantly reduce minority carrier lifetimes, such as copper in silicon, and cause problems such as significantly increased junction leakage or a shift in transistor threshold voltage (Vt).
• highly mobile metal TSV core materials that are known to significantly reduce minority carrier lifetimes, such as copper in silicon, and cause problems such as significantly increased junction leakage or a shift in transistor threshold voltage (Vt).
• Via-first, related via-middle, and via-last processes may be used to form disclosed TSV ICs.
• the via-first scheme describes a sequence in which substrate (e.g., silicon) through- vias are etched from the frontside of the wafer before wafer thinning, and are dielectrically insulated, and then metalized before the BEOL interconnect wiring levels are built.
• Conventional via-first processes forms the TSVs before formation of the transistors.
• a variant of the via-first process is the via-middle process where TSVs are etched and filled with an electrically conductive inner metal core after formation of the transistors but before the completion of the BEOL wiring levels.
• the BEOL wiring levels are built first, and the through-via steps are completed either by etch and inner metal core fill processing from the top side after BEOL wiring and before wafer thinning, or to the bottom side of the wafer subsequent to BEOL wiring and wafer thinning.
• the TSVs in one embodiment are "top surface offset TSVs" that are defined herein as TSVs that include TSV tips protruding from the bottom side of the TSV die that extend for > 85 % of the thickness of the semiconductor-comprising substrate, but do not reach the top surface of the substrate, such as being 2.5 to 8 ⁇ away from the top surface of the substrate.
• the thickness of the wafer may be about 30 to 50 ⁇ after wafer thinning (e.g., backgrind), for example, which is generally performed before via-last TSV etch.
• the target etch depth in this embodiment depends on the substrate (e.g., silicon) thickness, its thickness non-uniformity across the wafer, and the capability (etch uniformity) of the etch tool used. Reducing the distance from the TSV to the top surface improves cooling efficiency. In this embodiment all TSVs are dummy TSVs. Top surface offset TSVs allow arbitrary placement of transistors and metal routing, thus allowing enhanced cooling without loss of available die area.
• FIG. 5 is a simplified cross- sectional depiction of a portion of TSV die 500 including a TSV array including top surface offset TSVs 520, according to a disclosed embodiment.
• the TSVs 520 can be seen to terminate below the top surface 107 below the vertical extent of the diffusions associated with transistor 218 and other devices on the TSV die 500.
• Transistor 218 is shown above the TSV identified as TSV 520'.
• TSV die 500 shows how top surface offset TSVs allow circuitry (e.g., transistors, diodes resistors, etc.) to be formed in or on the top surface 107 of the TSVs, thus allowing enhanced cooling without the loss of available area on TSV die 500.
• circuitry e.g., transistors, diodes resistors, etc.
• TSV die 500 having top surface offset TSVs 520 is provided, described for a copper inner metal core process.
• Via-last vias for the TSVs are formed by a suitable etch process, followed by an optional dielectric liner deposition, then a barrier layer and seed deposition, and then electrochemical copper is deposited to fill the vias with a recipe that results in a relatively thin field (lateral to the TSV vias) deposition.
• the copper and barrier layer on the field regions can then be removed (e.g., wet strip or CMP), followed by a conventional substrate (e.g., silicon) dry etchback to create protruding TSV tips that extend out from the bottom surface of the substrate.
• the dry etchback can be used to also recess the dielectric liner (if present).
• Example applications for disclosed embodiments include high power dissipation applications, including analog, power management, and application processors. However, a variety of other applications can benefit from disclosed embodiments.
• the active circuitry formed on the top side semiconductor surface comprises circuit elements that generally include transistors, diodes, capacitors, and resistors, as well as signal lines and other electrical conductors that interconnect these various circuit elements.
• Disclosed embodiments can be integrated into a variety of process flows to form a variety of devices and related products.
• the semiconductor substrates may include various elements therein and/or layers thereon. These can include barrier layers, other dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.
• disclosed embodiments can be used in a variety of processes including bipolar, CMOS, BiCMOS and MEMS.

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• 2010
  • 2010-09-22 US US12/888,135 patent/US8294261B2/en active Active
  • 2010-12-17 WO PCT/US2010/061033 patent/WO2011093956A2/en not_active Ceased
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