CN101292348B - 具有增强的热和器件性能的可堆叠晶片或管芯封装 - Google Patents
具有增强的热和器件性能的可堆叠晶片或管芯封装 Download PDFInfo
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Abstract
本发明提供一种衬底,该衬底具有器件层(210,310)和金属化区(230,315)。在衬底内,提供了导电通孔(270,350)和导热区(260,365)。热传导区可通过到沟槽内的淀积或形成图样而形成。衬底可在堆叠设置中提供。
Description
技术领域
本发明实施例涉及微电子技术。具体地说,本发明实施例涉及热和器件性能增强的堆叠晶片(stacked wafer)或管芯封装(die packaging)。
背景技术
在半导体制造中,晶体管可在半导体晶片上形成。晶体管和其它器件可集成以形成执行许多有用功能的集成电路(IC)。一般情况下,晶片可切割,并且各个IC管芯可封装和销售。为提高IC的性能,提高晶体管的性能可能有利。此外,随着晶体管变得更小、更快和更先进,越来越难以从工作晶体管中散除热量。此外,在晶片或管芯封装中,诸如堆叠式管芯封装等较密集的封装选择可能是有利的。但是,一般的堆叠管芯设置可能不适用于诸如热沉等一般的散热器件。
发明内容
根据本发明的第一方面,提供了一种用于可堆叠晶片或管芯封闭的设备,包括:
金属化区,包括衬底的器件层上的多个金属层;
通孔,延伸通过所述衬底和所述器件层,并接触所述金属化区中的金属层;以及
散热和应力工程区,所述散热和应力工程区在所述器件层上引起应力,并且所述散热和应力工程区位于所述衬底中并与所述器件层相邻。
根据本发明的第二方面,提供了一种用于可堆叠晶片或管芯封闭的设备,包括:
第一有源表面,包括通过互连耦合到第二衬底的第二有源表面的第一衬底的金属化区,其中所述第一衬底包括与所述第一有源表面相邻的散热和应力工程区,并且还包括延伸通过所述第一衬底并接触所述金属化区的金属层的通孔,其中所述散热和应力工程区在所述第一有源层上引起应力;以及
冷却器件,位于与所述第二衬底的有源表面相对的表面上。
根据本发明的第三方面,提供了一种用于可堆叠晶片或管芯封闭的方法,包括:
在衬底表面上提供散热和应力工程层,其中所述衬底表面与所述衬底器件层上的金属化区相对;
显露所述金属化区的金属层,其中显露所述金属层包括提供通过所述散热和应力工程层、所述衬底和有源区的通孔开口;
在所述通孔开口侧壁上提供侧壁绝缘体;以及
在所述通孔开口中提供传导填充。
根据本发明的第四方面,提供了一种用于可堆叠晶片或管芯封闭的方法,包括:
在衬底表面中提供沟槽,其中所述衬底表面与所述衬底器件层上的金属化区相对;
在所述衬底表面和所述沟槽上形成绝缘层;
通过提供通过所述绝缘层、所述衬底和所述器件层的通孔开口而显露所述金属化区;
在所述绝缘层和所述通孔开口上形成第二绝缘层;
显露所述金属化区的金属化层;以及
选择性地在所述沟槽和所述通孔开口中提供传导填充,以便形成所述沟槽中的散热和应力工程区和所述通孔开口中的全通通孔。
附图说明
本发明通过示例方式示出,并不限于所附的附图;附图中,相似的标号表示类似的元件,其中:
图1示出衬底的横截面视图,包括散热和应力工程区(heat spreading and stress engineering region)和连接到具有背侧冷却器件的衬底的通孔。
图2A-2F示出在衬底中形成散热和应力工程区及通孔的方法的横截面视图。
图3A-3H示出在衬底中形成散热和应力工程区及通孔的方法的横截面视图。
图4示出在衬底中包括散热和应力工程区的系统示图。
具体实施方式
在各种实施例中,描述了与堆叠晶片或管芯封装有关的设备和方法。但是,各种实施例可在不存在一个或多个特定细节的情况下实践,或者通过其它方法、材料或组件实践。在其它实例中,熟知的结构、材料或操作未详细示出或描述,以免不混淆本发明各种实施例方面。类似地,为便于解释,陈述了特定的数字、材料和配置以便提供本发明的详尽理解。不过,实践本发明可无需这些特定的细节。此外,要理解,图中所示各种实施例是图示表示,并且不一定按比例画出。
为减小微电子产品的大小,可增大半导体芯片的封装密度。增大封装密度的一个方法可以是堆叠芯片。在操作中,堆叠式芯片的有源区域(active area)可生成大量的热,这可能需要散除,以便芯片可正确地运行。一般情况下,在单芯片封装中,诸如集成的散热片或风扇等背侧冷却器件可用于散除热量。但是,在堆叠式布置中,由于空间约束或与电气连接定线(connection routing)不兼容的原因,为堆叠中的每个芯片使用背侧冷却器件可能是不可行的。简单地说,本发明实施例可包括在芯片衬底内,可从芯片有源区域散除热量的散热区以允许多种堆叠式芯片配置。
此外,芯片的有源区域可包括具有晶体管的集成电路(IC)。IC可包括N沟道金属氧化物半导体(NMOS)晶体管和P沟道金属氧化物半导体(PMOS)晶体管。要提高任一晶体管类型的性能,可应用应力到晶体管的沟道区(channel region)。具体而言,双向张应力(biaxial tensile stress)可增强NMOS和PMOS晶体管的性能。本发明实施例可包括在允许多种堆叠式芯片配置的同时提供应力到IC晶体管。
图1示出可以为堆叠晶片或管芯提供散热和应力诱导(stress inducement)的设备。
图1示出设备100的横截面型视图。设备100包括具有有源表面(active surface)45的衬底140。衬底140接附到冷却器件150并且通过互连160连接到衬底110。衬底110包括器件层115、金属化区120、通孔170和区域180,并在其背侧具有连接130。
衬底140可包括任何合适的材料,并且有源表面145可包括任何合适的器件。在实施例中,衬底140可以为管芯。在另一实施例中,衬底140可以为晶片。在实施例中,衬底140可包括半导体。在其它实施例中,衬底140可以包括硅、绝缘体上硅(silicon on insulator)、锗或其它材料。在实施例中,衬底140可以为厚度在大约2到10μm范围的薄衬底。在实施例中,有源表面145可以包括NMOS或PMOS晶体管、其它器件、金属化层、介电层、钝化层和焊盘(bond pad)。在实施例中,衬底140可以包括微处理器。在另一实施例中,衬底140可以包括存储器件。
互连160可以为任何合适的材料,并且可以电气连接衬底140和衬底110。在一些实施例中,互连可以包括导体,如铜。在实施例中,互连160可以包括焊料。在实施例中,互连160可以为有源表面145的器件提供电气定线(electrical routing)。在实施例中,互连160可以包括3维互连。
冷却器件150可以是从衬底150散除热量的任何合适的材料或结构。在实施例中,冷却器件150可以包括热沉。在另一实施例中,冷却器件150可以包括热接口材料(thermal interface material)。在另一实施例中,冷却器件150可以包括风扇。在实施例中,冷却器件150可以包括集成散热件。在实施例中,由于有源表面145是衬底140的前侧,因此,冷却器件150可以为背侧冷却器件。在实施例中,可不提供冷却器件150。
衬底110可以包括任何合适的材料。在实施例中,衬底110可以包括半导体。在其它实施例中,衬底110可以包括硅、绝缘体上硅、锗或其它材料。在实施例中,衬底110可以包括具有<100>硅晶(silicon crystal)的硅。在另一实施例中,衬底110可以包括具有<110>硅晶的硅。在实施例中,衬底110可以为管芯。在另一实施例中,衬底110可以为晶片。在实施例中,衬底110可以为厚度在大约2到10μm范围的薄衬底。在另一实施例中,衬底110可以为厚度在大约2到5μm范围的薄衬底。
器件层115可以包括任何合适的器件。在实施例中,器件层115可以包括NMOS晶体管。在另一实施例中,器件层115可以包括PMOS晶体管。在实施例中,器件层115可以包括平面晶体管。在另一实施例中,器件层115可以包括非平面或三门晶体管。在实施例中,器件层115可以包括晶体管和电容器。在实施例中,器件层115可以在衬底110的前侧上,并且与前侧相对的侧可以为衬底110的背侧。器件层115可以上述所列器件的任何组合。
金属化区120可以互连器件层115的器件,并且可以提供到外部组件的连接定线。金属化层120可以包括由介电材料分隔的任何数量的互连金属和通孔层(via layer)。在实施例中,金属化区120的金属层每个都可以大致为平坦并且通过层间介电质(ILD)相互分隔。在实施例中,金属层可以通过通孔层的通孔连接到相邻金属层。在实施例中,金属化区120可以包括范围大约在1到9的多个金属层。在实施例中,金属化区120可以提供到互连160的连接。在另一实施例中,金属化区120可提供通过焊盘(未示出)到互连160的连接。金属化区120的金属和通孔层可以包括任何合适的传导材料。在实施例中,金属化区120的金属和通孔层可以包括铜。
通孔170可以为器件层115中的器件提供到外部组件的连接定线。在实施例中,通孔170可以延伸通过衬底110、器件层115和部分金属化区120。在实施例中,通孔170可以连接到金属化区120的金属层。在实施例中,通孔170可延伸通过器件层115部分和金属化区120,使得它不接触或影响任何器件或金属层。在实施例中,通孔170可以为衬底通孔。
通孔170也可以连接到连接130。在实施例中,通孔170可以通过焊盘(未示出)连接到连接130。在另一实施例中,通孔170可通过衬底110背侧上的金属迹线(trace)(未示出)连接到连接130。通孔170可以包括任何合适的传导材料。在实施例中,通孔170可以包括铜。
连接130可以提供到外部组件(未示出)的连接。在实施例中,连接130可以为衬底110提供连接和电气定线。在另一实施例中,连接130可以为衬底140提供电气定线。在实施例中,连接130可以为衬底110和衬底140提供电气定线,并且提供到诸如印刷电路板(PCB)等外部衬底的连接。在实施例中,连接130可以包括铜。在另一实施例中,连接130可以包括焊料。在实施例中,连接130可以为受控塌陷芯片(collapse chip)连接(C4)凸出部(bump)。
区域180可以在衬底110中提供,并且可以与器件层115相邻。在实施例中,区域180可以为器件层115提供散热区。在实施例中,区域180可以为器件层115提供应力诱导或应力工程区。在实施例中,区域180可以为器件层115提供散热和应力诱导区。在实施例中,区域180可以包括铜。在实施例中,区域180可以包括铜,并且可以具有范围大约在10到30μm的厚度。在另一实施例中,区域180可以包括铜并且可以具有范围大约在80到120μm的厚度。在实施例中,区域180可以包括铜并且可以具有范围大约在80到120μm的厚度。在另一实施例中,区域180可以包括具有金钢石颗粒(diamond particle)的铜。
在另一实施例中,区域180可以包括金钢石或类金钢石碳(diamond like carbon)材料。类金钢石碳材料可以通过在360到4400℃范围的温度淀积碳而形成。在实施例中,区域180可以包括具有厚度在大约1到100μm范围的金钢石或类金钢石材料。在另一实施例中,区域180可以包括具有厚度在大约1到10μm范围的金钢石或类金钢石材料。在实施例中,区域180可以包括具有厚度在大约5到25μm范围的金钢石或类金钢石材料。
如上所述,区域180可以为器件层115提供散热区。通常,材料传热的能力可以为材料的热传导性(thermal conductivity),它以每米开氏度瓦数(W/m·K)单位表示。在实施例中,区域180的热传导性可以大于衬底110的热传导性,使得在使用区域180时热量可比不使用时更快地从器件层115散除。在各种实施例中,衬底110可以包括硅(<100W/m·K),并且区域180可以包括金钢石(>1000W/m·K)、类金钢石材料(~400-500W/m·K),或铜(400W/m·K)。在实施例中,区域180可以通过从器件层115散除热量而允许衬底110正常操作。在实施例中,区域180可以具有大约比衬底110热传导性高4到20倍的热传导性。在另一实施例中,区域180可以具有大约比衬底110热传导性高2到10倍的热传导性。在实施例中,区域180可以具有大约比衬底110热传导性高4到10倍的热传导性。
如上所述,区域180可以在器件层115上提供应力诱导。在器件层115上诱发的双向张应力可提高器件层115上NMOS和PMOS晶体管的性能。在实施例中,区域180可以为应力工程结构(stress engineering structure)。
在器件层115上诱发的应力可以由衬底110与区域180材料之间的热膨胀系数(CTE)的不匹配引起。
在实施例中,衬底110可以包括硅,器件层115可以在大约90到110℃范围的温度操作,并且区域180可以包括在大约20到30℃温度施镀(plated)的铜。在此类实施例中,可在操作温度下在器件层115上形成张应力,这是因为铜具有比硅更高的CTE,并且铜的无应力温度是施镀温度。在实施例中,区域180可以具有比衬底110更高的CTE,并且区域180可以在低于器件层115的操作温度的温度配置(dispose),从而在器件层115上形成张应力(tensile stress)。
在另一实施例中,衬底110可以包括硅,器件层115可以在大约90到110℃的温度操作,并且区域180可以包括在大约360到440℃范围温度淀积的金钢石或类金钢石材料。在此类实施例中,可在操作温度下在器件层115上引起张应力,这是因为金钢石或类金钢石材料具有比硅更低的CTE,并且金钢石或类金钢石材料的无应力温度为淀积温度(deposition temperature)。在实施例中,区域180可以具有比衬底110更低的CTE,并且区域180可以在高于器件层115操作温度的温度配置,从而在器件层115上形成张应力。
器件层上的张应力可以为任何量的张应力。在实施例中,张应力可以在大约0.1到5GPa范围。在另一实施例中,张应力可以在大约1到2GPa范围。在另一实施例中,张应力可以在大约0.5到3GPa范围。
图1示出通过互连160由其有源或前表面连接的两个衬底110、140。衬底140包括接附到其背侧的冷却器件150,并且衬底110包括散热和应力诱导区域180和衬底通孔180,并且在其背侧具有外部连接130。但是,许多其它配置也可以提供。如图1所示,衬底110可以包括连接130。连接130可以有利于连接到类似于衬底110的包括散热和应力诱导区及衬底通孔的另一衬底的背侧。类似于衬底110的若干衬底可以用类似的方式堆叠。
图2A-2F示出可以为堆叠晶片或管芯提供散热和应力诱导区的方法。
图2A示出设备200,包括具有器件层220的衬底210和金属化区230。在实施例中,如下面参照图3A-3H所述,设备200可通过结合层(bonding layer)(未示出)接附到载体(carrier)(未示出)。金属化区域230可以包括由介电材料分隔的任何数量的金属层和通孔层(via layer)。为清晰起见,图2A只示出包括金属化物(metallization)250和介电质240的一个金属层。在实施例中,金属化区230可以包括范围大约在1到9的多个金属层。
衬底210可以包括任何合适的材料。在实施例中,衬底210可以包括半导体。在其它实施例中,衬底210可以包括硅、绝缘体上硅、锗或其它材料。在实施例中,衬底210可以为管芯。在另一实施例中,衬底210可以为晶片。在实施例中,衬底210可以为厚度在大约2到10μm范围的薄衬底。在另一实施例中,衬底210可以为厚度在大约2到5μm范围的薄衬底。
器件层220可以包括任何合适的器件。在实施例中,器件层220可以包括NMOS晶体管。在另一实施例中,器件层220可以包括PMOS晶体管。在实施例中,器件层220可以包括平面晶体管。在另一实施例中,器件层220可以包括非平面或三门晶体管。在实施例中,器件层220可以包括晶体管和电容器。器件层220可以包括上述所列器件的任何组合。通常,衬底210的前侧可视为具有器件层220和金属化区240的侧,并且衬底210的背侧可以相对于正侧。
金属化区230可以互连器件层220的器件,并且可以提供到外部组件的连接定线。金属化区230的金属和通孔层可以包括任何合适的传导材料。在实施例中,金属化区230的金属和通孔层可以包括铜。
如图2B所示,层260可在衬底210的背侧形成。层260可以通过任何合适的技术形成,并且可以为任何合适的材料。在实施例中,层260可以包括铜,并且可以通过施镀形成。在另一实施例中,层260可以包括铜,并且可以通过在大约20到30℃范围的温度施镀形成。在实施例中,层260可以包括铜并且可以具有范围大约在10到30μm的厚度。在另一实施例中,层260可以包括铜并且可以具有范围大约在10到120μm的厚度。在实施例中,层260可以包括铜并且可以具有范围大约在80到120μm的厚度。在实施例中,层260可以包括具有金钢石颗粒的铜。
在实施例中,层260可以包括金钢石或类金钢石材料。在另一实施例中,层260可以包括具有金钢石或在大约360到440℃范围温度淀积的类金钢石材料。在实施例中,层260可以包括金钢石或类金钢石材料,衬底210可以包括硅,并且相对于衬底210,层260可以是薄的,这是因为金钢石或类金钢石材料充分比硅硬(大约10倍)。在实施例中,层260可以包括金钢石或类金钢石材料,并且可以具有在大约1到100μm范围的厚。在实施例中,层260可以包括金钢石或类金钢石材料,并且可以具有在大约1到10μm范围的厚度。在实施例中,层260可以包括金钢石或类金钢石材料,并且具有在大约5到25μm范围的厚度。
如上所述,层260与衬底210之间的CTE不匹配可以导致在操作期间在器件层220的器件上诱发的张应力。在实施例中,层260的CTE可大于衬底210的CTE,并且层260可在低于器件层220操作温度的温度形成。在实施例中,层260的CTE可小于衬底210的CTE,并且层260可在高于器件层220操作温度的温度形成。
如图2C所示,开口(opening)270可在层260、衬底210、器件层220、部分金属化层230中形成以显露(expose)金属化物250。开口270可以由任何合适的技术形成。在实施例中,可以通过先在层260上形成图样(pattern)(未示出),然后蚀刻层260、衬底210、器件层220及部分金属化区230,并且最后去除图样而形成开口270。在实施例中,金属化物250可充当在层260、衬底210、器件层220及部分金属化区230蚀刻期间的蚀刻停止层。在实施例中,图样可以包括光刻胶(photoresist)。在另一实施例中,开口270可以通过钻通层260、衬底210、器件层220及部分金属化区230而形成。
如图2D所示,绝缘体280可在开口270和层260上形成。绝缘体280可以通过任何合适的技术形成,并且可以包括任何合适的材料。在实施例中,绝缘体280可以包括氮化物或氧化物。在实施例中,绝缘体280可通过淀积法(deposition)形成。
如图2E所示,可形成侧壁290。侧壁290可以由任何合适的技术形成。在实施例中,侧壁290可以通过绝缘体280的非等向性蚀刻(anisotropic etch)形成。
如图2F所示,通孔295可在开口270中形成。通孔295可以通过任何合适的技术形成,并且可以包括任何合适的材料。在实施例中,通孔295可以延伸通过层260、衬底210、器件层220及部分金属化区230。在实施例中,通孔295可以为传导材料(conductive material)。通孔295可以包括任何传导材料。在实施例中,通孔295可以包括铜。在实施例中,通孔295可通过施镀(plating)形成。在实施例中,侧壁290可以将通孔295与层260、衬底210、器件层220及部分金属化区230电绝缘。
在实施例中,连接可在衬底210(未示出)背侧上形成。在实施例中,连接可以为C4凸出部(C4 bumps)。在另一实施例中,连接可以包括铜。
图3A-3H示出可以为堆叠晶片或管芯提供散热和应力诱导区的方法。
图3A示出设备300,包括具有器件层310的衬底305和金属化区315。金属化层315可以包括由介电材料分隔的任何数量的金属层和通孔层。为清晰起见,图3A只示出包括金属化物325和介电质320的一个金属层。在实施例中,金属化区315可以包括范围大约在1到9的任何数量的金属层。
设备300也包括结合层330和载体335。结合层330和载体335可以为任何合适的材料。在实施例中,载体335可以为厚硅。在实施例中,载体335可以包括有源层和金属化层(未示出)。在实施例中,可不使用结合层330和载体335。
衬底305可以包括任何合适的材料。在实施例中,衬底305可以包括半导体。在其它实施例中,衬底305可以包括硅、绝缘体上硅、锗或其它材料。在实施例中,衬底305可以为管芯。在另一实施例中,衬底305可以为晶片。在实施例中,衬底305可以为厚度在大约2到10μm范围的薄衬底。在另一实施例中,衬底305可以为厚度在大约2到5μm范围的薄衬底。
器件层310可以包括任何合适的器件。在实施例中,器件层310可以包括NMOS晶体管。在另一实施例中,器件层310可以包括PMOS晶体管。在实施例中,器件层310可以包括平面晶体管。在另一实施例中,器件层310可以包括非平面或三门晶体管。在实施例中,器件层310可以包括晶体管和电容器。器件层310可以以上所列器件的任何组合。通常,衬底305的前侧可视为具有器件层310和金属化区315的侧,并且衬底305的背侧可以与前侧相对。
金属化区315可以互连器件层310的器件,并且可以提供到外部组件的连接定线。金属化区315的金属和通孔层可以包括任何合适的传导材料。在实施例中,金属化区315的金属和通孔层可以包括铜。
如图3B所示,沟槽340可在衬底305中形成。沟槽340可以由任何合适的材料形成。在实施例中,可以通过先在衬底305上形成图样(未示出),然后蚀刻衬底305,并最后去除图样而形成沟槽340。在实施例中,图样可以包括光刻胶。
如图3C所示,绝缘体345可在沟槽340和衬底305上形成。绝缘体345可以通过任何合适的技术形成,并且可以为任何合适的材料。在实施例中,绝缘体345可以包括氮化物或氧化物。
如图3D所示,开口350可以在绝缘体345、衬底305和器件层310中形成以显露金属化区315。开口350可以由任何合适的技术形成。在实施例中,可以通过先在绝缘体345上形成图样(未示出),然后蚀刻绝缘体345、衬底305和器件层310,并且最后去除图样而形成开口350。在实施例中,图样可以包括光刻胶。在实施例中,金属化区315中的介电材料可以充当蚀刻停止层。
如图3E所示,绝缘体355可在开口350和绝缘体345上形成。绝缘体355可以通过任何合适的技术形成,并且可以为任何合适的材料。在实施例中,绝缘体355可以包括氮化物或氧化物。在实施例中,绝缘体355可以将通孔(下面进一步论述)与衬底305和器件层310电绝缘。
如图3F所示,可执行蚀穿(break-through etch)以显示金属化物325。蚀穿可通过任何合适的技术执行。在实施例中,蚀穿可包括非等向性蚀刻。
如图3G所示,可形成图样360和传导填充(conductive fill)365。图样360可以通过任何合适的技术形成,并且可以包括任何合适的材料。在实施例中,图样360可以包括光刻胶,并且可以通过光刻工艺(photolithography process)形成。
传导填充365可以通过任何合适的技术形成,并且可以为任何合适的材料。在实施例中,传导填充365可以包括铜。在实施例中,传导填充365可通过施镀形成。在实施例中,传导填充365可以通过在大约20到30℃范围的温度施镀而形成。在实施例中,开口350中传导填充的部分可形成传导通孔(conductive through via)。在实施例中,沟槽340中的传导填充365部分可以形成应力工程区,并且在器件层310上形成张应力。在实施例中,传导填充365可以具有大于衬底305的CTE的CTE,并且传导填充365可以在低于器件层310操作温度的温度形成。在实施例中,传导填充365可以具有小于衬底305的CTE的CTE,并且传导填充365可以在高于器件层310操作温度的温度形成。在实施例中,沟槽340中的传导填充365部分可以为器件层310提供散热区。
如图3H所示,图样360可以被去除,并且介电质370、导体375和连接380可以在传导填充345上形成。介电质370、导体375和连接380可以通过任何合适的技术形成,并且可以包括任何合适的材料。在实施例中,介电质370可以通过旋转涂布法(spin on method)形成。在实施例中,导体375可以通过图样、蚀刻、图样去除和施镀工艺形成。在实施例中,导体可以包括铜。在实施例中,连接380可以包括凸出部。在实施例中,连接380可通过C4工艺形成。在实施例中,连接380可允许到诸如印刷电路板等衬底的倒转片连接(flip-chip connection)。
图4示出系统400。系统400可以包括处理器410、存储器420、存储器440、图形处理器440、显示处理器450、网络接口460、I/O接口470及通信总线480。在实施例中,存储器420可以包括易失性存储器组件。系统400的任何组件可以包括如上所述的散热和应力工程区。此外,如上所述,公开的发明允许包括散热和应力工程区的芯片堆叠。包括散热和应力工程区等堆叠组件的大量组合可以实现。在实施例中,存储器420可以包括散热和应力工程区,并且存储器420可以与处理器410堆叠。在实施例中,系统400可以包括第二处理器(未示出),并且第二处理器可以包括散热和应力工程区,并且第二处理器可以与410堆叠。
此说明书通篇对“一个实施例”或“实施例”的引用指结合该实施例描述的特定特性、结构、材料或特征包括在本发明的至少一个实施例中。因此,在说明书通篇各个位置出现的“在一个实施例”或“在实施例中”短语不一定全部指本发明的同一实施例。此外,特定的特性、结构、材料或特征可在一个或多个实施例中以任何适合的方式组合。
要理解,上述描述旨在说明而不是限制。在查看上述说明后,本领域的技术人员将明白许多其它实施例。因此,本发明的范围应参照随附权利要求书及此类权利要求书授权的等效物完全范围定义。
Claims (19)
1.一种用于可堆叠晶片或管芯封装的设备,包括:
金属化区,包括衬底的器件层上的多个金属层;
通孔,延伸通过所述衬底和所述器件层,并接触所述金属化区中的金属层;以及
散热和应力工程区,所述散热和应力工程区在所述器件层上引起应力,并且所述散热和应力工程区位于所述衬底中并与所述器件层相邻且整个位于所述器件层上。
2.如权利要求1所述的设备,其特征在于,所述散热和应力工程区包括铜。
3.如权利要求1所述的设备,其特征在于,所述散热和应力工程区至少包括如下之一:金钢石、类金钢石材料或带有金钢石颗粒的铜。
4.如权利要求1所述的设备,其特征在于,在90到110℃的温度范围内,所述散热和应力工程区在所述器件层中的晶体管上造成范围0.5到3GPa的双向张应力。
5.如权利要求1所述的设备,其特征在于,所述散热和应力工程区具有在比所述衬底的热传导性高4到20倍范围中的热传导性。
6.如权利要求1所述的设备,其特征在于,还包括:
所述金属化区上的互连,其中所述互连连接到第二衬底的有源表面;以及
接附到与所述有源表面相对的所述第二衬底的表面的冷却器件。
7.一种用于可堆叠晶片或管芯封装的设备,包括:
第一有源表面,包括通过互连耦合到第二衬底的第二有源表面的第一衬底的金属化区,其中所述第一衬底包括与所述第一有源表面相邻且整个位于所述第一有源表面上的散热和应力工程区,并且还包括延伸通过所述第一衬底并接触所述金属化区的金属层的通孔,其中所述散热和应力工程区在所述第一有源表面上引起应力;以及
冷却器件,位于与所述第二衬底的有源表面相对的表面上。
8.如权利要求7所述的设备,其特征在于,还包括:
印刷电路板,连接到与所述第一衬底的有源表面相对的所述第一衬底的表面上的凸出部。
9.如权利要求7所述的设备,其特征在于,所述散热和应力工程区至少包括如下之一:铜、金钢石、类金钢石碳或带金钢石颗粒的铜。
10.如权利要求7所述的设备,其特征在于,在90到110℃的温度范围内,所述散热和应力工程区在所述第一衬底中的晶体管上造成范围0.5到3GPa的双向张应力,并且所述散热和应力工程区具有在比所述第一衬底热传导性高4到20倍范围内的热传导性。
11.一种用于可堆叠晶片或管芯封装的方法,包括:
在衬底表面上提供散热和应力工程层,其中所述衬底表面与所述衬底的器件层上的金属化区相对;
显露所述金属化区的金属层,其中显露所述金属层包括提供通过所述散热和应力工程层、所述衬底和有源区的通孔开口;
在所述通孔开口侧壁上提供侧壁绝缘体;以及
在所述通孔开口中提供传导填充。
12.如权利要求11所述的方法,其特征在于,还包括:
将所述金属化区上的互连电气连接到第二衬底的有源表面上的第二互连。
13.如权利要求11所述的方法,其特征在于,提供所述散热和应力工程层包括在低于所述器件层操作温度的温度提供所述散热和应力工程区,并且所述散热和应力工程层的热膨胀系数大于所述衬底的热膨胀系数。
14.如权利要求11所述的方法,其特征在于,提供所述散热和应力工程层包括在高于所述器件层操作温度的温度提供所述散热和应力工程区,并且所述散热和应力工程层的热膨胀系数小于所述衬底的热膨胀系数。
15.如权利要求11所述的方法,其特征在于,所述散热和应力工程层至少包括如下之一:铜、金钢石、类金钢石碳或带金钢石颗粒的铜。
16.一种用于可堆叠晶片或管芯封装的方法,包括:
在衬底表面中提供沟槽,其中所述衬底表面与所述衬底的器件层上的金属化区相对;
在所述衬底表面和所述沟槽上形成绝缘层;
通过提供通过所述绝缘层、所述衬底和所述器件层的通孔开口而显露所述金属化区;
在所述绝缘层和所述通孔开口上形成第二绝缘层;
显露所述金属化区的金属化层;以及
选择性地在所述沟槽和所述通孔开口中提供传导填充,以便形成所述沟槽中的散热和应力工程区和所述通孔开口中的全通通孔。
17.如权利要求16所述的方法,其特征在于,还包括:
在所述衬底表面和所述传导填充上形成介电层;
在所述介电层上形成凸出部;以及
将所述凸出部电气连接到第二衬底的有源表面上的互连,其中与所述有源表面相对的所述第二衬底的表面接附到冷却器件。
18.如权利要求16所述的方法,其特征在于,所述传导填充包括铜。
19.如权利要求16所述的方法,其特征在于,选择性地提供传导填充包括形成图样,所述图样包括所述沟槽上的开口和所述衬底上方的所述通孔开口。
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2006
- 2006-10-24 CN CN2006800393517A patent/CN101292348B/zh not_active Expired - Fee Related
- 2006-10-24 TW TW095139195A patent/TWI340440B/zh not_active IP Right Cessation
- 2006-10-24 DE DE112006002909.6T patent/DE112006002909B4/de not_active Expired - Fee Related
- 2006-10-24 GB GB0806342A patent/GB2444467B/en not_active Expired - Fee Related
- 2006-10-24 WO PCT/US2006/041779 patent/WO2007050754A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US4842699A (en) * | 1988-05-10 | 1989-06-27 | Avantek, Inc. | Method of selective via-hole and heat sink plating using a metal mask |
US6278181B1 (en) * | 1999-06-28 | 2001-08-21 | Advanced Micro Devices, Inc. | Stacked multi-chip modules using C4 interconnect technology having improved thermal management |
US6653730B2 (en) * | 2000-12-14 | 2003-11-25 | Intel Corporation | Electronic assembly with high capacity thermal interface |
Also Published As
Publication number | Publication date |
---|---|
TWI340440B (en) | 2011-04-11 |
US20070093066A1 (en) | 2007-04-26 |
DE112006002909B4 (de) | 2014-10-30 |
GB2444467A (en) | 2008-06-04 |
TW200725839A (en) | 2007-07-01 |
WO2007050754A2 (en) | 2007-05-03 |
WO2007050754A3 (en) | 2007-06-14 |
GB0806342D0 (en) | 2008-05-14 |
CN101292348A (zh) | 2008-10-22 |
GB2444467B (en) | 2010-12-08 |
DE112006002909T5 (de) | 2008-09-18 |
US7723759B2 (en) | 2010-05-25 |
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