CN113921511A - 半导体封装件 - Google Patents
半导体封装件 Download PDFInfo
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- CN113921511A CN113921511A CN202110772790.5A CN202110772790A CN113921511A CN 113921511 A CN113921511 A CN 113921511A CN 202110772790 A CN202110772790 A CN 202110772790A CN 113921511 A CN113921511 A CN 113921511A
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Abstract
一种半导体封装件包括第一半导体芯片、第二半导体芯片、第一主连接焊盘结构和第一虚设连接焊盘结构。第一主连接焊盘结构布置在第一半导体芯片与第二半导体芯片之间的界面处,并且被布置为在与第一半导体芯片的顶表面平行的第一方向上彼此间隔开第一主间距,其中,第一主连接焊盘结构中的每一个包括:第一连接焊盘,其电连接至第一半导体芯片;以及第二连接焊盘,其电连接至第二半导体芯片并且接触第一连接焊盘。第一虚设连接焊盘结构布置在第一半导体芯片与第二半导体芯片之间的界面处,被布置为与第一主连接焊盘结构间隔开,并且被布置为在第一方向上彼此间隔开第一虚设间距,第一虚设间距大于第一主间距。
Description
相关申请的交叉引用
本申请基于和要求于2020年7月10日在韩国知识产权局提交的韩国专利申请No.10-2020-0085673的优先权,该申请的公开内容以引用方式全部并入本文中。
技术领域
本发明构思涉及半导体封装件,更具体地,涉及具有多个半导体芯片的堆叠结构的半导体封装件。
背景技术
为了改善半导体装置的性能和存储容量,广泛地使用具有堆叠有多个半导体芯片的结构的半导体封装件。具体地,已经提出了通过经连接焊盘附接和切割(sawing)晶圆来形成多个半导体芯片的堆叠结构的方法。然而,通常,发生包括诸如铜等的金属材料的连接焊盘的台阶或水平差或者发生围绕连接焊盘的绝缘层的局部侵蚀,这增大了接合操作的难度。
发明内容
本发明构思的各个方面提供了其中可以通过防止发生绝缘层的局部侵蚀来使晶圆与晶圆接合操作的缺陷最小化的半导体封装件。
根据本发明构思的一方面,一种半导体封装件包括:第一半导体芯片、第二半导体芯片、第一主连接焊盘结构和第一虚设连接焊盘结构。第一主连接焊盘结构布置在第一半导体芯片与第二半导体芯片之间的界面处,并且被布置为在与第一半导体芯片的顶表面平行的第一方向上彼此间隔开第一主间距,其中,第一主连接焊盘结构中的每一个包括第一连接焊盘和第二连接焊盘,所述第一连接焊盘电连接至第一半导体芯片,所述第二连接焊盘电连接至第二半导体芯片并且接触第一连接焊盘。第一虚设连接焊盘结构布置在第一半导体芯片与第二半导体芯片之间的界面处,被布置为与第一主连接焊盘结构间隔开,并且被布置为在第一方向上彼此间隔开第一虚设间距,第一虚设间距大于第一主间距。
根据本发明构思的一方面,一种半导体封装件包括:第一半导体芯片、第二半导体芯片、主连接焊盘结构、第一虚设连接焊盘结构和第二虚设连接焊盘结构。主连接焊盘结构布置在第一半导体芯片与第二半导体芯片之间的界面处,其中,主连接焊盘结构中的每一个包括第一连接焊盘和第二连接焊盘,所述第一连接焊盘电连接至第一半导体芯片,所述第二连接焊盘电连接至第二半导体芯片并且接触第一连接焊盘。第一虚设连接焊盘结构布置在第一半导体芯片与第二半导体芯片之间的界面处,并且被布置为与主连接焊盘结构间隔开。第二虚设连接焊盘结构布置在第一半导体芯片与第二半导体芯片之间的界面处,并且被布置为与主连接焊盘结构间隔开,其中,第一虚设连接焊盘结构位于第二区域与第三区域之间的第一区域中,第二虚设连接焊盘结构位于第二区域中,主连接焊盘结构位于第三区域中。当从第一半导体芯片的顶部观看时,主连接焊盘结构具有关于第三区域的面积的第一主焊盘密度,当从第一半导体芯片的顶部观看时,第一虚设连接焊盘结构具有关于第一区域的面积的第一虚设焊盘密度,当从第一半导体芯片的顶部观看时,第二虚设连接焊盘结构具有关于第二区域的面积的第二虚设焊盘密度,第一虚设焊盘密度小于第一主焊盘密度,并且第二虚设焊盘密度小于第一虚设焊盘密度。
根据本发明构思的一方面,一种半导体封装件包括:第一半导体芯片;第二半导体芯片;第一主连接焊盘结构,其布置在第一半导体芯片与第二半导体芯片之间的界面处,并且被布置为在与第一半导体芯片的顶表面平行的第一方向上彼此间隔开第一主间距;第二主连接焊盘结构,其布置在第一半导体芯片与第二半导体芯片之间的界面处,并且被布置为在第一方向上彼此间隔开第二主间距,第二主间距大于第一主间距;以及第一虚设连接焊盘结构,其布置在第一半导体芯片与第二半导体芯片之间的界面处,并且被布置为在第一方向上彼此间隔开第一虚设间距,第一虚设间距大于第一主间距,其中,第一主连接焊盘结构和第二主连接焊盘结构中每一个包括第一连接焊盘和第二连接焊盘,所述第一连接焊盘电连接至第一半导体芯片,所述第二连接焊盘电连接至第二半导体芯片并且接触第一连接焊盘。
附图说明
通过结合附图的下面的详细描述,将更加清楚地理解本发明构思的实施例,在附图中:
图1是根据示例实施例的半导体封装件的布局图;
图2是示出图1的焊盘布置的示例的示意图;
图3是沿图2的线A1-A1'截取的截面图;
图4是图3的部分CX1的放大图;
图5是根据示例实施例的半导体封装件的截面图;
图6是根据示例实施例的半导体封装件的布局图;
图7是示出图6的焊盘布置的示例的示意图;
图8是沿图7的线A1-A1'截取的截面图;
图9是根据示例实施例的半导体封装件的布局图;
图10是根据示例实施例的半导体封装件的布局图;
图11是根据示例实施例的半导体封装件的布局图;
图12是根据示例实施例的半导体封装件的截面图;
图13是根据示例实施例的半导体封装件的截面图;
图14是根据示例实施例的半导体封装件的截面图;以及
图15至图24是示出根据示例实施例的制造半导体封装件的方法的示意图。
具体实施方式
在下文中,以下将参照附图详细地描述本发明构思的实施例。
图1是根据示例实施例的半导体封装件100的布局图。图2是示出图1的焊盘布置的示例的示意图。图3是沿图2的线A1-A1'截取的截面图。图4是图3的部分CX1的放大图。
参照图1至图4,半导体封装件100可以具有其中第一半导体芯片10C附接到第二半导体芯片20C的结构。第一半导体芯片10C可以包括第一衬底10W和第一衬底10W上的第一布线结构10MS。第二半导体芯片20C可以包括第二衬底20W和第二衬底20W上的第二布线结构20MS。
第一主连接焊盘结构MP1和虚设连接焊盘结构DP可以布置在第一半导体芯片10C与第二半导体芯片20C之间(例如,第一半导体芯片10C与第二半导体芯片20C之间的界面处)。围绕第一主连接焊盘结构MP1和虚设连接焊盘结构DP的第一接合绝缘层10UI和第二接合绝缘层20UI可以布置在第一半导体芯片10C与第二半导体芯片20C之间(例如,第一半导体芯片10C与第二半导体芯片20C之间的界面处)。第一半导体芯片10C和第二半导体芯片20C可以通过第一主连接焊盘结构MP1、虚设连接焊盘结构DP、第一接合绝缘层10UI和第二接合绝缘层20UI经金属氧化物混合接合彼此附接。本文中描述的每个连接焊盘“结构”可以指通过焊盘与焊盘接合工艺连接的两个焊盘的组合。如各种附图中所示,多个连接焊盘结构可以以矩阵图案布置。尽管有时仅结合一个这样的结构来描述第一主连接焊盘结构MP1和第一虚设连接焊盘结构至第三虚设连接焊盘结构DP1至DP3,但是在每个焊盘区域中包括的结构中的每一个结构可以具有与结合单独描述的连接焊盘结构所讨论的相同的特性。
如图1中所示,第一半导体芯片10C和第二半导体芯片20C可以具有在其中心区域的第一主焊盘区域MPR1和在其边缘区域中的划线区域SR,并且可以具有在第一主焊盘区域MPR1与划线区域SR之间的虚设焊盘区域DPR。虚设焊盘区域DPR可以包括围绕第一主焊盘区域MPR1的第一虚设焊盘区域DPR1、围绕第一虚设焊盘区域DPR1的第二虚设焊盘区域DPR2和围绕第二虚设焊盘区域DPR2的第三虚设焊盘区域DPR3。由于第一虚设焊盘区域DPR1具有围绕第一主焊盘区域MPR1的环形状,因此第一虚设焊盘区域DPR1可以被描述为第一虚设焊盘环区域。由于第二虚设焊盘区域DPR2具有围绕第一主焊盘区域MPR1和第一虚设焊盘区域DPR1两者的环形状,因此第二虚设焊盘区域DPR2可以被描述为第二虚设焊盘环区域。由于第三虚设焊盘区域DPR3具有围绕第一主焊盘区域MPR2、第一虚设焊盘区域DPR1和第二虚设焊盘区域DPR2的环形状,因此第三虚设焊盘区域DPR3可以被描述为第三虚设焊盘环区域。这些区域还可以被描述为最内中心区域(例如,MPR1)、第一围绕环区域(例如,DPR1)、第二围绕环区域(例如,DPR2)和最外环区域(例如,DPR3)。
多个第一主连接焊盘结构MP1可以布置在第一主焊盘区域MPR1中,并且可以具有第一主焊盘密度D_MP1。在本文中,在平面图中(即,当从第一半导体芯片10C的顶部观看时,其被描述为顶视图),第一主焊盘密度D_MP1可以是第一主焊盘区域MPR1中的所有的第一主连接焊盘结构MP1的面积之和与第一主焊盘区域MPR1的面积之比。例如,第一主焊盘密度D_MP1可以为大约5%至大约50%,或者大约0.05至大约0.5。
虚设连接焊盘结构DP可以包括第一虚设连接焊盘结构至第三虚设连接焊盘结构DP1、DP2和DP3。第一虚设连接焊盘结构DP1可以布置在第一虚设焊盘区域DPR1中,并且可以具有第一虚设焊盘密度D_DP1。第二虚设连接焊盘结构DP2可以布置在第二虚设焊盘区域DPR2中,并且可以具有第二虚设焊盘密度D_DP2。第三虚设连接焊盘结构DP3可以布置在第三虚设焊盘区域DPR3中,并且可以具有第三虚设焊盘密度D_DP3。当从顶视图观看时,每个相应的虚设焊盘密度可以是相应的虚设焊盘区域中的所有虚设焊盘结构的面积之和与对应的虚设焊盘区域(例如,环区域)的面积之比。这些密度还可以被描述为虚设焊盘面积密度(例如,特定虚设焊盘区域中的虚设焊盘面积密度)。虚设焊盘密度还可以指每给定面积的虚设焊盘的数量,其还可以具有以下描述的逐渐增大/减小关系。例如,第一虚设焊盘密度至第三虚设焊盘密度D_DP1、D_DP2和D_DP3可以为大约1%至大约40%,或者大约0.01至大约0.4。
在示例实施例中,第一虚设焊盘密度至第三虚设焊盘密度D_DP1、D_DP2和D_DP3可以逐渐减小。例如,第一虚设焊盘密度D_DP1可以小于第一主焊盘密度D_MP1,第二虚设焊盘密度D_DP2可以小于第一虚设焊盘密度D_DP1,并且第三虚设焊盘密度D_DP3可以小于第二虚设焊盘密度D_DP2(即,D_DP3<D_DP2<D_DP1<D_MP1)。
在示例实施例中,第一虚设焊盘密度至第三虚设焊盘密度D_DP1、D_DP2和D_DP3可以具有根据虚设梯度规则的值。虚设梯度规则可以基于第一主焊盘密度D_MP1的值来确定第一虚设焊盘密度至第三虚设焊盘密度D_DP1、D_DP2和D_DP3。虚设梯度规则可以基于第一主焊盘密度D_MP1和参考焊盘密度DCR的值将虚设焊盘区域DPR划分为n个子虚设焊盘区域(例如,子虚设焊盘环区域),并且n个子虚设焊盘区域中的每一个的焊盘密度可以彼此不同。例如,在图1中所示的实施例中,虚设焊盘区域DPR可以包括三个子虚设焊盘区域,并且三个子虚设焊盘区域可以分别对应于第一虚设焊盘区域至第三虚设焊盘区域DPR1、DPR2和DPR3。
例如,虚设焊盘区域DPR可以包括n个子虚设焊盘区域,并且n可以由等式1确定。
(D_MP1)/(DCR)-1≤n<(D_MP1)/(DCR) 等式1,
其中,n是自然数,DCR是参考焊盘密度,并且D_MP1是第一主焊盘密度。
在示例实施例中,参考焊盘密度DCR可以为大约2%至大约5%。然而,参考焊盘密度DCR不限于此,并且可以根据第一半导体芯片10C和第二半导体芯片20C的应用具有不同的值。
例如,当第一主焊盘密度D_MP1为15%并且参考焊盘密度DCR为3%时,虚设焊盘区域DPR可以基于等式1包括四个子虚设焊盘区域。例如,当第一主焊盘密度D_MP1为10%并且参考焊盘密度DCR为3%时,虚设焊盘区域DPR可以基于等式1包括三个子虚设焊盘区域。
n个子虚设焊盘区域中的每一个的虚设焊盘密度D_DPk可以由等式2确定。
D_DPk=(n+1-k)/(n+1)×D_MP1 等式2,
其中,D_DPk可以是第k子虚设焊盘区域的密度,k可以是从1至n的自然数,并且D_MP1可以是第一主焊盘密度。
例如,当第一主焊盘密度D_MP1为12%并且参考焊盘密度DCR为3%时,虚设焊盘区域DPR可以基于等式1包括三个子虚设焊盘区域,并且第一子虚设焊盘区域至第三子虚设焊盘区域的虚设焊盘密度可以基于等式2分别为9%、6%和3%。例如,在图1和图2中所示的示例中,第一主焊盘密度D_MP1可以为12%,第一虚设焊盘密度D_DP1可以为9%,第二虚设焊盘密度D_DP2可以为6%,并且第三虚设焊盘密度D_DP3可以为3%。
例如,当第一主焊盘密度D_MP1为20%并且参考焊盘密度DCR为5%时,虚设焊盘区域DPR可以基于等式1包括三个子虚设焊盘区域,并且第一子虚设焊盘区域至第三子虚设焊盘区域的虚设焊盘密度可以基于等式2分别为15%、10%和5%。例如,在图1和图2中所示的示例中,第一主焊盘密度D_MP1可以为20%,第一虚设焊盘密度D_DP1可以为15%,第二虚设焊盘密度D_DP2可以为10%,并且第三虚设焊盘密度D_DP3可以为5%。
例如,多个第一主连接焊盘结构MP1可以被布置为在第一方向(例如,X方向和/或Y方向)上彼此间隔开第一主间距P11,多个第一虚设连接焊盘结构至第三虚设连接焊盘结构DP1、DP2和DP3可以分别被布置为在第一方向上彼此间隔开第一虚设间距P21、第二虚设间距P22和第三虚设间距P23。第一虚设间距P21可以大于第一主间距P11,第二虚设间距P22可以大于第一虚设间距P21,并且第三虚设间距P23可以大于第二虚设间距P22(即,P11<P21<P22<P23)。
如图3中所示,每个第一主连接焊盘结构MP1可以在与第一半导体芯片10C的顶表面平行的第一方向上具有第一宽度W1,第一虚设连接焊盘结构至第三虚设连接焊盘结构DP1、DP2和DP3中的每一个可以在第一方向上具有第二宽度W2,并且第二宽度W2可以与第一宽度W1基本上相同。在其它实施例中,第一虚设连接焊盘结构至第三虚设连接焊盘结构DP1、DP2和DP3中的至少一个可以具有与第一主连接焊盘结构MP1的宽度或焊盘面积不同的宽度或焊盘面积。
如图1和图2中所示,随着虚设焊盘区域DPR的虚设焊盘密度在从半导体封装件100的中心区域朝向划线区域SR的方向上逐渐减小(即,D_DP3<D_DP2<D_DP1<D_MP1),可以防止在第一主连接焊盘结构MP1的平坦化操作中可发生第一接合绝缘层10UI和第二接合绝缘层20UI的局部侵蚀。
尽管图2示出了第一主连接焊盘结构MP1和虚设连接焊盘结构DP两者具有方形平面形状,但是第一主连接焊盘结构MP1和虚设连接焊盘结构DP的平面形状(例如,如从顶视图观看)不限于此,并且可以是各种形状(诸如,矩形、菱形、圆角方形、圆角矩形、椭圆形和圆形)。另外,尽管图2示出了没有虚设连接焊盘结构DP布置在划线区域SR中,但是可替代地,虚设连接焊盘结构DP可以例如以第三虚设焊盘密度D_DP3布置在划线区域SR的至少部分中。
如图2和图3中所示,第一半导体芯片10C可以包括第一衬底10W和第一布线结构10MS,第二半导体芯片20C可以包括第二衬底20W和第二布线结构20MS,并且第一主连接焊盘结构MP1和虚设连接焊盘结构DP可以布置在第一半导体芯片10C与第二半导体芯片20C之间,或者第一半导体芯片10C与第二半导体芯片20C之间的界面处。
第一主连接焊盘结构MP1和虚设连接焊盘结构DP中的每一个可以包括第一连接焊盘16和与第一连接焊盘16接触的第二连接焊盘26。如在本文中使用的,术语“接触”指直接连接,例如,触摸。第一接合绝缘层10UI可以布置在第一布线结构10MS上以围绕第一连接焊盘16的侧表面,并且第二接合绝缘层20UI可以布置在第二布线结构20MS上以围绕第二连接焊盘26的侧表面。当第二接合绝缘层20UI与第一接合绝缘层10UI接触时,第一半导体芯片10C和第二半导体芯片20C可以通过金属氧化物混合接合彼此附接。
第一衬底10W和第二衬底20W可以基于IV族材料晶圆(诸如,硅晶圆)或III-V族化合物晶圆来形成。另外,就形成方法而言,第一衬底10W和第二衬底20W可以由单晶晶圆(诸如,硅单晶晶圆)形成。然而,第一衬底10W和第二衬底20W不限于单晶晶圆,并且各种晶圆(诸如,外延晶圆、抛光晶圆、退火晶圆、绝缘体上硅(SOI)晶圆)可以用作第一衬底10W和第二衬底20W。在本文中,外延晶圆指其中结晶材料生长在单晶硅衬底上的晶圆。另外,第一衬底10W和第二衬底20W可以包括掺杂有杂质的阱或掺杂有杂质的结构。另外,第一衬底10W和第二衬底20W可以包括各种装置隔离结构(诸如,浅沟槽隔离(STI)结构)。
第一半导体芯片10C和第二半导体芯片20C中的每一个可以包括各种类型的多个单独的装置。多个单独的装置可以包括各种微电子装置,例如,金属氧化物半导体场效应晶体管(MOSFET)(诸如,互补金属绝缘体半导体(CMOS)晶体管)、系统大规模集成(LSI)、图像传感器(诸如,CMOS成像传感器(CIS))、微电子机械系统(MEMS)、有源装置、无源装置等。
在示例实施例中,第一半导体芯片10C和第二半导体芯片20C中的每一个可以包括动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、闪速存储器芯片、电可擦除和可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁性随机存取存储器(MRAM)芯片和电阻式随机存取存储器(RRAM)芯片中的至少一种。
例如,如图4中所示,第一集成电路10TR可以形成在第一衬底10W上,并且第二集成电路20TR可以形成在第二衬底20W上。第一集成电路10TR和第二集成电路20TR可以包括各种半导体装置(诸如,晶体管、二极管、电阻器、电容器等)。图4示出了典型的晶体管作为集成电路。晶体管可以包括例如源极/漏极区域、形成在衬底中的沟道区域、和形成在衬底上的栅极结构。
第一布线结构10MS可以布置在第一衬底10W上,并且可以包括多个第一布线图案14A、多个第一接触件14B和第一层间绝缘膜12。第一集成电路10TR可以通过多个第一布线图案14A和多个第一接触件14B与外部交换电信号。在本文中,电信号可以包括电源电压、接地电压、信号电压等。多个第一布线图案14A可以具有布置在不同竖直水平处的多个金属层的堆叠结构。第一层间绝缘膜12可以具有多个绝缘层的堆叠结构,并且第一层间绝缘膜12可以被布置为覆盖第一集成电路10TR。
第二布线结构20MS可以布置在第二衬底20W上,并且可以包括多个第二布线图案24A、多个第二接触件24B和第二层间绝缘膜22。第二集成电路20TR可以通过多个第二布线图案24A和多个第二接触件24B与外部交换电信号。多个第二布线图案24A可以具有布置在不同竖直水平处的多个金属层的堆叠结构。第二层间绝缘膜22可以具有多个绝缘层的堆叠结构,并且第二层间绝缘膜22可以被布置为覆盖第二集成电路20TR。
第一连接焊盘16和围绕第一连接焊盘16的侧壁的第一接合绝缘层10UI可以布置在第一布线结构10MS上。第二连接焊盘26和围绕第二连接焊盘26的侧壁的第二接合绝缘层20UI可以布置在第二布线结构20MS上。每个第一连接焊盘16的顶表面可以被布置为与第一接合绝缘层10UI的顶表面共面,并且每个第二连接焊盘26的顶表面可以被布置为与第二接合绝缘层20UI的顶表面共面。每个第一连接焊盘16的顶表面可以与相应的第二连接焊盘26的顶表面接触,并且第一接合绝缘层10UI的顶表面可以与第二接合绝缘层20UI的顶表面接触。在本文中,第一连接焊盘16的面对第二半导体芯片20C的表面可以被称作第一连接焊盘16的顶表面,并且第二连接焊盘26的面对第一半导体芯片10C的表面可以被称作第二连接焊盘26的顶表面。另外,如本文中使用的,诸如“相同”、“相等”、“平面”或“共面”的术语包含相同性或接近相同性,包括例如由于制造工艺而可能发生的变化。除非上下文或其它陈述另有指示,否则在本文中可以使用术语“基本上”来强调该含义。
第一连接焊盘16可以各自包括第一金属层16F和第一阻挡层16L。第一阻挡层16L可以围绕第一金属层16F的侧壁和底表面,并且可以位于第一金属层16F与第一接合绝缘层10UI之间。第一接合绝缘层10UI可以包括第一绝缘层18A和第一接合层18B,并且第一接合层18B的顶表面可以被布置为与第一连接焊盘16的顶表面共面。
第二连接焊盘26可以各自包括第二金属层26F和第二阻挡层26L。第二阻挡层26L可以围绕第二金属层26F的侧壁和底表面,并且可以位于第二金属层26F与第二接合绝缘层20UI之间。第二接合绝缘层20UI可以包括第二绝缘层28A和第二接合层28B,并且第二接合层28B的顶表面可以与第二连接焊盘26的顶表面共面,并且与第一接合层18B接触。
在示例实施例中,第一金属层16F和第二金属层26F可以包括铜(Cu)、金(Au)或它们的合金。第一金属层16F和第二金属层26F可以经由高温退火通过金属原子的相互扩散而接合。第一阻挡层16L和第二阻挡层26L可以包括钛(Ti)、钽(Ta)、氮化钛(TiN)和氮化钽(TaN)中的至少一种。
在示例实施例中,第一接合层18B和第二接合层28B可以包括氧化硅、氮化硅碳(SiCN)等。当第一接合层18B和第二接合层28B彼此接触时,第一接合层18B和第二接合层28B可以通过应用高温退火操作来接合。第一绝缘层18A和第二绝缘层28A可以包括氧化硅。例如,第一绝缘层18A和第二绝缘层28A可以包括正硅酸四乙酯(TEOS)、Tonen硅氮烷(TOSZ)、原子层沉积(ALD)氧化物、可流动化学气相沉积(FCVD)氧化物、高密度等离子体(HDP)氧化物、等离子体增强氧化(PEOX)氧化物中的至少一种,但是不限于此。
如图4中所示,每个第一主连接焊盘结构MP1可以连接至多个第一布线图案14A和/或多个第一接触件14B,以电连接至第一集成电路10TR,并且另外可以连接至多个第二布线图案24A和/或多个第二接触件24B,以电连接至第二集成电路20TR。因此,第一主连接焊盘结构MP1可以用于将信号从相应的半导体芯片外部传输或传送至半导体芯片的集成电路,或者将信号从半导体芯片的集成电路传输或传送至相应的半导体芯片外部。虚设连接焊盘结构DP可以不连接至多个第一布线图案14A或多个第二布线图案24A,并且/或者可以不连接至相应的半导体芯片的任何集成电路组件。如此,该实施例中的虚设连接焊盘结构DP不连接,以从相应的半导体芯片的任何集成电路传送任何信号或者向其传送任何信号。虚设连接焊盘结构DP可以不连接,以从两个半导体芯片中的任一个(例如,第一半导体芯片10C或第二半导体芯片20C)发送任何信号或者向其发送任何信号。在一些实施例中,虚设焊盘结构可以是完全被绝缘材料围绕的导电焊盘,并且由此不直接连接至任何其它导电组件。
在根据以上陈述的示例实施例的半导体封装件100中,虚设连接焊盘结构DP可以被布置为具有根据虚设梯度规则而改变的虚设焊盘密度。因此,可以防止在第一主连接焊盘结构MP1和虚设连接焊盘结构DP的平坦化操作中发生第一接合绝缘层10UI和第二接合绝缘层20UI的局部侵蚀,因此,可以使第一半导体芯片10C和第二半导体芯片20C的接合操作中的缺陷的发生率最小化。
图5是根据示例实施例的半导体封装件100A的截面图。图5是与图3的部分CX1对应的部分的放大图。在图5中,与图1至图4中相同的附图标记表示相同的组件。
参照图5,可以通过双镶嵌操作来形成第一连接焊盘16A和第二连接焊盘26A。第一连接焊盘16A和第二连接焊盘26A中的每一个可以具有这样的结构:在该结构中,下部(例如,距第一半导体芯片10C与第二半导体芯片20C之间的界面更远的部分)的宽度窄,并且上部(例如,更靠近第一半导体芯片10C与第二半导体芯片20C之间的界面的部分)的宽度宽。因为第一连接焊盘16A和第二连接焊盘26A的接触面积可以较大,所以可以保持第一连接焊盘16A和第二连接焊盘26A的更刚性的接合。
图6是根据示例实施例的半导体封装件200的布局图。图7是示出图6的焊盘布置的示例的示意图。图8是沿图7的线A2-A2’截取的截面图。
参照图6至图8,第一主连接焊盘结构MP1、第二主连接焊盘结构MP2和第一虚设连接焊盘结构DP1可以布置在第一半导体芯片10C与第二半导体芯片20C之间的界面处。
第一主连接焊盘结构MP1可以布置在第一主焊盘区域MPR1中,并且可以具有第一主焊盘密度D_MP1。第二主连接焊盘结构MP2可以布置在第二主焊盘区域MPR2中,并且可以具有第二主焊盘密度D_MP2。第一虚设连接焊盘结构DP1布置在第一虚设焊盘区域DPR1中,并且第一虚设焊盘区域DPR1布置在第一主焊盘区域MPR1与第二主焊盘区域MPR2之间。第一虚设连接焊盘结构DP1可以具有第一虚设焊盘密度D_DP1。在示例实施例中,第一虚设焊盘密度D_DP1可以小于第一主焊盘密度D_MP1,并且大于第二主焊盘密度D_MP2(即,D_MP2<D_DP1<D_MP1)。
在示例实施例中,第一虚设焊盘密度D_DP1可以具有根据虚设梯度规则的值。虚设梯度规则可以基于第一主焊盘密度D_MP1与第二主焊盘密度D_MP2之间的差值来确定第一虚设焊盘密度D_DP1。例如,当第一主焊盘密度D_MP1与第二主焊盘密度D_MP2之间的差值小于参考焊盘密度DCR时,第一虚设焊盘区域DPR1可以具有单一的焊盘密度,并且可以基于等式3至等式5来确定第一虚设焊盘密度D_DP1。
D_DP1=k1×D_MP1+k2×D_MP2 等式3,
k1=A_MP1/(A_MP1+A_MP2+A_DP1) 等式4,
k2=A_MP2/(A_MP1+A_MP2+A_DP1) 等式5,
其中,D_DP1是第一虚设焊盘密度,D_MP1是第一主焊盘密度,D_MP2是第二主焊盘密度,A_DP1是第一虚设焊盘区域DPR1的面积,A_MP1是第一主焊盘区域MPR1的面积,并且A_MP2是第二主焊盘区域MPR2的面积。
例如,当第一主焊盘密度D_MP1为10%,第二主焊盘密度D_MP2为8%,第一主焊盘区域MPR1和第二主焊盘区域MPR2的面积各自为(包括焊盘的总面积的)40%,并且参考焊盘密度DCR为3%时,基于等式3至等式5,第一虚设焊盘密度D_DP1可以为9.33%。
如图8中所示,多个第一主连接焊盘结构MP1可以被布置为在第一方向上彼此间隔开第一主间距P11,多个第二主连接焊盘结构MP2可以被布置为在第一方向上彼此间隔开第二主间距P12,并且多个第一虚设连接焊盘结构DP1可以被布置为在第一方向上彼此间隔开第一虚设间距P21。第一虚设间距P21可以大于第一主间距P11,并且小于第二主间距P12(即,P11<P21<P12)。
另外,当第一主焊盘区域MPR1与第二主焊盘区域MPR2之间的距离小于第一主间距P11和第一宽度W1(参见图3)之和或者第二主间距P12和第一宽度W1之和时,虚设焊盘可以不布置在第一主焊盘区域MPR1与第二主焊盘区域MPR2之间。
例如,当第一主焊盘区域MPR1和第二主焊盘区域MPR2被布置为具有彼此不同的焊盘密度,并且第一主焊盘区域MPR1与第二主焊盘区域MPR2之间的焊盘密度之差小于或等于参考焊盘密度DCR时,可以根据虚设梯度规则来确定布置在第一主焊盘区域MPR1与第二主焊盘区域MPR2之间的第一虚设焊盘区域DPR1,并且可以防止或减少在第一主连接焊盘结构MP1和第二主连接焊盘结构MP2的平坦化操作中可发生第一接合绝缘层10UI和第二接合绝缘层20UI的局部侵蚀。
图9是根据示例实施例的半导体封装件200A的布局图。
参照图9,第一主焊盘密度D_MP1与第二主焊盘密度D_MP2之间的差值可以小于或等于参考焊盘密度DCR。第一虚设连接焊盘结构DP1可以布置在第一虚设焊盘区域DPR1中,第一虚设焊盘密度D_DP1可以小于第一主焊盘密度D_MP1,并且小于第二主焊盘密度D_MP2(即,D_DP1<D_MP2<D_MP1)。
在示例实施例中,第一虚设焊盘密度D_DP1可以具有根据虚设梯度规则的值,并且可以基于参照图6至图8描述的等式3至等式5来确定第一虚设焊盘密度D_DP1。例如,当第一主焊盘密度D_MP1为10%,第二主焊盘密度D_MP2为8%,第一主焊盘区域MPR1和第二主焊盘区域MPR2的面积各自为(包括焊盘的总面积的)30%,并且参考焊盘密度DCR为3%时,基于等式3至等式5,第一虚设焊盘密度D_DP1可以为6.42%。
例如,当第一主焊盘区域MPR1和第二主焊盘区域MPR2被布置为具有彼此不同的焊盘密度,并且第一主焊盘区域MPR1与第二主焊盘区域MPR2之间的焊盘密度之差小于或等于参考焊盘密度DCR时,可以根据虚设梯度规则来确定布置在第一主焊盘区域MPR1与第二主焊盘区域MPR2之间的第一虚设焊盘区域DPR1,并且可以防止或减少在第一主连接焊盘结构MP1和第二主连接焊盘结构MP2的平坦化操作中可发生第一接合绝缘层10UI和第二接合绝缘层20UI的局部侵蚀。
图10是根据示例实施例的半导体封装件200B的布局图。
参照图10,第一主焊盘密度D_MP1与第二主焊盘密度D_MP2之间的差值可以大于参考焊盘密度DCR。虚设焊盘区域DPR可以根据虚设梯度规则被划分为n个子虚设焊盘区域,并且n个子虚设焊盘区域中的每一个的焊盘密度可以变化。例如,在图10中所示的实施例中,虚设焊盘区域DPR可以包括两个子虚设焊盘区域,并且该两个子虚设焊盘区域可以对应于第一虚设焊盘区域DPR1和第二虚设焊盘区域DPR2。然而,注意诸如“第一”、“第二”、“第三”等的序数可以简单地用作某些元件、步骤等的标签,以将这样的元件、步骤等彼此区分开。在本说明书中未使用“第一”、“第二”等进行描述的术语在权利要求中仍可以被称作“第一”或“第二”。另外,用特定序数(例如,特定权利要求中的“第一”)引用的术语可以在其它地方用不同的序数(例如,本说明书或另一权利要求中的“第二”)来描述。
例如,虚设焊盘区域DPR可以包括n个子虚设焊盘区域,并且n可以由等式6确定。
(D_MP1-D_MP2)/(DCR)-1≤n<(D_MP1-D_MP2)/(DCR) 等式6,
其中,n是自然数,DCR是参考焊盘密度,D_MP1是第一主焊盘密度,并且D_MP2是第二主焊盘密度。
另外,第k子虚设焊盘区域可以具有根据等式7的子虚设焊盘密度。在本文中,当虚设焊盘区域DPR包括n个子虚设焊盘区域时,最靠近第一主焊盘区域MPR1的子虚设焊盘区域可以被称作第一子虚设焊盘区域,并且最靠近第二主焊盘区域MPR2的子虚设焊盘区域可以被称作第n子虚设焊盘区域。
D_DPk=(n+1-k)/(n+1)×D_MP1+(k)/(n+1)×D_MP2 等式7,
其中,D_DPk是第k子虚设焊盘区域的子虚设焊盘密度,k是从1至n的自然数,D_MP1是第一主焊盘密度,并且D_MP2是第二主焊盘密度。
例如,当第一主焊盘密度D_MP1为16%,第二主焊盘密度D_MP2为10%,并且参考焊盘密度DCR为2%时,虚设焊盘区域DPR可以基于等式6包括两个子虚设焊盘区域。另外,基于等式7,第一虚设焊盘区域DPR1的第一虚设焊盘密度D_DP1可以为14%,并且第二虚设焊盘区域DPR2的第二虚设焊盘密度D_DP2可以为12%。在该实施例中,第一虚设焊盘密度D_DP1可以小于第一主焊盘密度D_MP1,第二虚设焊盘密度D_DP2可以小于第一虚设焊盘密度D_DP1,并且第二主焊盘密度D_MP2可以小于第二虚设焊盘密度D_DP2(即,D_MP2<D_DP2<D_DP1<D_MP1)。
例如,即使当第一主焊盘区域MPR1和第二主焊盘区域MPR2被布置为具有彼此不同的焊盘密度,并且第一主焊盘区域MPR1与第二主焊盘区域MPR2之间的焊盘密度之差大于参考焊盘密度DCR时,第一虚设焊盘区域DPR1和第二虚设焊盘区域DPR2也可以具有根据虚设梯度规则逐渐变化的焊盘密度,因此,可以防止或减少在第一主连接焊盘结构MP1和第二主连接焊盘结构MP2的平坦化操作中可发生第一接合绝缘层10UI和第二接合绝缘层20UI的局部侵蚀。
图11是根据示例实施例的半导体封装件200C的布局图。
参照图11,与参照图10描述的半导体封装件200B不同,在平面图中,第一虚设焊盘区域DPR1可以被布置为(例如,在三侧)围绕第一主焊盘区域MPR1,并且第二虚设焊盘区域DPR2可以被布置为(例如,在三侧)围绕第二主焊盘区域MPR2。
可以通过经连接焊盘结构以及第一接合绝缘层10UI和第二接合绝缘层20UI的金属氧化物混合接合使第一半导体芯片10C和第二半导体芯片20C附接来制造根据参照图1至图11描述的示例实施例的半导体封装件100、100A、200、200A、200B和200C。连接焊盘结构可以包括在第一主焊盘区域MPR1和第二主焊盘区域MPR2中形成的第一主连接焊盘结构MP1和第二主连接焊盘结构MP2、以及在虚设焊盘区域DPR中形成的虚设连接焊盘结构DP。在这些实施例中,可以根据虚设梯度规则来确定虚设焊盘区域DPR的焊盘密度。
示例虚设梯度规则如下。
首先,当半导体封装件包括一个主焊盘区域MPR1时,虚设焊盘区域DPR可以包括n个子虚设焊盘区域,并且n可以由等式1确定。
(D_MP1)/(DCR)-1≤n<(D_MP1)/(DCR) 等式1,
其中,n是自然数,DCR是参考焊盘密度,并且D_MP1是第一主焊盘密度。
另外,n个子虚设焊盘区域中的每一个的虚设焊盘密度D_DPk可以由等式2确定。
D_DPk=(n+1-k)/(n+1)×D_MP1 等式2,
其中,D_DPk可以是第k子虚设焊盘区域的密度,k可以是从1至n的自然数,并且D_MP1可以是第一主焊盘密度。
其次,当半导体封装件包括具有彼此不同的焊盘密度的第一主焊盘区域MPR1和第二主焊盘区域MPR2,并且第一主焊盘密度D_MP1与第二主焊盘密度D_MP2之间的差值小于参考焊盘密度DCR时,第一虚设焊盘区域DPR1可以包括单一的焊盘密度,并且可以基于等式3至等式5来确定第一虚设焊盘密度D_DP1。
D_DP1=k1×D_MP1+k2×D_MP2 等式3,
k1=A_MP1/(A_MP1+A_MP2+A_DP1) 等式4,
k2=A_MP2/(A_MP1+A_MP2+A_DP1) 等式5,
其中,D_DP1是第一虚设焊盘密度,D_MP1是第一主焊盘密度,D_MP2是第二主焊盘密度,A_DP1是第一虚设焊盘区域DPR1的面积,A_MP1为第一主焊盘区域MPR1的面积,并且A_MP2为第二主焊盘区域MPR2的面积。
第三,当半导体封装件包括具有彼此不同的焊盘密度的第一主焊盘区域MPR1和第二主焊盘区域MPR2,并且第一主焊盘密度D_MP1与第二主焊盘密度D_MP2之间的差值大于参考焊盘密度DCR时,虚设焊盘区域DPR可以包括n个子虚设焊盘区域,并且n可以由等式6确定。
(D_MP1-D_MP2)/(DCR)-1≤n<(D_MP1-D_MP2)/(DCR) 等式6,
其中,n是自然数,DCR是参考焊盘密度,D_MP1是第一主焊盘密度,并且D_MP2是第二主焊盘密度。
另外,n个子虚设焊盘区域之中的第k子虚设焊盘区域可以具有根据等式7的子虚设焊盘密度。
D_DPk=(n+1-k)/(n+1)×D_MP1+(k)/(n+1)×D_MP2 等式7,
其中,D_DPk是第k子虚设焊盘区域的密度,并且k是从1至n的自然数。例如,n可以在2至10的范围内。
总之,虚设连接焊盘结构DP可以被布置为具有根据虚设梯度规则变化的虚设焊盘密度。因此,可以减少或防止在第一主连接焊盘结构MP1和第二主连接焊盘结构MP2以及虚设连接焊盘结构DP的平坦化操作中发生第一接合绝缘层10UI和第二接合绝缘层20UI的局部侵蚀,因此,可以使第一半导体芯片10C和第二半导体芯片20C的接合操作中的缺陷的发生率最小化。
图12是根据示例实施例的半导体封装件1000的截面图。
参照图12,半导体封装件1000可以包括第一半导体芯片110C、第二半导体芯片120C、第三半导体芯片130C和第四半导体芯片140C。第一半导体芯片110C可以包括布置在第一衬底110的第一表面上的布线层114和层间绝缘膜112A,并且接合绝缘层112B、主连接焊盘116MP和虚设连接焊盘116DP可以布置在层间绝缘膜112A上。上绝缘层112C和接合绝缘层112D可以布置在第一衬底110的第二表面上。
相似地,第二半导体芯片至第四半导体芯片120C、130C和140C可以分别包括布置在第二衬底至第四衬底120、130和140的第一表面上的布线层124、134和144以及层间绝缘膜122A、132A和142A,并且接合绝缘层122B、132B和142B、主连接焊盘126MP、136MP和146MP以及虚设连接焊盘126DP、136DP和146DP可以布置在层间绝缘膜122A、132A和142A上。上绝缘层122C和132C以及接合绝缘层122D和132D可以布置在第二衬底120和第三衬底130的第二表面上。可以利用先前结合图1至图11描述的主连接焊盘布置和虚设连接焊盘布置之一来连接半导体封装件1000的相邻的半导体芯片。即,图12可以包括连接焊盘布置,用于连接对于图1至图11的实施例中的任一个的半导体封装件1000的半导体芯片。在一个实施例中,半导体封装件1000的所有半导体芯片使用相同的连接焊盘布置(例如,图1至图11的实施例之一)被接合至相邻的芯片。在另一实施例中,半导体封装件1000的特定半导体芯片可以使用不同的连接焊盘布置(例如,来自图1至图11的不同实施例)被接合至不同的相邻的芯片。这同样适用于以下进一步讨论的图13和图14。
第一半导体芯片110C还可以包括穿过第一衬底110的贯通孔118A、以及布置在第一衬底110的第二表面上并将贯通孔118A连接至主连接焊盘126MP的上布线层118B。相似地,第二半导体芯片120C和第三半导体芯片130C还可以分别包括穿过第二衬底120和第三衬底130的贯通孔128A和138A、以及布置在第二衬底120和第三衬底130的第二表面上并将贯通孔128A和138A连接至主连接焊盘136MP和146MP的上布线层128B和138B。
还可以布置围绕第一半导体芯片至第四半导体芯片110C、120C、130C和140C的顶表面和侧表面的模制材料160,并且连接凸块170可以附接到布置在第一半导体芯片110C的第一表面上的主连接焊盘116MP和虚设连接焊盘116DP。模制材料160可以包括环氧模塑化合物(EMC)等,但是在一些实施例中,模制材料160可以仅覆盖第一半导体芯片至第四半导体芯片110C、120C、130C和140C的侧表面,或者模制材料160可以被省略。
在示例实施例中,第一半导体芯片至第四半导体芯片110C、120C、130C和140C可以是存储器芯片或逻辑芯片。例如,第一半导体芯片至第四半导体芯片110C、120C、130C和140C可以都是相同类型的存储器芯片,并且可替代地,第一半导体芯片至第四半导体芯片110C、120C、130C和140C中的至少一个可以是逻辑芯片,并且第一半导体芯片至第四半导体芯片110C、120C、130C和140C中的其余半导体芯片可以是存储器芯片。
图13是根据示例实施例的半导体封装件1000A的截面图。
参照图13,半导体封装件1000A还可以包括插件500。插件500可以包括基层510、再分布层520、第一顶表面焊盘522和第一底表面焊盘524。将每个第一顶表面焊盘522电连接至第一底表面焊盘524的贯通孔(未示出)还可以布置在基层510中。插件500和第一半导体芯片110C可以通过使用第一顶表面焊盘522经由金属氧化物混合接合彼此附接。可替代地,插件500和第一半导体芯片110C可以通过连接凸块(未示出)彼此连接。
主板600可以包括基板层610和第二顶表面焊盘622,并且插件500的第一底表面焊盘524可以通过板连接端子540电连接至主板600的第二顶表面焊盘622。散热单元700还可以布置在第四半导体芯片140C上。
图14是根据示例实施例的半导体封装件2000的截面图。
参照图14,半导体封装件2000可以包括其上安装有插件500的主板600、包括附接到插件500的第一半导体芯片至第四半导体芯片110C、120C、130C和140C的子半导体封装件1000B、以及第五半导体芯片400。子半导体封装件1000B可以是参照图12描述的半导体封装件1000。半导体封装件2000可以被称作系统。
尽管图14示出了半导体封装件2000包括两个子半导体封装件1000B,但是本发明构思不限于此。例如,半导体封装件2000可以包括一个子半导体封装件1000B,或者可以包括三个或更多个子半导体封装件1000B。
第五半导体芯片400可以包括在其上的有源表面上形成有第三半导体装置412的第五衬底410、多个顶表面连接焊盘420、前表面保护层440、和附接在多个顶表面连接焊盘420上的多个连接凸块460。第五半导体芯片400可以是例如中央处理单元(CPU)芯片、图形处理单元(GPU)芯片或应用处理器(AP)芯片。多个顶表面连接焊盘420中的每一个可以包括铝、铜和镍中的至少一种。
插件500可以包括基层510、分别布置在基层510的顶表面和底表面上的第一顶表面焊盘522和第一底表面焊盘524、以及穿过基层510并将第一顶表面焊盘522连接至第一底表面焊盘524的第一布线路径530。
基层510可以包括半导体、玻璃、陶瓷或塑料。例如,基层510可以包括硅。第一布线路径530可以是连接至基层510的顶表面和/或底表面上的第一顶表面焊盘522和/或第一底表面焊盘524的布线层,或者可以是将基层510中的第一顶表面焊盘522电连接至第一底表面焊盘524的内部贯通电极。将子半导体封装件1000B电连接至插件500的连接凸块360和将第五半导体芯片400电连接至插件500的连接凸块460可以连接至第一顶表面焊盘522。
第一底部填充层380可以位于子半导体封装件1000B与插件500之间,并且第二底部填充层480可以位于第五半导体芯片400与插件500之间。第一底部填充层380和第二底部填充层480可以分别围绕连接凸块360和连接凸块460。
半导体封装件2000还可以包括在插件500上围绕子半导体封装件1000B以及第五半导体芯片400的侧表面的封装模制层900。封装模制层900可以包括例如EMC。在一些实施例中,封装模制层900可以覆盖子半导体封装件1000B以及第五半导体芯片400的顶表面。在一些其它实施例中,封装模制层900可以不覆盖子半导体封装件1000B的顶表面和第五半导体芯片400。例如,散热构件可以利用其间的热界面材料(TIM)层附接在子半导体封装件1000B和第五半导体芯片400上。TIM层可以是例如矿物油、油脂、填缝腻子、相变凝胶、相变材料焊盘或填充有颗粒的环氧树脂。散热构件可以是例如散热片、散热器、热管或液体冷却的冷板。
板连接端子540可以附接在第一底表面焊盘524上。板连接端子540可以将插件500电连接至主板600。
主板600可以包括基板层610、分别布置在基板层610的顶表面和底表面上的第二顶表面焊盘622和第二底表面焊盘624、以及穿过基板层610并将第二顶表面焊盘622连接至第二底表面焊盘624的第二布线路径630。
在一些实施例中,主板600可以是印刷电路板。例如,主板600可以是多层印刷电路板。基板层610可以包括选自酚醛树脂、环氧树脂和聚酰亚胺中的至少一种材料。
暴露出第二顶表面焊盘622和第二底表面焊盘624的阻焊层(未示出)可以形成在基板层610的顶表面和下表面中的每一个上。板连接端子540可以连接至第二顶表面焊盘622,并且外部连接端子640可以连接至第二底表面焊盘624。板连接端子540可以将第一底表面焊盘524电连接至第二顶表面焊盘622。连接至第二底表面焊盘624的外部连接端子640可以将半导体封装件2000连接至外部。
在一些实施例中,半导体封装件2000可以不包括主板600,并且插件500的板连接端子540可以用作外部连接端子。
上述半导体封装件包括封装衬底(其可以是芯片的堆叠件的第一半导体芯片的衬底,或者可以是插件或主板)、堆叠在封装衬底上的多个半导体芯片、以及可以是模制层并且可以包括散热单元的包封材料。半导体封装件通常可以被描述为半导体装置。
图15至图24是示出根据示例实施例的制造半导体封装件的方法的示意图。图15至图24示出了根据操作序列制造参照图12描述的半导体封装件1000的方法,并且图16至图24是沿图15的线A3-A3'截取的截面图。
参照图15和图16,提供了包括多个装置区域DR的第一晶圆110W。多个装置区域DR可以被布置为通过划线区域SR彼此间隔开。可以在第一晶圆110W上形成布线层114和层间绝缘膜112A。另外,还可以在第一晶圆110W中形成贯通孔118A。
参照图17,通过以下步骤来形成主连接焊盘116MP和虚设连接焊盘116DP:在层间绝缘膜112A上形成接合绝缘层112B,蚀刻接合绝缘层112B的一部分以形成开口(未示出),以及用诸如金属材料的导电材料填充开口。可以以参照图4和图5描述的第一连接焊盘16的方式相似的方式来形成主连接焊盘116MP和虚设连接焊盘116DP。接合绝缘层112B可以最初比图17中所示的厚,并且金属材料可以填充接合绝缘层112B中的孔。随后,可以发生其中金属材料的一部分和接合绝缘层112B的一部分被平坦化并被去除以形成图17中所示的较薄的层的平坦化步骤。在该工艺期间,由于主连接焊盘116MP和虚设连接焊盘116DP的(例如,根据结合图1至图11讨论的示例实施例之一布置的)布局,可以防止或减少接合绝缘层的局部侵蚀。
参照图18,可以通过执行相对于第一晶圆110W描述的操作来准备第二晶圆120W、第三晶圆130W和第四晶圆(未示出)。
然后,可以将第二晶圆120W附接在第三晶圆130W上,并且另外,可以将第一晶圆110W附接在第二晶圆120W上。在示例实施例中,在将第二晶圆120W附接在第三晶圆130W上的操作中,可以在其中第二晶圆120W上的连接焊盘(未示出)和接合绝缘层122D与第三晶圆130W上的连接焊盘(未示出)和接合绝缘层132B接触的状态下应用高温热处理。
之后,可以通过执行磨削操作以暴露出贯通孔128A来去除第二晶圆120W的厚度的一部分。尽管图18示出了其中第三晶圆130W的有源表面(或前表面)附接到第二晶圆120W的无源表面(或后表面)的示例,但是可替代地,第三晶圆130W的有源表面可以附接到第二晶圆120W的有源表面。在这种情况下,第二晶圆120W和第三晶圆130W可以以面对面的方法接合。
参照图19,可以将连接凸块170附接在第一晶圆110W的前表面上。然后,可以将承载衬底180附接在连接凸块170上。可以在第一晶圆110W与承载衬底180之间形成粘合层190。
在示例实施例中,示出了其中使用了承载衬底180的情况,但是在其它实施例中,可以省略承载衬底180或晶圆支撑系统(WSS)。
参照图20,可以将与第一晶圆至第三晶圆110W、120W和130W接合的结构颠倒(例如,翻转)。
参照图21,可以通过执行磨削操作去除第三晶圆130W的厚度的一部分来暴露出贯通孔138A。
参照图22,可以将第四晶圆140W附接在第三晶圆130W上。第四晶圆140W可以是不包括贯通孔的晶圆。然后,可以通过执行磨削操作来去除第四晶圆140W的厚度的一部分。
参照图23,可以根据要被分离为其中堆叠有第一衬底至第四衬底110、120、130和140的多个结构的划线区域SR来切割第一晶圆至第四晶圆110W、120W、130W和140W的堆叠结构。
参照图24,可以形成覆盖其中堆叠有第一衬底至第四衬底110、120、130和140的多个结构的侧表面和顶表面的模制材料160。
之后,随着承载衬底180被去除并且每个结构被单个化,可以完成半导体封装件1000(参照图12)。
图22和图23示出了在执行第四晶圆140W的磨削操作之后在其中形成模制材料160的示例,但是在其它实施例中,还可以在执行第四晶圆140W的磨削操作之前形成模制材料160,然后,可以执行第四晶圆140W的磨削操作。
尽管已经参照本发明构思的实施例示出和描述了本发明构思,但是将理解,在不脱离所附权利要求的精神和范围的情况下,可以在本文中做出形式和细节上的各种改变。
Claims (20)
1.一种半导体封装件,包括:
第一半导体芯片;
第二半导体芯片;
第一主连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的界面处,并且被布置为在与所述第一半导体芯片的顶表面平行的第一方向上彼此间隔开第一主间距,其中,所述第一主连接焊盘结构中的每一个第一主连接焊盘结构包括第一连接焊盘和第二连接焊盘,所述第一连接焊盘电连接至所述第一半导体芯片,所述第二连接焊盘电连接至所述第二半导体芯片并且接触所述第一连接焊盘;以及
第一虚设连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处,被布置为与所述第一主连接焊盘结构间隔开,并且被布置为在所述第一方向上彼此间隔开第一虚设间距,所述第一虚设间距大于所述第一主间距。
2.根据权利要求1所述的半导体封装件,还包括:
第一接合绝缘层,其布置在所述第一半导体芯片上,并且被布置为在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处具有与每一个第一连接焊盘的表面共面的表面;以及
第二接合绝缘层,其布置在所述第二半导体芯片上,被布置为在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处具有与每一个第二连接焊盘的表面共面的表面,并且接触所述第一接合绝缘层。
3.根据权利要求1所述的半导体封装件,还包括模制材料,所述模制材料围绕所述第一半导体芯片的侧表面和所述第二半导体芯片的侧表面,
其中,当从所述第一半导体芯片的顶部观看时,所述第一虚设连接焊盘结构围绕所述第一主连接焊盘结构。
4.根据权利要求1所述的半导体封装件,还包括:
第二虚设连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处,并且被布置为在所述第一方向上彼此间隔开第二虚设间距;以及
第三虚设连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处,并且被布置为在所述第一方向上彼此间隔开第三虚设间距,
其中,所述第二虚设间距大于所述第一虚设间距,并且所述第三虚设间距大于所述第二虚设间距。
5.根据权利要求4所述的半导体封装件,其中,所述第一主连接焊盘结构、所述第一虚设连接焊盘结构、所述第二虚设连接焊盘结构和所述第三虚设连接焊盘结构从所述半导体封装件的中心区域在所述第一方向上朝向所述半导体封装件的边缘按次序布置,使得所述第一主连接焊盘结构位于所述半导体封装件的所述中心区域处,并且所述第三虚设连接焊盘结构在所述第一主连接焊盘结构、所述第一虚设连接焊盘结构、所述第二虚设连接焊盘结构和所述第三虚设连接焊盘结构之中最靠近所述半导体封装件的所述边缘。
6.根据权利要求4所述的半导体封装件,其中,当从所述第一半导体芯片的顶部观看时,所述第一主连接焊盘结构具有第一主焊盘密度,当从所述第一半导体芯片的所述顶部观看时,所述第一虚设连接焊盘结构具有第一虚设焊盘密度,当从所述第一半导体芯片的所述顶部观看时,所述第二虚设连接焊盘结构具有第二虚设焊盘密度,并且当从所述第一半导体芯片的所述顶部观看时,所述第三虚设连接焊盘结构具有第三虚设焊盘密度,并且
其中,所述第一虚设焊盘密度小于所述第一主焊盘密度,所述第二虚设焊盘密度小于所述第一虚设焊盘密度,并且所述第三虚设焊盘密度小于所述第二虚设焊盘密度。
7.根据权利要求1所述的半导体封装件,其中:
所述第一主连接焊盘结构布置在第一主焊盘区域中,当从所述第一半导体芯片的顶部观看时,所述第一主连接焊盘结构具有第一主焊盘密度,
所述第一虚设连接焊盘结构布置在第一虚设焊盘区域中,并且
所述第一虚设焊盘区域包括n个子虚设焊盘区域,并且n由等式1确定,
(D_MP1)/(DCR)-1≤n<(D_MP1)/(DCR):等式1,
其中,n是自然数,DCR是参考焊盘密度,并且
第k子虚设焊盘区域具有根据等式2的子虚设焊盘密度,
D_DPk=(n+1-k)/(n+1)×D_MP1:等式2,
其中,D_DPk是所述第k子虚设焊盘区域的密度,k是从1至n的自然数,并且D_MP1是所述第一主焊盘密度。
8.根据权利要求1所述的半导体封装件,还包括第二主连接焊盘结构,所述第二主连接焊盘结构布置在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处,被布置为与所述第一主连接焊盘结构和所述第一虚设连接焊盘结构间隔开,并且被布置为在所述第一方向上彼此间隔开第二主间距,所述第二主间距大于所述第一主间距。
9.根据权利要求8所述的半导体封装件,其中:
所述第一主连接焊盘结构布置在第一主焊盘区域中,当从所述第一半导体芯片的顶部观看时,所述第一主连接焊盘结构具有第一主焊盘密度,所述第二主连接焊盘结构布置在第二主焊盘区域中,当从所述第一半导体芯片的所述顶部观看时,所述第二主连接焊盘结构具有第二主焊盘密度,所述第一虚设连接焊盘结构布置在第一虚设焊盘区域中,并且当从所述第一半导体芯片的所述顶部观看时,所述第一虚设连接焊盘结构具有第一虚设焊盘密度,
所述第一主焊盘密度与所述第二主焊盘密度之间的差小于参考焊盘密度,并且
所述第一虚设焊盘密度由等式3至等式5确定,
D_DP1=k1×D_MP1+k2×D_MP2:等式3,
k1=A_MP1/(A_MP1+A_MP2+A_DP1):等式4,
k2=A_MP2/(A_MP1+A_MP2+A_DP1):等式5,
其中,D_DP1是所述第一虚设焊盘密度,D_MP1是所述第一主焊盘密度,D_MP2是所述第二主焊盘密度,A_DP1是所述第一虚设焊盘区域的面积,A_MP1是所述第一主焊盘区域的面积,并且A_MP2是所述第二主焊盘区域的面积。
10.根据权利要求9所述的半导体封装件,其中,所述参考焊盘密度是2%至5%。
11.根据权利要求9所述的半导体封装件,其中,所述第一虚设焊盘密度小于所述第一主焊盘密度,并且所述第二主焊盘密度小于所述第一虚设焊盘密度。
12.根据权利要求9所述的半导体封装件,其中,所述第一虚设焊盘密度小于所述第一主焊盘密度,并且所述第一虚设焊盘密度小于所述第二主焊盘密度。
13.根据权利要求8所述的半导体封装件,其中:
所述第一主连接焊盘结构布置在第一主焊盘区域中,当从所述第一半导体芯片的顶部观看时,所述第一主连接焊盘结构具有第一主焊盘密度,所述第二主连接焊盘结构布置在第二主焊盘区域中,当从所述第一半导体芯片的所述顶部观看时,所述第二主连接焊盘结构具有第二主焊盘密度,
所述第一主焊盘密度与所述第二主焊盘密度之间的差大于参考焊盘密度,
所述第一虚设连接焊盘结构布置在第一虚设焊盘区域中,所述第一虚设焊盘区域包括n个子虚设焊盘区域,n由等式6确定,
(D_MP1-D_MP2)/(DCR)-1≤n<(D_MP1-D_MP2)/(DCR):等式6,
其中,n是自然数,DCR是所述参考焊盘密度,并且
第k子虚设焊盘区域具有根据等式7的子虚设焊盘密度,
D_DPk=(n+1-k)/(n+1)×D_MP1+(k)/(n+1)×D_MP2:等式7,
其中,D_DPk是所述第k子虚设焊盘区域的所述子虚设焊盘密度,k是从1至n的自然数,D_MP1是所述第一主焊盘密度,并且D_MP2是所述第二主焊盘密度。
14.一种半导体封装件,包括:
第一半导体芯片;
第二半导体芯片;
主连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的界面处,其中,所述主连接焊盘结构中的每一个主连接焊盘结构包括第一连接焊盘和第二连接焊盘,所述第一连接焊盘电连接至所述第一半导体芯片,所述第二连接焊盘电连接至所述第二半导体芯片并且接触所述第一连接焊盘;
第一虚设连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处,并且被布置为与所述主连接焊盘结构间隔开;以及
第二虚设连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处,并且被布置为与所述主连接焊盘结构间隔开,其中,所述第一虚设连接焊盘结构位于第二区域与第三区域之间的第一区域中,所述第二虚设连接焊盘结构位于所述第二区域中,所述主连接焊盘结构位于所述第三区域中,
其中,当从所述第一半导体芯片的顶部观看时,所述主连接焊盘结构具有关于所述第三区域的面积的第一主焊盘密度,当从所述第一半导体芯片的所述顶部观看时,所述第一虚设连接焊盘结构具有关于所述第一区域的面积的第一虚设焊盘密度,并且当从所述第一半导体芯片的所述顶部观看时,所述第二虚设连接焊盘结构具有关于所述第二区域的面积的第二虚设焊盘密度,并且
其中,所述第一虚设焊盘密度小于所述第一主焊盘密度,并且所述第二虚设焊盘密度小于所述第一虚设焊盘密度。
15.根据权利要求14所述的半导体封装件,其中:
所述主连接焊盘结构被布置为在与所述第一半导体芯片的顶表面平行的第一方向上彼此间隔开第一主间距,
所述第一虚设连接焊盘结构被布置为在所述第一方向上彼此间隔开第一虚设间距,所述第一虚设间距大于所述第一主间距,并且
所述第二虚设连接焊盘结构被布置为在所述第一方向上彼此间隔开第二虚设间距,所述第二虚设间距大于所述第一虚设间距。
16.根据权利要求14所述的半导体封装件,还包括:
第一接合绝缘层,其布置在所述第一半导体芯片上,并且被布置为具有与每一个第一连接焊盘的表面共面的表面;
第二接合绝缘层,其布置在所述第二半导体芯片上,被布置为具有与每一个第二连接焊盘的表面共面的表面,并且接触所述第一接合绝缘层;以及
模制材料,其围绕所述第一半导体芯片的侧表面、所述第一接合绝缘层的侧表面、所述第二接合绝缘层的侧表面和所述第二半导体芯片的侧表面。
17.一种半导体封装件,包括:
第一半导体芯片;
第二半导体芯片;
第一主连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的界面处,并且被布置为在与所述第一半导体芯片的顶表面平行的第一方向上彼此间隔开第一主间距;
第二主连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处,并且被布置为在所述第一方向上彼此间隔开第二主间距,所述第二主间距大于所述第一主间距;以及
第一虚设连接焊盘结构,其布置在所述第一半导体芯片与所述第二半导体芯片之间的所述界面处,并且被布置为在所述第一方向上彼此间隔开第一虚设间距,所述第一虚设间距大于所述第一主间距,
其中,所述第一主连接焊盘结构和所述第二主连接焊盘结构中的每一个包括:
第一连接焊盘,其电连接至所述第一半导体芯片,并且
第二连接焊盘,其电连接至所述第二半导体芯片并且接触所述第一连接焊盘。
18.根据权利要求17所述的半导体封装件,其中:
所述第一主连接焊盘结构布置在第一主焊盘区域中,当从所述第一半导体芯片的顶部观看时,所述第一主连接焊盘结构具有第一主焊盘密度,所述第二主连接焊盘结构布置在第二主焊盘区域中,当从所述第一半导体芯片的所述顶部观看时,所述第二主连接焊盘结构具有第二主焊盘密度,所述第一虚设连接焊盘结构布置在第一虚设焊盘区域中,并且当从所述第一半导体芯片的所述顶部观看时,所述第一虚设连接焊盘结构具有第一虚设焊盘密度,
所述第一主焊盘密度与所述第二主焊盘密度之间的差小于参考焊盘密度,并且
所述第一虚设焊盘密度由等式3至等式5确定,
D_DP1=k1×D_MP1+k2×D_MP2:等式3,
k1=A_MP1/(A_MP1+A_MP2+A_DP1):等式4,
k2=A_MP2/(A_MP1+A_MP2+A_DP1):等式5,
其中,D_DP1是所述第一虚设焊盘密度,D_MP1是所述第一主焊盘密度,D_MP2是所述第二主焊盘密度,A_DP1是所述第一虚设焊盘区域的面积,A_MP1是所述第一主焊盘区域的面积,并且A_MP2是所述第二主焊盘区域的面积。
19.根据权利要求17所述的半导体封装件,其中:
所述第一主连接焊盘结构布置在第一主焊盘区域中,当从所述第一半导体芯片的顶部观看时,所述第一主连接焊盘结构具有第一主焊盘密度,所述第二主连接焊盘结构布置在第二主焊盘区域中,并且当从所述第一半导体芯片的所述顶部观看时,所述第二主连接焊盘结构具有第二主焊盘密度,
所述第一主焊盘密度与所述第二主焊盘密度之间的差大于参考焊盘密度,并且
所述第一虚设连接焊盘结构布置在第一虚设焊盘区域中,并且所述第一虚设焊盘区域包括n个子虚设焊盘区域,其中,n由等式6确定,
(D_MP1-D_MP2)/(DCR)–1≤n<(D_MP1-D_MP2)/(DCR):等式6,
其中,n是自然数,DCR是所述参考焊盘密度,并且
第k子虚设焊盘区域具有根据等式7的子虚设焊盘密度,
D_DPk=(n+1-k)/(n+1)×D_MP1+(k)/(n+1)×D_MP2:等式7,
其中,D_DPk是所述第k子虚设焊盘区域的所述子虚设焊盘密度,k是从1至n的自然数,D_MP1是所述第一主焊盘密度,并且D_MP2是所述第二主焊盘密度。
20.根据权利要求19所述的半导体封装件,其中,所述参考焊盘密度为2%至5%,并且
n是2至10的自然数。
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KR20230111506A (ko) | 2022-01-18 | 2023-07-25 | 주식회사 엘지에너지솔루션 | 배터리 제어 장치 및 방법 |
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TW428243B (en) | 1999-01-22 | 2001-04-01 | United Microelectronics Corp | Method for enhancing the planarization of the die region and scribe line by using dummy pattern |
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