CN102870203A - 用于集成电路器件的增强散热的凸出tsv尖端 - Google Patents

用于集成电路器件的增强散热的凸出tsv尖端 Download PDF

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CN102870203A
CN102870203A CN2010800658213A CN201080065821A CN102870203A CN 102870203 A CN102870203 A CN 102870203A CN 2010800658213 A CN2010800658213 A CN 2010800658213A CN 201080065821 A CN201080065821 A CN 201080065821A CN 102870203 A CN102870203 A CN 102870203A
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tsv
substrate
chip
hole
pseudo
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CN102870203B (zh
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K·马瓦塔里
K·奥亚
Y·尤米达
J·A·韦斯特
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Texas Instruments Inc
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Texas Instruments Inc
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明涉及一种集成电路器件（100），其包括具有顶面的衬底（110），该顶面包括衬底焊盘（112）；以及包括半导体衬底（105）的贯穿衬底通孔（115）芯片，半导体衬底（105）包括具有有源电路的顶部半导体表面（106）和底表面（106）。顶部半导体表面（107）包括在衬底顶表面上耦合到衬底焊盘的结合连接器（109）。多个贯穿衬底通孔（TSV）包括从顶侧半导体表面延伸到凸出TSV尖端（121）的内部金属芯（125），该TSV尖端（121）从底表面向外延伸。多个TSV的至少一个是伪TSV（120），伪TSV（120）具有其凸出TSV尖端，该凸出TSV尖端没有到其上的任何电气连接，并且提供另外表面积从而增强从TSV芯片的底侧散热。

Description

用于集成电路器件的增强散热的凸出TSV尖端
技术领域
公开的实施例涉及包括贯穿衬底通孔例如贯穿硅通孔的集成电路（IC）。
背景技术
在半导体晶片上制造的大规模IC芯片中，电子信号由电流携带通过导体和晶体管。在IC芯片中由电流携带的能量以热量的形式沿电流流过IC的路径部分耗散。在IC中生成的热量P是动态功率PD和静态功率PS之和：
P=PD+PS=ACV2f+VIleak
其中A是栅极活性因数，C是全部栅极的总电容负载，V2是峰到峰电源电压摆动，f是频率，并且Ileak是泄漏电流。静态功率项PS=VIleak是由于泄漏电流Ileak耗散的静态功率。动态功率项PD=ACV2f是从IC电容负载的充电和放电耗散的动态功率。
IC芯片的另一特性是芯片上温度的不均匀分布。越来越多的功能块集成在片上系统（SOC）设计中的单芯片中。较高的功率密度块产生不均匀的温度分布，并在芯片上导致“热点或过热点”，也称为“热块或过热块”。过热点能够导致跨芯片约5℃到大致30℃的温差。由于载流子迁移率与温度成反比，因此时钟速度通常是为了芯片上的最热点而设计。因此，热设计由这些片上热点的温度驱动。同样，如果由于跨芯片的片上温度变化因此没有跨IC芯片实现均匀载流子迁移率，这可能导致信号速度和复杂化电路定时控制的变化。
包括落入式散热器、散热片和热管的散热器过去一直用来增强IC封装的热性能。另外，另一已知方法是将高导热率罩盖直接附加到芯片的后侧，从而改善散热。伴随已知实践的显著问题是其中热点被定位的芯片前侧（例如，接近晶体管切换发生处）必须用于布线，并且在连接到散热装置之前，在操作期间生成的热必须通过IC芯片的衬底的整个厚度引出到它的底侧，因此散热效率低。
发明内容
公开的实施例描述IC器件，其包含具有顶表面的衬底，该顶表面包括衬底焊盘，以及在衬底顶表面上的TSV（硅通孔）芯片。TSV芯片包含顶侧半导体表面和底表面，该顶侧半导体表面包括有源电路，其中该顶侧半导体表面包括耦合到在衬底的顶表面上的衬底焊盘的结合连接器。多个TSV在IC芯片上，其包含从顶侧半导体表面延伸到凸出TSV尖端的内金属芯，所述凸出的TSV尖端从底表面向外延伸。
多个TSV的至少一个是“伪TSV”，其在此被定义为没有用于IC器件的电气功能的TSV。除了没有任何连到其上的电器连接之外，伪TSV具有其凸出的TSV尖端。伪TSV可以与在此称为“有源TSV”的常规功能TSV对照，该常规功能TSV包括到TSV尖端的电气连接，以便为IC器件，例如为将VDD、VSS或源自TSV芯片的信号耦合到在TSV芯片上面或下面的其它电路（例如，另一IC或分立元件），提供电气功能。
所公开的实施例通过TSV芯片的衬底（例如硅）提供比常规导热路径更高导热率的路径，该路径改善从芯片顶侧到芯片底侧的传热。凸出TSV尖端显著增加TSV芯片底侧上的表面积，这显著改善辐射传热并因此改善散热。
本发明认识到因为如铜类的金属具有比大多数衬底材料更高的导热率，所以TSV的内部金属芯为源自顶侧半导体表面和底表面的传热提供降低的热阻。例如，与具有约168W/m·K的导热率的硅比较，铜具有约398W/m·K的导热率。对于衬底例如绝缘体上的半导体（SOI）、GaAs、Ge、SiC以及除块Si之外的其它半导体，衬底的导热率可能甚至更低。
附图说明
下面参考附图对示例实施例进行描述，其中：
图1是根据一公开的示例实施例的在衬底上包含TSV芯片的IC器件的侧视图，其中TSV芯片包括为源自TSV芯片的增强传热具有凸出尖端的多个伪TSV。
图2是根据一公开的示例实施例的在封装衬底上的TSV芯片上包含顶侧器件的IC器件的侧视图，其中TSV芯片包括为增强传热具有凸出尖端的多个伪TSV和多个常规有源TSV，并且其中顶侧器件通过到有源TSV的连接耦合到TSV芯片。
图3是根据所公开的示例实施例的TSV芯片的图示，其中TSV包含遍及TSV芯片基本均匀排列的多个伪TSV。
图4是根据一公开的示例实施例的包含TSV芯片的IC器件的一部分和顶侧器件的简化剖面图，该TSV芯片包括TSV阵列，该TSV阵列包括有源TSV和多个伪TSV，该顶侧器件通过到有源TSV的连接来耦合到TSV芯片。
图5是根据一公开的示例实施例的包括TSV阵列的TSV芯片的一部分的简化剖面图，该TSV阵列包括顶表面偏移TSV。
具体实施方式
图1说明根据一公开的示例实施例在衬底110上包含TSV芯片115的示例IC器件100，其中TSV芯片115包括具有凸出TSV尖端121的多个伪TSV 120，凸出TSV尖端121为源自TSV芯片的增强传热在TSV芯片115的底表面106上提供另外的表面积。TSV芯片包括含半导体的衬底105，该含半导体的衬底105包括顶侧半导体表面107和底表面106。所显示的顶侧半导体表面107包括显示为连接到TSV芯片115上连接到焊盘（未示出）的支柱（例如，可以焊接加盖的铜支柱）的结合连接器109。衬底105可以包含各种衬底，例如含硅衬底（例如块硅衬底）、硅锗、碳化硅、GaN或绝缘体上硅（SOI）衬底。
如上面提到，由于“伪TSV”的凸出TSV尖端没有到其上的任何电气连接，因此“伪TSV”是没有用于IC器件100的电气功能的TSV。伪TSV可以与常规有源TSV对照，该常规有源TSV包括到TSV尖端的电气连接以便为IC器件提供电气功能，通常传输VSS、VDD或信号到TSV芯片上面或下面的器件。如在图1中示出，全部TSV是伪TSV 120。凸出TSV尖端121的长度（或尖端高度）通常是从5到50μm，并且TSV 120的剖面面积定义尺寸（例如直径）一般是从8到40μm。尽管TSV在此一般描述为具有圆形剖面，但TSV可以具有包括例如矩形或正方形的其它剖面形状。
衬底110被显示为具有球栅阵列的（BGA）111的印刷电路板（PCB）衬底。衬底110可以包含各种其它衬底，例如有机衬底、陶瓷衬底、硅衬底或硅中介板（silicon interposer）。衬底110包括衬底焊盘112，衬底焊盘112在TSV芯片115上耦合到显示为支柱的结合连接器109。
多个伪TSV 120被示出包含从顶侧半导体表面107延伸到凸出TSV尖端121的内部金属芯125，凸出TSV尖端121从底表面106延伸。多个伪TSV 120还被示出包括介电衬层（dielectric liner）126。看到TSV尖端121没有介电衬层126，并且更一般地TSV尖端121的长度的至少50%没有介电衬层126。
图2图解根据一公开实施例的在封装衬底110上的TSV芯片115上包含顶侧器件230的IC器件200，其中TSV芯片115包括具有凸出TSV尖端121的多个伪TSV 120和多个常规有源TSV 130，其中顶侧器件230通过到有源TSV 130的连接来耦合到TSV芯片115。顶侧器件230可以包括耦合到多个有源TSV 130的至少一个IC。顶侧器件230也可以包含IC之外的器件，例如包含电容器、电阻器等，从而提供在本领域中称为“集成的各向异性芯片集成”的堆叠。
IC器件200和其它IC器件在此被示出没有罩盖。然而，在其它实施例中包括罩盖。罩盖可以用各种方式附加，包括使用导热粘合胶、片材、油脂或导热粘合剂。具有回流的焊膏是另一示例附加或连接物选项。
图3说明根据所公开实施例的TSV芯片300，其中TSV包含遍及TSV芯片300的面积或区域（在x方向和y方向上）基本均匀排列的多个伪TSV 120。例如，在一个特定实施例中，所述TSV可以具有25μm直径，并被设置以提供50μm的中心到中心间距。伪TSV 120被示出是具有正方形剖面的柱形。对于在侧面上是5mm的正方形芯片，这样的TSV芯片可以容纳10,000个TSV。在具有圆形剖面的TSV尖端的情况下，每个TSV尖端121提供等于TSV尖端121侧壁表面积（圆柱体的侧壁表面积）的“生长面积”，其等于2πrh=924μm2（其中r是TSV尖端的半径）。
尽管TSV芯片300包括周期性的伪TSV的阵列，但伪TSV也可以用非周期性图案设置。例如，伪填充TSV可以紧靠近电路热点放置，其中根据IC建模或经验，高频和高强度电路集成在电路操作期间导致非常高的温度提高。这样的伪TSV放置为从电路散热提供直接、简捷的路径，伪TSV可以因此保持IC器件在安全温度区中的可靠操作。
图4说明根据一公开实施例的包含TSV芯片315的IC器件400的一部分和顶侧器件230，TSV芯片315包括TSV阵列，该TSV阵列包括有源TSV 130和多个伪TSV 120，顶侧器件230通过到有源TSV130的连接而耦合到TSV芯片315。TSV芯片315包含具有顶面107（例如硅或硅锗表面）和底表面107的半导体衬底105。TSV芯片315包括一般含铜的多个金属互连层，包括示例的线路后端（BEOL）堆叠，该堆叠包含显示为M1到M7的第一到第七金属互连层。在该示例中，BEOL排列M1-M7可以包含铜，以及可以包含示出同样用来形成支柱焊盘328的铝的顶部（第8）金属层417，因此，BEOL堆叠可以称为8层金属堆叠。然而，公开的实施例可以应用到一般包含任何数目金属层的BEOL堆叠，其可以具有或没有顶部金属层417。
金属前介电质（PMD）239在顶表面107和M1，以及ILD层之间示出，ILD层包含被示出包含介电材料的ILD1、ILD2、ILD3、ILD4、ILD5和ILD6，该介电材料设置在多个金属互连层M1到M7的各自互连层之间，其中ILD7在M7和包括支柱焊盘328的顶部金属层417之间。ILD材料可以包含低k介电或超低k介电层，并且对于ILD1、ILD2、ILD3、ILD4、ILD5、ILD6和ILD7层的每个是不同（或相同）的材料。
尽管TSV芯片315显示TSV 120、130都在定义它们的TSV终止金属互连层的M1终止，但在其它实施例中，TSV终止金属互连层可以在M1上面的金属层（包括顶部金属互连层（在图4中示出的M7））终止。被显示为晶体管218的有源电路在邻近伪TSV120的一个的顶表面107上形成。尽管没有示出，但晶体管218由包含M1、M2、M3、M4等和相关通孔的许多可能连接选项的一个耦合到TSV IC 315上的其它器件或组件，如在图4中示出。
可见有源TSV 130通过衬底105为到TSV芯片315的顶表面106上的顶侧器件230的连接提供馈电，芯片315耦合到支柱焊盘328上的支柱109，其中支柱109如显示的被耦合到衬底110上的支柱焊盘112。可见伪TSV 120的尖端121未电气连接。由于伪TSV 120被示出嵌入在M1下面并在M1终止，因此在伪TSV 120上面的体积变得可用于路由互连金属线。TSV IC 315被示出在伪TSV 120上面包括M4路由线或定线（routing line）251和M6路由线252。尽管没有示出，但路由线251和252在TSV芯片315上各种电路之间提供互连。TSV120和130包含可见从充当TSV终止金属互连层的M1向下延伸通过底表面107的TSV内部金属芯125（例如铜）。内部金属芯125被示出由扩散势垒金属（例如Ta、TaN、Ti、TiN、Mn或Ru，或其组合）129围绕，然后由外介电衬层（例如SiO2、PSG或SiN，或其组合）126围绕。在介电衬层126上形成的扩散势垒金属129构成TSV 120、130，并在已知显著降低少数载流子寿命的高活动金属TSV芯材料（例如硅中铜）的情况下，防止TSV内芯125材料逃逸而进入衬底105，并防止引起例如显著增加的结漏或晶体管阈值电压（Vt）的移位的问题。
先通孔、相关中通孔和后通孔工艺可以用来形成公开的TSV IC。先通孔方案描述一种顺序，其中，衬底（例如硅）通孔在晶片薄化之前从晶片的前侧蚀刻，并介电绝缘，然后在BEOL互连布线层建立之前金属化。常规的先通孔工艺在晶体管形成之前形成TSV。先通孔工艺的变体是中通孔工艺，其中，在晶体管形成之后，但在BEOL布线层或层级完成之前，进行TSV蚀刻并用导电内部金属芯填充。在后通孔方案中，BEOL布线层首先建立，并且通孔步骤在BEOL布线之后并在晶片薄化之前由从顶侧的蚀刻和内部金属芯填充工艺完成，或在BEOL布线和晶片薄化之后蚀刻和内部金属芯填充工艺到晶片的底侧完成。
在晶片薄化之后的后通孔形成的情况中，在一个实施例中的TSV是在此定义为包括TSV尖端的TSV的“顶表面偏移TSV”，该TSV尖端从TSV芯片的底侧凸出并延伸含半导体的衬底的厚度的≥85%，但没有达到衬底的顶表面，例如离开衬底的顶表面2.5到8μm。晶片的厚度在晶片薄化（例如背磨）之后例如可以是约30到50μm，该晶片薄化一般在后通孔TSV蚀刻之前执行。在该实施例中，目标蚀刻深度取决于衬底（例如硅）厚度、其跨晶片的厚度不均匀性以及使用的蚀刻工具的能力（蚀刻均匀性）。减小从TSV到顶表面的距离改善了冷却效率。在该实施例中，全部TSV都是伪TSV。顶表面偏移TSV允许晶体管的任意放置和金属定线或路由，因此在不损失可用芯片面积的情况下允许增强的冷却。
图5是根据一公开实施例的包括TSV阵列的TSV芯片500的一部分的简化剖面图，该TSV阵列包括顶表面偏移TSV 520。可见TSV 520在与晶体管218和TSV芯片500上其它器件关联的扩散的垂直范围之下的顶表面107之下终止。晶体管218在标识为TSV 520’的TSV之上示出。TSV芯片500示出顶面偏移TSV怎样允许电路（例如晶体管、二极管电阻器等）在TSV的顶表面107中或在顶表面107上形成，因此在不损失TSV芯片500可用面积的情况下允许增强的冷却。
提供用于形成具有顶表面偏移TSV 520的TSV芯片500的一个示例方法，通过铜内部金属芯工艺对其进行描述。用于TSV的后通孔的通孔由合适的蚀刻工艺形成，继之以任选的介电衬层沉积，然后是势垒层和种子沉积，然后电化学铜沉积从而用导致相对薄的场（横向于TSV通孔）沉积的方法填充通孔。在场区域上的铜和势垒层可以然后移除（例如，湿法剥除或CMP），继之以常规衬底（例如硅）干法回蚀，从而产生从衬底的底表面延伸出的凸出TSV尖端。干法回蚀可以用来同样将介电衬层凹入（如果存在）。
用于公开实施例的示例应用包括高功率耗散应用，包括模拟、功率管理和应用处理器。然而，各种其它应用可以从公开实施例受益。在顶侧半导体表面上形成的有源电路包含电路元件，该电路元件一般包括晶体管、二极管、电容器和电阻器，以及信号线和将这些各种电路元件互连的其它电导体。
公开实施例可以整合进入各种工艺流程，从而形成各种器件和相关产品。半导体衬底可以在其中和/或其上的层包括各种元件。这些可以包括势垒层、其它介电层、器件结构，包括源极区、漏极区、位线、基极、发射极、集电极、导线、导电通孔的有源元件和无源元件等。此外，公开实施例可以用于包括双极、CMOS、BiCMOS和MEMS的各种工艺。
因此，这里意图覆盖具有在示例实施例背景下描述的特征或步骤的一个或更多的不同组合的实施例，所述示例实施例具有这样特征或步骤的全部或仅一些特征。本领域技术人员会意识到许多其它实施例和变化在本要求发明的保护范围内也是可能的。

Claims (6)

1.一种集成电路器件，包含：
第一衬底，所述第一衬底具有包括衬底焊盘的顶表面；
第二衬底，所述第二衬底具有包括电路的第一和第二表面；
结合连接器，所述结合连接器在所述第一表面上并耦合到所述衬底焊盘，以及
多个贯穿通孔，每个通孔都包含从所述第一表面通过所述第二衬底延伸到所述第二表面的金属芯，并具有从所述第二表面向外凸出的尖端；所述多个通孔包括在各自焊盘和所述电路之间提供电气连接路径的有源通孔和提供散热路径的伪通孔。
2.根据权利要求1所述的器件，其中所述金属芯包含铜；并且每个通孔进一步包含在势垒层之上的介电衬层，所述介电衬层覆盖所述凸出尖端的长度的小于50%。
3.根据权利要求2所述的器件，其中所述凸出尖端的所述长度是至少5μm。
4.根据权利要求3所述的器件，其中所述伪通孔布置成均匀阵列。
5.根据权利要求2所述的器件，其中所述电路进一步包括多个金属互连层；以及所述通孔连接到所述多个金属互连层的第一层。
6.根据权利要求1所述的器件，其中所述多个贯穿衬底通孔包括在与所述电路关联的扩散的垂直范围之下终止的多个顶表面偏移通孔。
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