WO2011044796A1 - 一种具有扫描链的集成电路和芯片测试方法 - Google Patents

一种具有扫描链的集成电路和芯片测试方法 Download PDF

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Publication number
WO2011044796A1
WO2011044796A1 PCT/CN2010/076448 CN2010076448W WO2011044796A1 WO 2011044796 A1 WO2011044796 A1 WO 2011044796A1 CN 2010076448 W CN2010076448 W CN 2010076448W WO 2011044796 A1 WO2011044796 A1 WO 2011044796A1
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Prior art keywords
input
scan
output
interface group
integrated circuit
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PCT/CN2010/076448
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English (en)
French (fr)
Inventor
谢武洪
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炬力集成电路设计有限公司
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Application filed by 炬力集成电路设计有限公司 filed Critical 炬力集成电路设计有限公司
Priority to EP10823027.7A priority Critical patent/EP2428808B1/en
Publication of WO2011044796A1 publication Critical patent/WO2011044796A1/zh
Priority to US13/359,015 priority patent/US8438439B2/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3172—Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing

Definitions

  • the invention belongs to the field of integrated circuit technology, and in particular relates to an integrated circuit and a chip testing method with a scan chain.
  • the way to test the digital logic portion of a chip composed of large scale integrated circuits is usually a scan chain test.
  • the scan chain consists of scan registers.
  • the general structure of the non-scan register is shown in Figure 1A.
  • the data output (q) of the register gets the value of the data input (d) and remains until the next rising edge of the clock. Update to the value of the new data input (d).
  • the general structure of the scan register is shown in Figure 1B. Compared to the non-scan register, the scan register adds a data input selector to the data input.
  • the register data input d' is d
  • the register data input d' is the scan data input scan_in
  • the output of the register (q/scan_out) is the scan enable signal
  • the value of (scan_enable) can be different to get the value of d or scan_in.
  • the data output q/scan_out of the previous scan register is connected to the next scan data input scan_in to form a long register strip called the scan chain (scan). Chain).
  • the original design sketch without the scan chain is inserted, as shown in FIG. 1D, is a full scan design sketch after inserting the scan chain.
  • Registers on the scan chain have scan-controllable and scan-observable characteristics.
  • Automatic test vector generation by controlling the clock connected to each scan register with the scan enable signal and the first scan input signal (scan_in) connected to the chip pins (Automatic Test Program The Generation, ATPG) tool can control the value of the data output of any scan register on the entire scan chain. It can also obtain the data of any scan register on the scan chain based on the last scan output signal (scan_out) connected to the chip pin.
  • Scanning chain test can be performed on each packaged chip.
  • the corresponding external pins pin1, pin2, pin4., and pin5 are used as the available pins of the scan chain after the input and output interfaces io1, io2, io6, and io7 are packaged.
  • the structure of the scan chain is shown in Figure 2D.
  • the present invention provides an embodiment of an integrated circuit having a scan chain, which can reduce the test time of the integrated circuit and reduce the test cost.
  • Another object of embodiments of the present invention is to provide a chip testing method.
  • an integrated circuit having a scan chain the integrated circuit further includes a first interface group, a second interface group, and a scan data selector;
  • the first interface group and the second interface group each include at least two input and output interfaces that can be packaged as external pins of the integrated circuit;
  • Each input/output interface of the first interface group is connected in one-to-one correspondence with an input end of the scan data selector, and an output end of the scan data selector is connected to a scan data input end of the scan chain;
  • the scan data output end of the scan chain is connected to each input and output interface of the second interface group;
  • the scan data selector is configured to select, according to a package type indication signal input to the control end thereof, data on the input/output interface corresponding to the indication signal in the first interface group for output.
  • Another object of embodiments of the present invention is to provide an integrated circuit having a scan chain, the integrated circuit including a plurality of scan chain units, each scan chain unit including a first interface group, a second interface group, a scan chain, and a scan Data selector
  • the first interface group and the second interface group each include at least two input and output interfaces that can be packaged as external pins of the integrated circuit;
  • Each input/output interface of the first interface group is connected in one-to-one correspondence with an input end of the scan data selector, and an output end of the scan data selector is connected to a scan data input end of the scan chain;
  • the scan data output end of the scan chain is connected to each input and output interface of the second interface group;
  • the scan data selector is configured to select, according to a package type indication signal input to the control end thereof, data on the input/output interface corresponding to the indication signal in the first interface group for output.
  • Another object of the embodiments of the present invention is to provide an integrated circuit having a scan chain, the integrated circuit further comprising a clock interface group and a clock signal selector;
  • the clock interface group includes at least two input and output interfaces that can be packaged as external pins of an integrated circuit
  • Each input/output interface of the clock interface group is connected in one-to-one correspondence with an input end of the clock signal selector, and an output end of the clock signal selector is connected to a scan clock input end of the scan chain;
  • the clock signal selector is configured to select, according to a package type indication signal input to the control end thereof, a clock signal on the input/output interface corresponding to the indication signal in the clock interface group to be output to a scan clock input end of the scan chain.
  • Another object of the present invention is to provide an integrated circuit having a scan chain, wherein the integrated circuit further includes an enable interface group and an enable signal selector;
  • Each of the enabled interface groups includes at least two input and output interfaces that can be packaged as external pins of the integrated circuit;
  • the input and output interfaces of the enable interface group are connected in one-to-one correspondence with the input ends of the enable signal selector, and the output end of the enable signal selector is connected to the scan enable input end of the scan chain;
  • the enable signal selector is configured to select, according to a package type indication signal input to the control end thereof, a scan that outputs an enable signal on the input/output interface corresponding to the indication signal in the enabled interface group to the scan chain. Enable the input.
  • Another object of the embodiments of the present invention is to provide a chip testing method, wherein the chip includes a first pin, a second pin, a scan chain, a first interface group, a second interface group, and scan data selection.
  • Each of the first interface group and the second interface group respectively includes at least two input and output interfaces, one of the input and output interfaces of the first interface group is connected to the first pin, and one of the input and output interfaces of the second interface group is Two pin connection;
  • Each input and output interface of the first interface group is connected in one-to-one correspondence with an input end of the scan data selector, and an output end of the scan data selector is connected to a scan data input end of the scan chain, the scan The scan data output end of the chain is connected to each input and output interface of the second interface group;
  • the chip test method includes:
  • the scan data selector selects to input the test input data to the scan data input end according to the package type information of the chip
  • the scan chain responds to the test input data, and outputs test output data from the scan data output end;
  • the test output data is read from the second pin.
  • the scan data selector selects the data on the input/output interface corresponding to the indication signal in the first interface group to output to each input in the second interface group according to the package type indication signal input to the control end thereof.
  • the output interface can greatly increase the number of scan chains for various package types with different functions of the chip, thereby greatly saving the test cost of the integrated circuit and improving the test efficiency of the integrated circuit.
  • 1A is a schematic structural diagram of a non-scan register provided by the prior art
  • 1B is a schematic structural diagram of a scan register provided by the prior art
  • 1C is a schematic diagram of an original design provided by the prior art without an inserted scan chain
  • 1D is a schematic diagram of a full scan design of an inserted scan chain provided by the prior art
  • FIGS. 2A, 2B, and 2C are schematic diagrams of three different package types of the same integrated circuit provided by the prior art
  • FIGS. 2A, 2B, and 2C are schematic structural views of a scan chain provided by the prior art for the chip shown in FIGS. 2A, 2B, and 2C;
  • FIG. 3 is a structural block diagram of an integrated circuit with a scan chain according to a first embodiment of the present invention
  • FIG. 4 is a structural block diagram of an integrated circuit with a scan chain according to a second embodiment of the present invention.
  • 5A and 5B are schematic diagrams showing the structure of an integrated circuit having a scan chain in a package type 1 and a package 2 type according to an embodiment of the present invention
  • FIG. 6 is a structural block diagram of an integrated circuit with a scan chain according to a third embodiment of the present invention.
  • FIG. 7 is a structural block diagram of an integrated circuit with a scan chain according to a fourth embodiment of the present invention.
  • FIG. 8 is a structural block diagram of an integrated circuit with a scan chain according to a fifth embodiment of the present invention.
  • FIG. 9 is a structural block diagram of an integrated circuit with a scan chain according to a sixth embodiment of the present invention.
  • FIG. 10A and FIG. 10B are schematic diagrams showing the structure of an integrated circuit having a scan chain in a package type 1 and a package 2 type according to an embodiment of the present invention
  • FIG. 11 is a flow chart showing an implementation of a chip testing method according to an embodiment of the invention.
  • the scan data selector selects the data on the input/output interface corresponding to the indication signal in the first interface group to output to each input in the second interface group according to the package type indication signal input to the control end thereof.
  • the output interface can greatly increase the number of scan chains for various package types with different functions of the chip, thereby greatly saving the test cost of the integrated circuit and improving the test efficiency of the integrated circuit.
  • FIG. 3 shows the structure of an integrated circuit having a scan chain according to a first embodiment of the present invention, and for convenience of explanation, only parts related to the embodiment of the present invention are shown.
  • the integrated circuit with scan chain 13 includes a first interface group 11, a second interface group 14, and a scan data selector 12.
  • the scan chain 13 includes a scan data input terminal, a scan data output terminal, a scan clock input terminal, and a scan enable input terminal. among them:
  • the first interface group 11 and the second interface group 14 each include at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the first interface group 11 are connected in one-to-one correspondence with the input terminals of the scan data selector 12, and the output end of the scan data selector 12 is connected to the scan data input terminal SI of the scan chain 13.
  • the scan data output terminal SO of the scan chain 13 is connected to the respective input and output interfaces of the second interface group 14.
  • the scan data selector 12 selects the data on the input/output interface corresponding to the indication signal in the first interface group 11 to be output to the scan chain 13 according to the package type indication signal input to its control terminal (not shown). Scan data input SI.
  • the package type indication signal is used to indicate the package type of the integrated circuit.
  • the integrated circuits of the embodiments of the present invention may be packaged into different types. At each package type, at least one of the first interface groups 11 is packaged as an external pin, and at least one of the second interface groups 14 The input and output interfaces are packaged as external pins.
  • FIG. 4 shows the structure of an integrated circuit having a scan chain according to a second embodiment of the present invention, and for convenience of explanation, only parts related to the embodiment of the present invention are shown.
  • the integrated circuit adds a clock interface group 15 and a clock signal selector 16 to the integrated circuit shown in FIG.
  • the clock interface group 15 includes at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the clock interface group 15 are connected in one-to-one correspondence with the input terminals of the clock signal selector 16, and the output of the clock signal selector 16 is connected to the scan clock input terminal CLK of the scan chain 13.
  • the clock signal selector 16 selects a clock signal on the input/output interface corresponding to the indication signal in the clock interface group 15 to be output to the scan chain 13 according to the package type indication signal input to its control terminal (not shown). Scan clock input.
  • At least one of the input and output interfaces of the clock interface group 15 is packaged as an external pin under each package type of the integrated circuit.
  • enable interface group 17 and the enable signal selector 18 can also be added to the integrated circuit of this embodiment.
  • the enable interface group 17 includes at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the enable interface group 17 are connected in one-to-one correspondence with the input terminals of the enable signal selector 18.
  • the output end of the enable signal selector 18 is connected to the scan enable input Scan_enable of the scan chain 13.
  • the enable signal selector 18 selects an enable signal output on the input/output interface corresponding to the indication signal in the enable interface group 17 according to the package type indication signal input to its control terminal (not shown).
  • At each package type of the integrated circuit at least one of the input interface groups 17 is packaged as an external pin.
  • the input and output interface package1_fun1_io1 in the first interface group is packaged as the external pin fun1_pin
  • the input and output interface package1_fun1_io2 in the second interface group is packaged as the external pin fun1_pin2.
  • the available pins of the scan chain are fun1_pin1 and fun1_pin2. Since the input/output interface package1_fun1_io1 in the first interface group is packaged as the external pin fun1_pin1 under the package type 1, the scan data selector 12 is input thereto.
  • the control type of the control type indicates that the data of the input/output interface package1_fun1_io1 in the first interface group is output to the scan data input end of the scan chain, so that the data input from the external pin fun1_pin1 is scanned as the package type 1
  • the scan data input signal of the chain scan_chain Since the input/output interface package1_fun1_io1 in the first interface group is packaged as the external pin fun1_pin1 under the package type 1, the scan data selector 12 is input thereto.
  • the control type of the control type indicates that the data of the input/output interface package1_fun1_io1 in the first interface group is output to the scan data input end of the scan chain, so that the data input
  • the output of the scan chain scan_chain is transferred to the input and output interfaces package1_fun1_io2 and package2_fun2_io2 in the second interface group. Since the input/output interface package1_fun1_io2 in the second interface group is encapsulated as the external pin fun1_pin2 in this package type 1, the data output to the input/output interface package1_fun1_io2 in the second interface group can be output through the external pin fun1_pin2. So that the tester can get the output signal of the scan chain scan_chain.
  • the input/output interface package2_fun2_io1 in the first interface group is packaged as the external pin fun2_pin1
  • the input/output interface package2_fun2_io2 in the second interface group is packaged as the external pin fun2_pin2.
  • the available pins of the scan chain are fun2_pin1 and fun2_pin2. Since the input/output interface package2_fun2_io1 in the first interface group is packaged as the external pin fun2_pin1 under the package type 2, the scan data selector 12 is input thereto.
  • the control type of the control type indicates that the data of the input/output interface package2_fun2_io1 in the first interface group is output to the scan data input end of the scan chain 13, so that the data input from the external pin fun2_pin1 is used as the package type 2 Scan data input signal of scan chain scan_chain.
  • the output of the scan chain scan_chain is transferred to the input and output interfaces package1_fun1_io2 and package2_fun2_io2 in the second interface group. Since the input/output interface package2_fun2_io2 in the second interface group is encapsulated as the external pin fun2_pin2 in this package type 2, the data output to the input/output interface package2_fun2_io2 in the second interface group can be output through the external pin fun2_pin2 So that the tester can get the output signal of the scan chain scan_chain.
  • Fig. 6 shows the structure of an integrated circuit having a scan chain according to a third embodiment of the present invention, and for convenience of explanation, only parts related to the embodiment of the present invention are shown.
  • the integrated circuit with scan chain includes a plurality of scan chain units 1, each scan chain unit 1 including a first interface group 11, a second interface group 14, a scan chain 13, and a scan data selector 12.
  • the scan chain 13 includes a scan data input terminal, a scan data output terminal, a scan clock input terminal, and a scan enable input terminal. among them:
  • the first interface group 11 and the second interface group 14 each include at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the first interface group 11 are connected in one-to-one correspondence with the input terminals of the scan data selector 12, and the output of the scan data selector 12 is connected to the scan data input terminal SI of the scan chain 13.
  • the scan data output terminal SO of the scan chain 13 is connected to the respective input and output interfaces of the second interface group 14.
  • the scan data selector 12 selects the data on the input/output interface corresponding to the indication signal in the first interface group 11 to be output to the scan chain 13 according to the package type indication signal input to its control terminal (not shown). Scan data input SI.
  • the package type indication signal is used to indicate the package type of the integrated circuit.
  • the integrated circuits of the embodiments of the present invention may be packaged into different types. Under each package type, at least one of the input and output interfaces of each of the first interface groups 11 is packaged as an external pin, and each of the second interface groups 14 At least one of the input and output interfaces is packaged as an external pin.
  • the number of input and output interfaces included in the first interface group in each scan chain unit 1 may be the same or different, and the number of input and output interfaces included in the second interface group in each scan chain unit 1 may be the same. , can also be different.
  • Fig. 7 shows the structure of an integrated circuit having a scan chain according to a fourth embodiment of the present invention, and for convenience of explanation, only parts related to the embodiment of the present invention are shown.
  • the integrated circuit adds a clock control unit 2 to the integrated circuit shown in FIG. 6, which includes a clock interface group 15 and a clock signal selector 16.
  • the clock interface group 15 includes at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the clock interface group 15 are connected in one-to-one correspondence with the input terminals of the clock signal selector 16, and the output of the clock signal selector 16 is connected to the scan clock input terminal CLK of the scan chain 13.
  • the clock signal selector 16 selects a clock signal on the input/output interface corresponding to the indication signal in the clock interface group 15 to be output to the scan chain 13 according to the package type indication signal input to its control terminal (not shown). Scan clock input.
  • an enable control unit 3 can be added to the integrated circuit shown in FIG. 7, and the enable control unit 3 includes an enable interface group 17 and an enable signal selector 18.
  • the enable interface group 17 includes at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the enable interface group 17 are connected in one-to-one correspondence with the input terminals of the enable signal selector 18.
  • the output end of the enable signal selector 18 is connected to the scan enable input Scan_enable of the scan chain 13.
  • the enable signal selector 18 selects an enable signal output on the input/output interface corresponding to the indication signal in the enable interface group 17 according to the package type indication signal input to its control terminal (not shown).
  • Fig. 8 shows the structure of an integrated circuit having a scan chain according to a fifth embodiment of the present invention, and for convenience of explanation, only parts related to the embodiment of the present invention are shown.
  • the integrated circuit with scan chain also includes a clock interface group 15 and a clock signal selector 16.
  • the scan chain 13 includes a scan clock input terminal, a scan data input terminal, a scan data output terminal, and a scan enable input terminal. among them:
  • the clock interface group 15 includes at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the clock interface group 15 are connected in one-to-one correspondence with the input terminals of the clock signal selector 16, and the output of the clock signal selector 16 is connected to the scan clock input terminal CLK of the scan chain 13.
  • the clock signal selector 16 selects a clock signal on the input/output interface corresponding to the indication signal in the clock interface group 15 to be output to the scan chain 13 according to the package type indication signal input to its control terminal (not shown). Scan clock input.
  • the integrated circuits of the embodiments of the present invention may be packaged in different types, and at each package type, at least one of the input and output interfaces of the clock interface group 15 is packaged as an external pin.
  • the integrated circuit further includes an enable interface group 17 and an enable signal selector 18 in the integrated circuit shown in FIG.
  • the scan chain 13 further includes a scan enable input, a scan data input terminal, a scan data output terminal, and a scan clock input terminal. among them:
  • the enable interface group 17 includes at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the enable interface group 17 are connected in one-to-one correspondence with the input terminals of the enable signal selector 18.
  • the output end of the enable signal selector 18 is connected to the scan enable input of the scan chain 13.
  • the enable signal selector 18 selects an enable signal output on the input/output interface corresponding to the indication signal in the enable interface group 17 according to the package type indication signal input to its control terminal (not shown).
  • At each package type of the integrated circuit at least one of the input interface groups 17 is packaged as an external pin.
  • FIG. 9 shows the structure of an integrated circuit having a scan chain according to a sixth embodiment of the present invention, and for convenience of explanation, only parts related to the embodiment of the present invention are shown.
  • the integrated circuit with scan chain also includes an enable interface group 17 and an enable signal selector 18.
  • the scan chain 13 includes a scan enable input, a scan data input terminal, a scan data output terminal, and a scan clock input terminal. among them:
  • the enable interface group 17 includes at least two input and output interfaces that can be packaged as external pins of an integrated circuit.
  • the input and output interfaces of the enable interface group 17 are connected in one-to-one correspondence with the input terminals of the enable signal selector 18.
  • the output end of the enable signal selector 18 is connected to the scan enable input Scan_enable of the scan chain 13.
  • the enable signal selector 18 selects an enable signal output on the input/output interface corresponding to the indication signal in the enable interface group 17 according to the package type indication signal input to its control terminal (not shown).
  • At each package type of the integrated circuit at least one of the input interface groups 17 is packaged as an external pin.
  • FIG. 10A and FIG. 10B are schematic diagrams showing the structure of an integrated circuit having a scan chain in a package type 1 and a package 2 type according to an embodiment of the present invention.
  • FIG. 11 is a flowchart showing an implementation of a chip testing method according to an embodiment of the present invention.
  • the chip includes a first pin, a second pin, a scan chain, a first interface group, a second interface group, and a scan data selector. among them:
  • the first interface group and the second interface group respectively comprise at least two input and output interfaces, one of the input and output interfaces of the first interface group is connected to the first pin, and one of the input and output interfaces of the second interface group and the second reference The feet are connected.
  • Each input and output interface of the first interface group is connected with the input end of the scan data selector one by one, and the output end of the scan data selector is connected with the scan data input end of the scan chain, and the scan data output end and the second interface of the scan chain are connected.
  • Each input and output interface of the group is connected.
  • step S101 test input data is input from the first pin
  • step S102 the scan data selector selects a corresponding input/output interface in the first interface group according to the package type information of the chip, and inputs test input data to the scan data input end;
  • step S103 the scan chain responds to the test input data, and outputs test output data from the scan data output end to each input/output interface in the second interface group;
  • step S104 test output data is read from the second pin.
  • the integrated circuit with the scan chain provided by the embodiment of the invention is particularly suitable for single core chips of various package types, especially when the single core chip has a large difference in package functions under different package types, the scan chain can be greatly increased.
  • the number thus reducing the number of registers per scan chain, greatly saving chip test cost and time, and improving chip test efficiency.
  • the scan data selector selects the data on the input/output interface corresponding to the indication signal in the first interface group to output to each input in the second interface group according to the package type indication signal input to the control end thereof.
  • the output interface so that the input and output interfaces of the corresponding package can be used as the available pins of the scan chain under different package types of the integrated circuit, thereby greatly increasing the number of scan chains in the integrated circuit and reducing the number of registers in a single scan chain. , thereby greatly reducing the testing cost of the integrated circuit and improving the testing efficiency of the integrated circuit.
  • the scan clock signal and the scan enable signal of the scan chain under different package types of the integrated circuit can be flexibly controlled.

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Description

一种具有扫描链的集成电路和芯片测试方法 技术领域
本发明属于集成电路技术领域，尤其涉及一种具有扫描链的集成电路和芯片测试方法。
背景技术
对由大规模集成电路构成的芯片的数字逻辑部分进行测试的方式通常为扫描链测试。扫描链由扫描寄存器组成。非扫描寄存器的一般结构如图1A所示，在时钟（clk）的上升沿，寄存器的数据输出端（q）得到数据输入端（d）的值，并保持到下一时钟上升沿时，再更新为新的数据输入端（d）的值。扫描寄存器的一般结构如图1B所示，相对于非扫描寄存器，扫描寄存器在数据输入端增加了一个数据输入选择器，在非扫描使能（即scan_enable=0）时，寄存器数据输入d′为d，在扫描使能（即scan_enable=1）时，寄存器数据输入d′为扫描数据输入scan_in，在时钟（clk）的上升沿，寄存器的输出（q/scan_out）得到的值依扫描使能信号（scan_enable）的值不同可以得到d或scan_in的值。前一个扫描寄存器的数据输出端q/scan_out与后一个的扫描数据输入scan_in连接在一起，可以形成一个长的寄存器条，称为扫描链（scan chain）。如图1C所示，为没有插入扫描链的原始设计简图，如图1D所示，为插入扫描链后的全扫描设计简图。
在扫描链上的寄存器具有扫描可控制与扫描可观测的特性。通过控制连接每个扫描寄存器的时钟与扫描使能信号及第一个与芯片引脚相连的扫描输入信号（scan_in），自动测试向量产生（Automatic Test Program Generation，ATPG）工具可以控制整条扫描链上的任意一个扫描寄存器的数据输出端的值，也可以根据最后一个与芯片引脚相连的扫描输出信号（scan_out）得到扫描链上任意一个扫描寄存器的数据输出端的值，这样，在扫描使能状态（即scan_enable=0）时，对扫描寄存器置初值，切换到非扫描使能状态（即scan_enable=0），即正常的数字电路的功能电路本身时，让时钟（clk）活动一次，功能电路下的逻辑数据输入（d）被锁存到寄存器输出（q/scan_out），再切换到扫描使能状态（scan_enable=1），把寄存器的值移位输出，与预先知道的应该得到的值对比，就知道电路本身有无生产过程中导致的制造缺陷。
通常情况下，对于一个集成电路，为了满足不同的市场需求，可能需要进行多种类型的封装，那么，为了确保所有的封装都可以进行扫描链测试，就需要找出每种封装类型下均会被封装为外部引脚的输入输出接口，即每种封装类型下被封装为外部引脚的输入输出接口的交集，用这些输入输出接口的交集对应的外部引脚作为扫描链的可用引脚，才可以确保在所有的封装类型下都可以进行扫描链测试。请参阅图2A、2B和2C，是同一芯片的三种不同封装类型，只有输入输出接口io1、io2、io6、io7会在三种封装下都被封装为外部引脚，此时，为了确保可以对每种封装的芯片都可以进行扫描链测试，一般仅将输入输出接口io1、io2、io6、io7封装后对应的外部引脚pin1、pin2、pin4.、pin5作为扫描链的可用引脚，其扫描链的结构如图2D所示。
这种方法对于功能重叠度高的封装来说是可行的，但是如果各种封装差异很大，每种封装类型下均被封装为外部引脚的输入输出接口的数目就会很少，相应的，可以插入的扫描链的条数也会变少，在设计较大的情况下，每条扫描链的寄存器个数会很多。由于单条扫描链的寄存器个数越多，测试时间越长，测试成本越大，所以这种方法会极大地增加测试成本和测试时间。
 技术问题
本发明提供一种具有扫描链的集成电路的实施例，能够减少集成电路的测试时间、降低测试成本。
本发明实施例的另一目的在于提供一种芯片测试方法。
 技术解决方案
本发明实施例是这样实现的，一种具有扫描链的集成电路所述集成电路还包括第一接口组、第二接口组以及扫描数据选择器；
所述第一接口组和第二接口组各自分别包括至少两个可封装为集成电路外部引脚的输入输出接口；
所述第一接口组的各输入输出接口与所述扫描数据选择器的输入端一一对应连接，所述扫描数据选择器的输出端与所述扫描链的扫描数据输入端连接；
所述扫描链的扫描数据输出端与所述第二接口组的各输入输出接口连接；
所述扫描数据选择器用于根据输入到其控制端的封装类型指示信号，选择所述第一接口组中与该指示信号对应的输入输出接口上的数据进行输出。
本发明实施例的另一目的在于提供一种具有扫描链的集成电路，所述集成电路包括多个扫描链单元，每个扫描链单元包括第一接口组、第二接口组、扫描链以及扫描数据选择器；
所述第一接口组和第二接口组各自分别包括至少两个可封装为集成电路外部引脚的输入输出接口；
所述第一接口组的各输入输出接口与所述扫描数据选择器的输入端一一对应连接，所述扫描数据选择器的输出端与所述扫描链的扫描数据输入端连接；
所述扫描链的扫描数据输出端与所述第二接口组的各输入输出接口连接；
所述扫描数据选择器用于根据输入到其控制端的封装类型指示信号，选择所述第一接口组中与该指示信号对应的输入输出接口上的数据进行输出。
本发明实施例的另一目的在于提供一种具有扫描链的集成电路，所述集成电路还包括时钟接口组、时钟信号选择器；
所述时钟接口组包括至少两个可封装为集成电路外部引脚的输入输出接口；
所述时钟接口组的各输入输出接口与所述时钟信号选择器的输入端一一对应连接，所述时钟信号选择器的输出端与所述扫描链的扫描时钟输入端连接；
所述时钟信号选择器用于根据输入到其控制端的封装类型指示信号，选择所述时钟接口组中与该指示信号对应的输入输出接口上的时钟信号输出到所述扫描链的扫描时钟输入端。
本发明实施例的另一目的在于提供一种具有扫描链的集成电路，其特征在于，所述集成电路还包括使能接口组以及使能信号选择器；
所述使能接口组各自分别包括至少两个可封装为集成电路外部引脚的输入输出接口；
所述使能接口组的各输入输出接口与所述使能信号选择器的输入端一一对应连接，所述使能信号选择器的输出端与所述扫描链的扫描使能输入端连接；
所述使能信号选择器用于根据输入到其控制端的封装类型指示信号，选择将所述使能接口组中与该指示信号对应的输入输出接口上的使能信号输出到所述扫描链的扫描使能输入端。
本发明实施例的另一目的在于提供一种芯片测试方法，其特征在于，所述芯片包括第一引脚、第二引脚、扫描链、第一接口组、第二接口组以及扫描数据选择器；
所述第一接口组和第二接口组各自分别包括至少两个输入输出接口，第一接口组的其中一个输入输出接口与第一引脚连接，第二接口组的其中一个输入输出接口与第二引脚连接；
所述第一接口组的各输入输出接口与所述扫描数据选择器的输入端一一对应连接，所述扫描数据选择器的输出端与所述扫描链的扫描数据输入端连接，所述扫描链的扫描数据输出端与所述第二接口组的各输入输出接口连接；
所述芯片测试方法包括：
从所述第一引脚输入测试输入数据；
所述扫描数据选择器依据芯片的封装类型信息，选择将所述测试输入数据输入到扫描数据输入端；
所述扫描链对所述测试输入数据进行响应，从扫描数据输出端输出测试输出数据；
从所述第二引脚读取所述测试输出数据。
 有益效果
在本发明实施例中，扫描数据选择器根据输入到其控制端的封装类型指示信号，选择第一接口组中与该指示信号对应的输入输出接口上的数据输出至第二接口组中的各个输入输出接口，从而针对芯片的功能差异较大的各种不同封装类型，可以极大地增加扫描链的数量，从而极大地节约集成电路测试成本，提高集成电路测试效率。
附图说明
图1A是现有技术提供的非扫描寄存器的结构示意图；
图1B是现有技术提供的扫描寄存器的结构示意图；
图1C是现有技术提供的没有插入扫描链的原始设计示意图；
图1D是现有技术提供的插入扫描链的全扫描设计示意图；
图2A、2B、2C是现有技术提供的同一集成电路的三种不同封装类型示意图；
图2D是现有技术提供的用于图2A、2B、2C所示芯片的扫描链的结构示意图；
图3是本发明第一实施例提供的具有扫描链的集成电路的结构框图；
图4是本发明第二实施例提供的具有扫描链的集成电路的结构框图；
图5A、5B是本发明实施例提供的在封装1类型和封装2类型时的具有扫描链的集成电路的结构示意图；
图6是本发明第三实施例提供的具有扫描链的集成电路的结构框图；
图7是本发明第四实施例提供的具有扫描链的集成电路的结构框图；
图8是本发明第五实施例提供的具有扫描链的集成电路的结构框图；
图9是本发明第六实施例提供的具有扫描链的集成电路的结构框图；
图10A、10B是本发明实施例提供的在封装1类型和封装2类型时的具有扫描链的集成电路的结构示意图；
图11是本发明一实施例的芯片测试方法的实现流程图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本发明实施例中，扫描数据选择器根据输入到其控制端的封装类型指示信号，选择第一接口组中与该指示信号对应的输入输出接口上的数据输出至第二接口组中的各个输入输出接口，从而针对芯片的功能差异较大的各种不同封装类型，可以极大地增加扫描链的数量，从而极大地节约集成电路测试成本，提高集成电路测试效率。
图3示出了本发明第一实施例提供的具有扫描链的集成电路的结构，为了便于说明，仅示出了与本发明实施例相关的部分。
该具有扫描链13的集成电路包括第一接口组11、第二接口组14以及扫描数据选择器12。其中扫描链13包括扫描数据输入端、扫描数据输出端、扫描时钟输入端、扫描使能输入端。其中：
第一接口组11和第二接口组14各自分别包括至少两个可封装为集成电路外部引脚的输入输出接口。其中第一接口组11的各输入输出接口与扫描数据选择器12的输入端一一对应连接，扫描数据选择器12的输出端与扫描链13的扫描数据输入端SI连接。扫描链13的扫描数据输出端SO与第二接口组14的各输入输出接口连接。
其中，扫描数据选择器12根据输入到其控制端（图中未示出）的封装类型指示信号，选择第一接口组11中与该指示信号对应的输入输出接口上的数据输出至扫描链13的扫描数据输入端SI。
其中，封装类型指示信号用于指示集成电路的封装类型。
本发明实施例的集成电路可被封装为不同的类型，在每种封装类型下，第一接口组11中至少有一个输入输出接口被封装为外部引脚，第二接口组14中至少有一个输入输出接口被封装为外部引脚。
图4示出了本发明第二实施例提供的具有扫描链的集成电路的结构，为了便于说明，仅示出了与本发明实施例相关的部分。
该集成电路在图3所示的集成电路中增加了时钟接口组15和时钟信号选择器16。
时钟接口组15包括至少两个可封装为集成电路外部引脚的输入输出接口。其中时钟接口组15的各输入输出接口与时钟信号选择器16的输入端一一对应连接，时钟信号选择器16的输出端与扫描链13的扫描时钟输入端CLK连接。
其中，时钟信号选择器16根据输入到其控制端（图中未示出）的封装类型指示信号，选择时钟接口组15中与该指示信号对应的输入输出接口上的时钟信号输出到扫描链13的扫描时钟输入端。
在本发明实施例中，在集成电路的每种封装类型下，时钟接口组15中至少有一个输入输出接口被封装为外部引脚。
更进一步的，本实施例的集成电路中还可以增加使能接口组17和使能信号选择器18。
使能接口组17包括至少两个可封装为集成电路外部引脚的输入输出接口。其中使能接口组17的各输入输出接口与使能信号选择器18的输入端一一对应连接，使能信号选择器18的输出端与扫描链13的扫描使能输入端Scan_enable连接。
其中，使能信号选择器18根据输入到其控制端（图中未示出）的封装类型指示信号，选择使能接口组17中与该指示信号对应的输入输出接口上的使能信号输出到扫描链13的扫描使能输入端。
在本发明实施例中，在集成电路的每种封装类型下，使能接口组17中至少有一个输入输出接口被封装为外部引脚。
以下以一个具体的实例，对本发明实施例提供的具有扫描链的集成电路进行详细的描述。
请参阅图5A，为本发明实施例提供的在封装1类型时的具有扫描链的集成电路的结构，详述如下：
在封装1类型下，第一接口组中的输入输出接口package1_fun1_io1被封装为外部引脚fun1_pin1，第二接口组中的输入输出接口package1_fun1_io2被封装为外部引脚fun1_pin2。则本发明实施例提供的具有扫描链的集成电路的扫描测试的过程如下：
扫描链（scan_chain）的可用引脚为fun1_pin1与fun1_pin2，由于在封装1类型下，第一接口组中的输入输出接口package1_fun1_io1被封装为外部引脚fun1_pin1，因此，扫描数据选择器12在输入到其控制端的封装类型指示信号的控制下选择将第一接口组中的输入输出接口package1_fun1_io1的数据输出至扫描链的扫描数据输入端，从而将从外部引脚fun1_pin1输入的数据作为此封装1类型下扫描链scan_chain的扫描数据输入信号。扫描链scan_chain的输出被传输至第二接口组中的输入输出接口package1_fun1_io2和package2_fun2_io2。由于第二接口组中的输入输出接口package1_fun1_io2在此封装1类型下被封装为外部引脚fun1_pin2，因此，通过该外部引脚fun1_pin2可以将传输至第二接口组中的输入输出接口package1_fun1_io2的数据输出，以使测试人员获得该条扫描链scan_chain的输出信号。
请参阅图5B，为本发明实施例提供的在封装2类型时的具有扫描链的集成电路的结构，详述如下：
在封装2类型下，第一接口组中的输入输出接口package2_fun2_io1被封装为外部引脚fun2_pin1，第二接口组中的输入输出接口package2_fun2_io2被封装为外部引脚fun2_pin2。则本发明实施例提供的具有扫描链的集成电路的扫描测试的过程如下：
扫描链（scan_chain）的可用引脚为fun2_pin1与fun2_pin2，由于在封装2类型下，第一接口组中的输入输出接口package2_fun2_io1被封装为外部引脚fun2_pin1，因此，扫描数据选择器12在输入到其控制端的封装类型指示信号的控制下选择将第一接口组中的输入输出接口package2_fun2_io1的数据输出至扫描链13的扫描数据输入端，从而将从外部引脚fun2_pin1输入的数据作为此封装2类型下扫描链scan_chain的扫描数据输入信号。扫描链scan_chain的输出被传输至第二接口组中的输入输出接口package1_fun1_io2和package2_fun2_io2。由于第二接口组中的输入输出接口package2_fun2_io2在此封装2类型下被封装为外部引脚fun2_pin2，因此，通过该外部引脚fun2_pin2可以将传输至第二接口组中的输入输出接口package2_fun2_io2的数据输出，以使测试人员获得该条扫描链scan_chain的输出信号。图6示出了本发明第三实施例提供的具有扫描链的集成电路的结构，为了便于说明，仅示出了与本发明实施例相关的部分。
该具有扫描链的集成电路包括多个扫描链单元1，每个扫描链单元1包括第一接口组11、第二接口组14、扫描链13以及扫描数据选择器12。其中扫描链13包括扫描数据输入端、扫描数据输出端、扫描时钟输入端和扫描使能输入端。其中：
第一接口组11和第二接口组14各自分别包括至少两个可封装为集成电路外部引脚的输入输出接口。第一接口组11的各输入输出接口与扫描数据选择器12的输入端一一对应连接，扫描数据选择器12的输出端与扫描链13的扫描数据输入端SI连接。扫描链13的扫描数据输出端SO与第二接口组14的各输入输出接口连接。
其中，扫描数据选择器12根据输入到其控制端（图中未示出）的封装类型指示信号，选择第一接口组11中与该指示信号对应的输入输出接口上的数据输出至扫描链13的扫描数据输入端SI。
其中，封装类型指示信号用于指示集成电路的封装类型。
本发明实施例的集成电路可被封装为不同的类型，在每种封装类型下，每个第一接口组11中至少有一个输入输出接口被封装为外部引脚，每个第二接口组14中至少有一个输入输出接口被封装为外部引脚。
在本发明实施例中，各扫描链单元1中第一接口组包括的输入输出接口的数量可以相同，也可以不同，各扫描链单元1中第二接口组包括的输入输出接口的数量可以相同，也可以不同。
图7示出了本发明第四实施例提供的具有扫描链的集成电路的结构，为了便于说明，仅示出了与本发明实施例相关的部分。
该集成电路在图6所示的集成电路中增加了时钟控制单元2，该时钟控制单元2包括时钟接口组15和时钟信号选择器16。
时钟接口组15包括至少两个可封装为集成电路外部引脚的输入输出接口。其中时钟接口组15的各输入输出接口与时钟信号选择器16的输入端一一对应连接，时钟信号选择器16的输出端与扫描链13的扫描时钟输入端CLK连接。
其中，时钟信号选择器16根据输入到其控制端（图中未示出）的封装类型指示信号，选择时钟接口组15中与该指示信号对应的输入输出接口上的时钟信号输出到扫描链13的扫描时钟输入端。
更进一步的，在图7所示的集成电路中还可以增加使能控制单元3，该使能控制单元3包括使能接口组17和使能信号选择器18。
使能接口组17包括至少两个可封装为集成电路外部引脚的输入输出接口。其中使能接口组17的各输入输出接口与使能信号选择器18的输入端一一对应连接，使能信号选择器18的输出端与扫描链13的扫描使能输入端Scan_enable连接。
其中，使能信号选择器18根据输入到其控制端（图中未示出）的封装类型指示信号，选择使能接口组17中与该指示信号对应的输入输出接口上的使能信号输出到扫描链13的扫描使能输入端。
图8示出了本发明第五实施例提供的具有扫描链的集成电路的结构，为了便于说明，仅示出了与本发明实施例相关的部分。
该具有扫描链的集成电路还包括时钟接口组15和时钟信号选择器16。其中扫描链13包括扫描时钟输入端、扫描数据输入端、扫描数据输出端、扫描使能输入端。其中：
时钟接口组15包括至少两个可封装为集成电路外部引脚的输入输出接口。其中时钟接口组15的各输入输出接口与时钟信号选择器16的输入端一一对应连接，时钟信号选择器16的输出端与扫描链13的扫描时钟输入端CLK连接。
其中，时钟信号选择器16根据输入到其控制端（图中未示出）的封装类型指示信号，选择时钟接口组15中与该指示信号对应的输入输出接口上的时钟信号输出到扫描链13的扫描时钟输入端。
本发明实施例的集成电路可被封装为不同的类型，在每种封装类型下，时钟接口组15中至少有一个输入输出接口被封装为外部引脚。
在本发明另一实施例中，该集成电路在图8所示的集成电路中还增加了使能接口组17和使能信号选择器18。该扫描链13还包括扫描使能输入端、扫描数据输入端、扫描数据输出端、扫描时钟输入端。其中：
使能接口组17包括至少两个可封装为集成电路外部引脚的输入输出接口。其中使能接口组17的各输入输出接口与使能信号选择器18的输入端一一对应连接，使能信号选择器18的输出端与扫描链13的扫描使能输入端连接。
其中，使能信号选择器18根据输入到其控制端（图中未示出）的封装类型指示信号，选择使能接口组17中与该指示信号对应的输入输出接口上的使能信号输出到扫描链13的扫描使能输入端。
在本发明实施例中，在集成电路的每种封装类型下，使能接口组17中至少有一个输入输出接口被封装为外部引脚。
图9示出了本发明第六实施例提供的具有扫描链的集成电路的结构，为了便于说明，仅示出了与本发明实施例相关的部分。
该具有扫描链的集成电路还包括使能接口组17和使能信号选择器18。其中扫描链13包括扫描使能输入端、扫描数据输入端、扫描数据输出端、扫描时钟输入端。其中：
使能接口组17包括至少两个可封装为集成电路外部引脚的输入输出接口。其中使能接口组17的各输入输出接口与使能信号选择器18的输入端一一对应连接，使能信号选择器18的输出端与扫描链13的扫描使能输入端Scan_enable连接。
其中，使能信号选择器18根据输入到其控制端（图中未示出）的封装类型指示信号，选择使能接口组17中与该指示信号对应的输入输出接口上的使能信号输出到扫描链13的扫描使能输入端。
在本发明实施例中，在集成电路的每种封装类型下，使能接口组17中至少有一个输入输出接口被封装为外部引脚。
请参阅图10A和图10B，为本发明实施例提供的在封装1类型和封装2类型时的具有扫描链的集成电路的结构示意图。
图11示出了本发明一实施例提供的芯片测试方法的实现流程，该芯片包括第一引脚、第二引脚、扫描链、第一接口组、第二接口组以及扫描数据选择器。其中：
第一接口组和第二接口组各自分别包括至少两个输入输出接口，第一接口组的其中一个输入输出接口与第一引脚连接，第二接口组的其中一个输入输出接口与第二引脚连接。第一接口组的各输入输出接口与扫描数据选择器的输入端一一对应连接，扫描数据选择器的输出端与扫描链的扫描数据输入端连接，扫描链的扫描数据输出端与第二接口组的各输入输出接口连接。
其中，芯片测试方法的流程详述如下：
在步骤S101中，从第一引脚输入测试输入数据；
在步骤S102中，扫描数据选择器依据芯片的封装类型信息，选择第一接口组中的对应输入输出接口，将测试输入数据输入到扫描数据输入端；
在步骤S103中，扫描链对测试输入数据进行响应，从扫描数据输出端输出测试输出数据至第二接口组中的各输入输出接口；
在步骤S104中，从第二引脚读取测试输出数据。
本发明实施例提供的具有扫描链的集成电路特别适用于多种封装类型的单核心芯片，特别是当单核心芯片在不同封装类型下的封装功能差异较大时，可以极大地增加扫描链的数量，从而减少每条扫描链的寄存器数量，极大地节约芯片测试成本和时间，提高芯片测试效率。
在本发明实施例中，扫描数据选择器根据输入到其控制端的封装类型指示信号，选择第一接口组中与该指示信号对应的输入输出接口上的数据输出至第二接口组中的各个输入输出接口，从而在集成电路的不同封装类型下都可以使用相应封装的输入输出接口作为扫描链的可用引脚，从而可以极大地增加集成电路中扫描链的条数，减少单条扫描链的寄存器数目，从而极大地降低集成电路的测试成本，提高集成电路的测试效率。另外还可以对集成电路的不同封装类型下的扫描链的扫描时钟信号和扫描使能信号进行灵活的控制。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种具有扫描链的集成电路，其特征在于，所述集成电路还包括第一接口组、第二接口组以及扫描数据选择器；
    所述第一接口组和第二接口组各自分别包括至少两个可封装为集成电路外部引脚的输入输出接口；
    所述第一接口组的各输入输出接口与所述扫描数据选择器的输入端一一对应连接，所述扫描数据选择器的输出端与所述扫描链的扫描数据输入端连接；
    所述扫描链的扫描数据输出端与所述第二接口组的各输入输出接口连接；
    所述扫描数据选择器用于根据输入到其控制端的封装类型指示信号，选择所述第一接口组中与该指示信号对应的输入输出接口上的数据输出至所述扫描数据输入端。
  2. 如权利要求1所述的集成电路，其特征在于，所述集成电路还包括时钟接口组和时钟信号选择器；
    所述时钟接口组包括至少两个可封装为集成电路外部引脚的输入输出接口；
    所述时钟接口组的各输入输出接口与所述时钟信号选择器的输入端一一对应连接，所述时钟信号选择器的输出端与所述扫描链的扫描时钟输入端连接；
    所述时钟信号选择器用于根据输入到其控制端的封装类型指示信号，选择所述时钟接口组中与该指示信号对应的输入输出接口上的时钟信号输出到所述扫描链的扫描时钟输入端。
  3. 如权利要求1或2所述的集成电路，其特征在于，所述集成电路还包括使能接口组、使能信号选择器；
    所述使能接口组包括至少两个可封装为集成电路外部引脚的输入输出接口；
    所述使能接口组的各输入输出接口与所述使能信号选择器的输入端一一对应连接，所述使能信号选择器的输出端与所述扫描链的扫描使能输入端连接；
    所述使能信号选择器用于根据输入到其控制端的封装类型指示信号，选择所述使能接口组中与该指示信号对应的输入输出接口上的使能信号输出到所述扫描链的扫描使能输入端。
  4. 一种具有扫描链的集成电路，其特征在于，所述集成电路包括多个扫描链单元，每个扫描链单元包括第一接口组、第二接口组、扫描链以及扫描数据选择器；
    所述第一接口组和第二接口组各自分别包括至少两个可封装为集成电路外部引脚的输入输出接口；
    所述第一接口组的各输入输出接口与所述扫描数据选择器的输入端一一对应连接，所述扫描数据选择器的输出端与所述扫描链的扫描数据输入端连接；
    所述扫描链的扫描数据输出端与所述第二接口组的各输入输出接口连接；
    所述扫描数据选择器用于根据输入到其控制端的封装类型指示信号，选择所述第一接口组中与该指示信号对应的输入输出接口上的数据进行输出。
  5. 如权利要求4所述的集成电路，其特征在于，所述集成电路还包括时钟控制单元，所述时钟控制单元包括时钟接口组和时钟信号选择器；
    所述时钟接口组包括至少两个可封装为集成电路外部引脚的输入输出接口；
    所述时钟接口组的各输入输出接口与所述时钟信号选择器的输入端一一对应连接，所述时钟信号选择器的输出端与所述扫描链的扫描时钟输入端连接；
    所述时钟信号选择器用于根据输入到其控制端的封装类型指示信号，选择所述时钟接口组中与该指示信号对应的输入输出接口上的时钟信号输出到所述扫描链的扫描时钟输入端。
  6. 如权利要求4或5所述的集成电路，其特征在于，所述集成电路还包括使能控制单元，所述使能控制单元包括使能接口组、使能信号选择器；
    所述使能接口组包括至少两个可封装为集成电路外部引脚的输入输出接口；
    所述使能接口组的各输入输出接口与所述使能信号选择器的输入端一一对应连接，所述使能信号选择器的输出端与所述扫描链的扫描使能输入端连接；
    所述使能信号选择器用于根据输入到其控制端的封装类型指示信号，选择所述使能接口组中与该指示信号对应的输入输出接口上的使能信号输出到所述扫描链的扫描使能输入端。
  7. 如权利要求4或5所述的集成电路，其特征在于，各扫描链单元中第一接口组包括的输入输出接口的数量相同或者不同，各扫描链单元中第二接口组包括的输入输出接口的数量相同或者不同。
  8. 一种具有扫描链的集成电路，其特征在于，所述集成电路还包括时钟接口组、时钟信号选择器；
    所述时钟接口组包括至少两个可封装为集成电路外部引脚的输入输出接口；
    所述时钟接口组的各输入输出接口与所述时钟信号选择器的输入端一一对应连接，所述时钟信号选择器的输出端与所述扫描链的扫描时钟输入端连接；
    所述时钟信号选择器用于根据输入到其控制端的封装类型指示信号，选择所述时钟接口组中与该指示信号对应的输入输出接口上的时钟信号输出到所述扫描链的扫描时钟输入端。
  9. 一种具有扫描链的集成电路，其特征在于，所述集成电路还包括使能接口组以及使能信号选择器；
    所述使能接口组包括至少两个可封装为集成电路外部引脚的输入输出接口；
    所述使能接口组的各输入输出接口与所述使能信号选择器的输入端一一对应连接，所述使能信号选择器的输出端与所述扫描链的扫描使能输入端连接；
    所述使能信号选择器用于根据输入到其控制端的封装类型指示信号，选择将所述使能接口组中与该指示信号对应的输入输出接口上的使能信号输出到所述扫描链的扫描使能输入端。
  10. 一种芯片测试方法，其特征在于，所述芯片包括第一引脚、第二引脚、扫描链、第一接口组、第二接口组以及扫描数据选择器；
    所述第一接口组和第二接口组各自分别包括至少两个输入输出接口，第一接口组的其中一个输入输出接口与第一引脚连接，第二接口组的其中一个输入输出接口与第二引脚连接；
    所述第一接口组的各输入输出接口与所述扫描数据选择器的输入端一一对应连接，所述扫描数据选择器的输出端与所述扫描链的扫描数据输入端连接，所述扫描链的扫描数据输出端与所述第二接口组的各输入输出接口连接；
    所述芯片测试方法包括：
    从所述第一引脚输入测试输入数据；
    所述扫描数据选择器依据芯片的封装类型信息，选择将所述测试输入数据输入到扫描数据输入端；
    所述扫描链对所述测试输入数据进行响应，从扫描数据输出端输出测试输出数据；
    从所述第二引脚读取所述测试输出数据
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