Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10N50/00—Galvanomagnetic devices
  • H10N50/10—Magnetoresistive devices
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R33/00—Arrangements or instruments for measuring magnetic variables
  • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
  • G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
  • G01R33/09—Magnetoresistive devices
  • G01R33/098—Magnetoresistive devices comprising tunnel junctions, e.g. tunnel magnetoresistance sensors
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y25/00—Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R33/00—Arrangements or instruments for measuring magnetic variables
  • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
  • G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
  • G01R33/09—Magnetoresistive devices
  • G01R33/093—Magnetoresistive devices using multilayer structures, e.g. giant magnetoresistance sensors
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
  • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F10/00—Thin magnetic films, e.g. of one-domain structure
  • H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F10/00—Thin magnetic films, e.g. of one-domain structure
  • H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
  • H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
  • H01F10/3254—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F10/00—Thin magnetic films, e.g. of one-domain structure
  • H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
  • H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
  • H01F10/3268—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
  • H01F10/3272—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
  • H01F10/00—Thin magnetic films, e.g. of one-domain structure
  • H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
  • H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
  • H01F10/3286—Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T428/00—Stock material or miscellaneous articles
  • Y10T428/11—Magnetic recording head
  • Y10T428/1107—Magnetoresistive
  • Y10T428/1114—Magnetoresistive having tunnel junction effect
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T428/00—Stock material or miscellaneous articles
  • Y10T428/11—Magnetic recording head
  • Y10T428/1107—Magnetoresistive
  • Y10T428/1143—Magnetoresistive with defined structural feature

Definitions

• Flash memory NAND or NOR
• traditional rotating storage e.g., disc drives
• MRAM Resistive sense memories
• the present disclosure relates to magnetic stacks (e.g., memory cells such as magnetic tunnel junction cells, and read sensors).
• the structures have a pinned reference layer configured for reduced inter layer coupling between the reference layer and the free layer. With these structures, high tunneling magnetoresistance (TMR) can be achieved.
• TMR tunneling magnetoresistance
• this disclosure describes a magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween, each of the free layer, reference layer and barrier layer having a center
• the stack includes an annular antiierromagnetic pinning layer having a center, with the center of the pinning layer aligned with the center of each of the free layer, reference layer and barrier layer, the pinning layer electrically isolated from the free layer and in physical contact with the reference layer,
• this disclosure describes a magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween.
• the stack includes an anti ferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer.
• Each of the free layer, reference layer, barrier layer and pinning layer have a center and an outer diameter, with the reference layer having a larger outer diameter than the free layer.
• this disclosure describes a magnetic stack having a free layer having a switchable magnetization orientation, a synthetic antiferromagnetic (SAF) coupled reference layer having a pinned magnetization orientation, and a barrier layer therebetween.
• the SAF reference layer has a first ferromagnetic sublayer and a second ferromagnetic sublayer separated by a metallic spacer, with the first sublayer different than the second sublayer,
• FIG. IA is a cross-sectional schematic diagram of an illustrative magnetic stack with in-plane magnetization orientation
• FIG. I B is a cross-sectional schematic diagram of an illustrative perpendicular anisotropy magnetic stack with out-of-piane magnetization orientation
• FIG. 2 is a schematic diagram of an illustrative memory unit including a memory cell and a scmiconduc tor transistor;
• FIG, 3 is a cross-sectional schematic diagram of an embodiment of a magnetic cell
• FIGS. 4A-4J illustrate a stepwise method for forming the magnetic cell of FIG. 3;
• FIG. 5 is a cross-sectional schematic diagram of an embodiment of a magnetic cell
• [15 J FIG. 6 is a cross-sectional schematic diagram of an embodiment of a magnetic cell
• FIG. 7 is a cross-sectional schematic diagram of an embodiment of a magnetic cell
• [17 [ FIGS. 8A-8H illustrate a stepwise method for forming the magnetic cell of FIG. 7;
• FIG. 9 is a cross-sectional schematic diagram of an embodiment of a magnetic ceil.
• This disclosure is directed to magnetic stacks (e.g., spin torque memory (STIlAM) cells, REAM cells, and other resistive sense memory cells (RSM cells) and read sensors).
• the structures have a pinned ferromagnetic reference layer, either a single layer or an SAF trilayer, that is larger than and extends past the ferromagnetic free layer. With such a structure, the interlayer coupling between the pinned reference layer and the free layer can be reduced, compared to a cell structure that has the same size for the reference layer and the free layer.
• TMR tunneling magnetoresistance
• the magnetic cells include an annular antiferromagnetic pinning layer that is isolated from the free layer but in physical contact with the reference layer. In other embodiments, the magnetic cells include an asymmetric SAF tri layer.
• FIG. IA is a cross-sectional schematic diagram of a magnetic cell 1OA that includes a soft ferromagnetic free layer 12A and a ferromagnetic reference (i.e., pinned) layer 14 A.
• Ferromagnetic free layer 12A and ferromagnetic reference layer 14A are separated by an oxide barrier layer 13 A or non-magnetic tunnel barrier. Note that other layers, such as seed or capping layers, are no! depicted for clarity but could be included as technical need arises.
• IJ Reference layer 14A is larger in size than free layer 12 A and extends past the edges of
• each layer e.g.. free layer 12A, reference layer 14A. etc.
• each layer has a center point and an outer diameter.
• reference layer 14A has a diameter greater than the diameter of free layer 12A, so that reference layer 14A extends past free layer 12A in all directions.
• Ferromagnetic layers 12 A, 14A may be made of any useful ferromagnetic (FM) material such as, for example, Fe, Co or TN ⁇ and alloys thereof, such as NiFc and CoFc, Ternary alloys, such as, CoFeB, may be particularly useful because of their lower moment and high polarization ratio, which are desirable for the spin-current switch.
• FM ferromagnetic
• Either or both of free layer 12A and reference layer 14A may be either a single ferromagnetic layer or a synthetic antifcrrornagnelic (SAF) coupled structure, i.e., two ferromagnetic sublayers separated by a metallic spacer, such as Ru or Cu, with the magnetization orientations of the sublayers in opposite directions to provide a net magnetization.
• SAF synthetic antifcrrornagnelic
• Barrier layer 13A may be made of an electrically insulating material such as, for example an oxide material (e.g., ALO 3 . TiO x or MgO). Other suitable materials may also be used. Barrier layer 13A could optionally be patterned with free layer 12A or with reference layer 14A, depending on process feasibility and device reliability.
• an oxide material e.g., ALO 3 . TiO x or MgO.
• Other suitable materials may also be used.
• Barrier layer 13A could optionally be patterned with free layer 12A or with reference layer 14A, depending on process feasibility and device reliability.
• Electrodes 18 A, 19A electrically connect ferromagnetic layers 12 A, 14A to a control circuit providing read and write currents through layers 12 A, 14A.
• isolation layer 16A Radially encircling at least free layer 12A, is an isolation layer 16A, which is electrically insulating.
• isolation layer 16A encircles free layer 12A, barrier layer 13A, and top electrode 19A.
• Isolation layer 16A has a thickness of about 2-30 run and is formed of electrically insulating materials such as oxide(s) and nitride(s). Examples of suitable materials for isolation layer 16A include Si 3 N 4 , SiO?., SiO x Ny, SiOCN, Ta 2 O 5 , Al 2 O 3 , MgO, and other low K dielectrics. In other embodiments, isolation layer 16A encircles free layer 12 A and top electrode 19A.
• the resistance across magnetic cell 1 OA is determined by the relative orientation of the magnetization vectors or magnetization orientations of ferromagnetic layers 12A, 14A.
• the magnetization direction of ferromagnetic reference layer 14A is pinned in a predetermined direction while the magnetization direction of ferromagnetic free layer 12A is free to rotate under the influence of spin torque.
• Pinning of ferromagnetic reference layer 14A may be achieved through, e.g., the use of exchange bias with an antiferromagnetically ordered material such as PtMn, IrMn, and others.
• Magnetic memory cell 1OA is in the low resistance state when the magnetization orientation of free layer 12A is in the same direction (parallel) as the magnetization orientation of reference layer 14 A. Conversely, a magnetic memory cell is in the high resistance state when the magnetization orientation of free layer 12A is in the opposite direction (anti-parallel) of the magnetization orientation of reference layer 14A. Switching the resistance state and hence the data state of magnetic cell 1OA via spin-transfer occurs when a current, passing through a magnetic layer of magnetic cell 1OA, becomes spin polarized and imparts a spin torque on free layer 12 A, When a sufficient spin torque is applied to free layer 12A. the magnetization orientation of free layer 12A can be switched between two opposite directions and accordingly, magnetic cell 1OA can be switched between the low resistance state and the high resistance state,
• FIG. IB illustrates an alternate embodiment of a magnetic memory cell that has the magnetization orientations of the free layer and the pinned layer perpendicular to the plane of the layers, or "out-of-plane' ⁇
• magnetic cell 1OB of FIG, IB has soft ferromagnetic free layer 12B and a ferromagnetic reference (i.e., pinned) layer 14B separated by an oxide bsarrier layer 13B or non-magnetic tunnel barrier.
• a first or bottom electrode 18B is in electrical contact with ferromagnetic reference layer 14B and a second or top electrode 19B is in electrical contact with ferromagnetic free layer 12B.
• Electrodes 18B, 19B electrically connect ferromagnetic layers 1213, 14B to a control circuit providing read and write currents through layers 12B, 14B.
• An electrically insulating radial isolation layer 16B encircles at least free layer 12A and top electrode 19B.
• the various elements of cell K)B are similar to the elements of cell 1OA, described above, except that the magnetization orientations of layers 12B, 14B are oriented perpendicular to the layer extension rather than in the layer plane,
• J Free layer 12B and reference layer 14B each have a magnetization orientation associated
• magnetic cell 1OB is in the low resistance state where the magnetization orientation of free layer 12B is in the same direction (parallel) as the magnetization orientation of reference layer 1413. In other embodiments, magnetic cell 1OB is in the high resistance state where the magnetization orientation of free layer 12B is in the opposite direction (anti-parallel) as the magnetization orientation of reference layer 14B.
• magnetic cell 1OB via spin-transfer occurs when a current, passing through a magnetic layer of magnetic cell 1OB, becomes spin polarized and imparts a spin torque on free layer 12B,
• a sufficient spin torque is applied to free layer 12B, the magnetization orientation of free layer 12B can be switched between two opposite directions and accordingly, magnetic cell 1OB can be switched between the low resistance state and the high resistance state.
• Both memory cells 1OA, 1OB arc illustrated with undefined magnetization orientations for free layer 12 A, 12B.
• a magnetic memory cell is in the low resistance state when the magnetization orientation of free layer 12A, 12B is in the same direction as the
• a magnetic memory cell is in the high resistance state when the magnetization orientation of free layer 12A, 12B is in the opposite direction of the magnetization orientation of reference layer 14A, 14B.
• the low resistance state is the "0" data state and the high resistance state is the "'1 '' data state, whereas in other embodiments, the low resistance state is u l" arid the high resistance state is 'O".
• the magnet stack of memory cells 1 OA, 1 OB of FIGS. IA and I B can also be used as a magnetic read sensor in a hard disc drive with some modifications.
• free layer 12 A, 12B is influenced by a stored magnetic state on an adjacent recording media, and when a current is passed through the stack, the magnetization orientation in the media can be detected,
• FIG. 2 is a schematic diagram of an illustrative memory unit 20 including a memory element 21 electrically coupled to a semiconductor transistor 22 via an electrically conducting element.
• Memory element 21 may be any of the memory cells described herein.
• Transistor 22 includes a semiconductor substrate 25 having doped regions (e.g., illustrated as n-doped regions) and a channel region (e.g., illustrated as a p-doped channel region) between the doped regions.
• Transistor 22 includes a gate 26 that is electrically coupled to a word line WL to allow selection and current to flow from a source line SL to memory element 21 and bit line BL.
• An array of programmable metallization memory units 20 can be formed on a semiconductor substrate with word lines and bit lines utilizing semiconductor fabrication techniques. Both memory cell 1 OA of FIG. IA and memory cell 1OB of FlG. IB are illustrated connected to a bit line BL via their top electrode 19 A, 19B. FlG.
• FIG 3 illustrates a first embodiment of a memory cell having a pinned SAF trilayer reference layer that is larger than arid extends past the ferromagnetic free layer
• This embodiment includes an anliferromagnetic pinning layer that is isolated from the free layer but in physical contact with the reference layer.
• the antiferromagnetic pinning layer is annular in some embodiments.
• memory cell 30 has a soft ferromagnetic free layer 32 and a SAF trilayer reference (i.e., pinned) layer 34 separated by a barrier layer 33.
• barrier layer 33 is an oxide barrier layer, in other embodiments it can be a non-magnetic tunnel barrier.
• trilayer 34 is composed of two layers of ferromagnetic material (e.g., CoFeB) separated by a layer of Ru, and barrier layer 33 is composed of MgO.
• a first or bottom electrode 38 is in electrical contact with trilayer 34 and a second or top electrode 39 is in electrical contact with ferromagnetic free layer 32.
• An electrically insulating isolation layer 36 encircles free layer 32 and top electrode 39.
• the various elements of cell 30 are similar to the element of cells 1OA, 1OB described above, except as noted.
• Memory cell 30 also includes a hard mask 37 positioned above top electrode 39.
• hard mask 37 is electrically conducting and is integral with or replaces top electrode 39.
• Memory cell 30 also includes an antiferromagnetic pinning layer 35 radially encircling the stack of barrier layer 33, free layer 32 and top electrode 39 and electrically insulated therefrom by isolation layer 36. In the illustrated embodiment, a portion of isolation layer 36 is exposed and not encircled by pinning layer 35.
• Free layer 32 is physically and electrically isolated from pinning layer 35, which is in physical contact with trilayer 34 at its extended area (i.e., proximate the outer diameter of trilayer 34) and provides pinning for SAF trilayer 34.
• SAF trilayer 34 is larger than and extends past free layer 32; that is, trilayer 34 has a larger outer diameter than free layer 32. Trilayer 34 also is larger than and extends past barrier layer 33, which in turn is larger than and extends past free layer 32.
• Trilayer 34, barrier 33 and free layer 32 are stacked with their centers aligned.
• FIGS 4A-4J The process flow to make this memory cell stack structure is shown in FIGS 4A-4J.
• a stack of appropriate materials forming bottom electrode 48, SAF trilayer 44, barrier layer 43, free layer 42, and top electrode 49 is deposited.
• high-temp ⁇ rature thermal annealing is done Io induce the epitaxial formation in barrier layer 43 (e.g., MgO barrier layer) and crystallization of ferromagnetic free layer 42 and SAF trilayer 44.
• a hard mask 47 is deposited on to top electrode 49 and then patterned. Subsequently, via milling and etching, free layer 42 is patterned and the etching is stopped at barrier layer 43.
• a protective layer 46 e.g., silicon nitride, is deposited in FIG. 4C to cover the stack of FIG. 4B. After milling and etching the structure of FIG. 4C, the extended area of SAF trilayer 44 is exposed in FlG. 4D while barrier layer 43 remains covered by protective isolation layer 46.
• an antiferromagnetic pinning layer 45 is deposited over the structure of FIG.
• a very thin ferromagnetic layer may be deposited over the structure of FlG. 4D before deposition of antiferromagnetic pinning layer 45 to increase the pinning effect.
• milling is performed to trim antiferromagnetic pinning layer 45 to achieve physical, electrical and magnetic separation between hard mask 47 and antiferromagnetic pinning layer 45.
• pinning layer 45 is an insulator (e.g., NiO)
• this separation is not necessary.
• many pinning materials are metallic and are alloys of Mn, thus the separation is desired.
• FIG. 4G the entire stack is annealing at elevated temperature in the presence of a strong
• the memory cell is finalized by deposition of dielectric material 40 in FIG. 4H to encase the structure.
• This dielectric material 40 is polished in FIG. 41 to provide a planar surface, and a bit line BL is deposited and patterned on top electrode 49 and hard mask 47 in FlG. 4J.
• FlG. 5 illustrates another embodiment of a memory cell having a pinned reference layer that is larger than and extends past the ferromagnetic ⁇ JQQ layer and having an annular pinning layer,
• memory cell 50 has a soft ferromagnetic free layer 52 and a single layer reference (i.e., pinned) layer 54 separated by an oxide barrier layer 53 or non-magnetic tunnel barrier.
• a first or bottom electrode 58 is in electrical contact with reference layer 54 and a second or top electrode 59 is in electrical contact with ferromagnetic free layer 52.
• a hard mask 57 is positioned above top electrode 59.
• An electrically insulating radial isolation layer 56 encircles free layer 52, hard mask 57 and top electrode 59.
• An antiferromagnetic pinning layer 55 radially encircles at least a portion of isolation layer 56 and the stack of barrier layer 53, free layer 52, top electrode 59 and hard mask 57.
• the various elements of cell 50 are similar to the clement of cells 1OA, 1OB, 30 described above, except as noted.
• reference layer 54 is larger than and extends past barrier layer 53, which in turn is larger than and extends past free layer 52.
• Reference layer 54, barrier 53 and free layer 52 are stacked with their centers aligned.
• FIG. 6 illustrates another embodiment of a memory cell having a pinned reference layer that is larger than and extends past the ferromagnetic free layer and that has an asymmetric SAF trilayer instead of a pinning layer.
• memory cell 60 has a soft ferromagnetic free layer 62 and an SAF trilayer reference (i.e., pinned) layer 64 separated by an oxide barrier layer 63 or non-magnetic tunnel barrier.
• a first or bottom electrode 68 is in electrical contact with trilayer 64 and a second or top electrode 69 is in electrical contact with ferromagnetic free layer 62.
• a hard mask 67 is positioned above top electrode 69.
• An electrically insulating radial isolation layer 66 encircles free layer 62, hard mask 67 and top electrode 69.
• the various elements of cell 60 are similar to the element of cells K)A, 1OB, 30, 50 described above, except as noted.
• memory cell 60 has no
• trilayer 64 (composed of a first ferromagnetic layer 64A, a metallic spacer 64B, and a second ferromagnetic layer 64C) is asymmetric in either physical thickness or coercivity between its ferromagnetic layers. That is, ferromagnetic layers 64A and 64C either have a different physical thickness or have a different coercivity. In FIG. 6, layer 64A is illustrated physically thicker than layer 64C. The magnetization configuration and orientation of tri layer 64 are defined after magnetic field setting. With no anti ferromagnetic pinning layer in cell 60, trilaycr 64 is designed in shape to induce shape anisotropy against thermal activation.
• FIG. 7 illustrates another embodiment of a memory cell having a pinned reference layer that is larger than and extends past the ferromagnetic free layer and having an annular pinning layer
• memory cell 70 has a soft ferromagnetic free layer 72 and an SAF trilayer reference (i.e., pinned) layer 74 separated by an oxide barrier layer 73 or non-magnetic tunnel barrier.
• a first or bottom electrode 78 is in electrical contact with lrilayer 74 and a second or top electrode 79 is in electrical contact with ferromagnetic free layer 72.
• a hard mask 77 is positioned above top electrode 79.
• An electrically insulating radial isolation layer 76 encircles free layer 72, hard mask 77 and top electrode 79.
• the various elements of cell 70 are similar to the clement of cells 1OA, 1OB, 30, 50, 60 described above, except as noted.
• Memory cell 70 includes a pinning layer 75 positioned below the stack of free layer 72, barrier layer 73, and trilayer 74,
• pinning layer 75 is an annular ring at the outer periphery of bottom electrode 78, in physical contact with and exchange coupled with trilayer 74.
• pinning layer 75 is centered around the stack of free layer 72, barrier layer 73, and trilayer 74 and does not vertically overlap or intersect with the stack.
• FIGS 8A-8H The process flow to make memory cell 70 is shown in FIGS 8A-8H.
• a metal layer 80 deposited which will form the eventual bottom electrode.
• Metal layer 80 is masked and patterned (e.g., milled) to form bottom electrode 88 of FIG. 8B.
• FIG. 8C In FIG. 8C,
• antiferromagnetic material is deposited in a ring around bottom electrode 88 and then polished to form pinning layer 85.
• An SAF trilayer 84, a barrier layer 83, a free layer 82 and top electrode 89 are sequentially formed in FIG. 8D over bottom electrode 88 and pinning layer 85.
• the various layers of pinning layer 85/bottora electrode 88, SAF trilayer 84, barrier layer 83, free layer 82 and top electrode 89 in the stack have the same diameter.
• FIG. 8E illustrates the various layers of pinning layer 85/bottora electrode 88, SAF trilayer 84, barrier layer 83, free layer 82 and top electrode 89 in the stack have the same diameter.
• I" _ free layer 82 and top electrode 89 are masked with hard mask 87 and patterned, to have a reduced size in relation to SAF trilayer 84 and barrier layer 83,
• Isolation material 86 is deposited in FIG. 8F to cover and encase the structure of FIG. 8E.
• This isolation materia! 86 is optionally milled and then covered with a dielectric material, which is polished in FIG. 8G to provide a planar surface of hard mask 87 and isolation material 86.
• a bit line BL is deposited and patterned on top electrode 89 and hard mask 87 in FIG. 8H.
• Memory cell 90 of FlG. 9 has a soft ferromagnetic free layer 92 and a single layer reference (i.e., pinned) layer 94 separated by an oxide barrier layer 93 or non-magnetic tunnel barrier.
• a first or bottom electrode 98 is in electrical contact with layer 94 and a second or top electrode 99 is in electrical contact with free layer 92.
• a hard mask 97 is positioned above top electrode 99.
• An electrically insulating radial isolation layer 96 encircles free layer 92, hard mask 97 and top electrode 99.
• An annular pinning layer 95 is positioned below the stack of free layer 92, barrier layer 93, and layer 94.
• the various elements of cell 90 are similar to the element of cells 1OA, 1OB, 30, 50, 60, 70 described above, except as noted.
• the structures of this disclosure may be made by thin film techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Material removal may be by etching, including milling, ion beam milling, wet etching, and the like.
• CVD chemical vapor deposition
• PVD physical vapor deposition
• ALD atomic layer deposition
• Material removal may be by etching, including milling, ion beam milling, wet etching, and the like.

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