WO2010150624A1 - 等化装置、等化方法及びプログラム - Google Patents
等化装置、等化方法及びプログラム Download PDFInfo
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- WO2010150624A1 WO2010150624A1 PCT/JP2010/059257 JP2010059257W WO2010150624A1 WO 2010150624 A1 WO2010150624 A1 WO 2010150624A1 JP 2010059257 W JP2010059257 W JP 2010059257W WO 2010150624 A1 WO2010150624 A1 WO 2010150624A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
- H04L25/03885—Line equalisers; line build-out devices adaptive
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/04—Control of transmission; Equalising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
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- the present invention relates to an equalization apparatus, an equalization method, and a program for equalizing signal waveform deterioration.
- Intersymbol interference refers to interference between adjacent signals indicating bit values of 0 or 1 during transmission. This intersymbol interference degrades the signal waveform, making it difficult to determine the bit value from the input signal input to the signal receiving side.
- Waveform equalization is a technique for intentionally changing part of a signal waveform in accordance with signal waveform degradation due to intersymbol interference.
- FIG. 1 is a diagram illustrating an example of an input signal deteriorated due to intersymbol interference.
- the deterioration of the waveform of the input signal includes a pre-cursor component before the main tap and a post-cursor component after the main tap.
- Non-Patent Document 1 discloses a decision feedback equalizer that can remove the influence of the post-cursor component.
- decision feedback equalization the bit value indicated by the input signal is determined from the waveform of the input signal. Then, based on the determination result, the influence of the waveform deterioration of the already received input signal is removed from the input signal input to the receiving side next time.
- Non-Patent Document 2 discloses a technique that combines waveform equalization on the transmission side and waveform equalization on the reception side.
- the technology disclosed in Non-Patent Document 2 eliminates both the effects of post-cursor components and pre-cursor components by combining waveform equalization on the transmission side and decision feedback equalization on the reception side. can do. As a result, signal degradation due to intersymbol interference can be completely eliminated.
- Non-Patent Document 2 When removing the influence of the pre-cursor component on the transmission side as in the technique disclosed in Non-Patent Document 2, it is necessary to feed back the coefficient calculated from the waveform of the input signal from the reception side to the transmission side. This is because the influence of the pre-cursor component is removed on the transmission side based on the waveform of the input signal.
- the present invention provides an equalization apparatus, an equalization method, and a program capable of removing the influence of a pre-cursor component from an input signal input to a signal reception side while avoiding an increase in circuit scale and power consumption.
- the purpose is to provide.
- an equalizer of the present invention is an equalizer that receives a signal transmitted from a signal transmission side as an input signal and equalizes deterioration of the waveform of the received input signal. , From the waveform of the input signal, the bit value indicated by the input signal is determined according to the clock, and the result of the determination is that the determined two-bit value is the same from the determined signal composed of a plurality of bits, A 2-bit transition signal whose bit values before and after the two consecutive bit values are different from the two consecutive bit values is detected, and the phase of the clock is synchronized with the phase of the detected two-bit transition signal.
- an equalization method of the present invention is an equalization apparatus that receives a signal transmitted from a signal transmission side as an input signal and equalizes deterioration of the waveform of the received input signal.
- An equalization method A determination process for determining a bit value indicated by the input signal according to a clock from the waveform of the input signal; As a result of the determination, two consecutive bit values are the same from the determined signal composed of a plurality of bits, and the bit values before and after the two consecutive bit values are the two consecutive bit values. And a synchronization process for detecting a different 2-bit transition signal and synchronizing the phase of the clock with the detected phase of the 2-bit transition signal.
- the program of the present invention receives, as an input signal, a signal transmitted from the signal transmission side, and an equalizer for equalizing deterioration of the waveform of the received input signal.
- a determination function for determining a bit value indicated by the input signal according to a clock from the waveform of the input signal; As a result of the determination, two consecutive bit values are the same from the determined signal composed of a plurality of bits, and the bit values before and after the two consecutive bit values are the two consecutive bit values.
- a synchronization function for detecting a different 2-bit transition signal and synchronizing the phase of the clock with the detected phase of the 2-bit transition signal.
- the equalizer determines the bit value indicated by the input signal from the waveform of the input signal according to the clock. Then, as a result of the determination, from the determined signal composed of a plurality of bits, the two consecutive bit values are the same, and the bit values before and after the two consecutive bit values are the two consecutive bit values. A 2-bit transition signal different from the above is detected, and the phase of the clock is synchronized with the phase of the detected 2-bit transition signal.
- the influence of the pre-cursor component can be removed from the input signal input to the signal receiving side while avoiding an increase in circuit scale and power consumption.
- FIG. 3 is a diagram illustrating an example of a 2-bit transition signal and a 1-bit transition signal of a determined signal output from a determination unit illustrated in FIG. 2. It is a figure which shows the other example of the 2 bit transition signal of the determined signal output from the determination part shown in FIG. 2, and a 1 bit transition signal.
- FIG. 5 is a diagram for explaining an operation for removing the influence of a pre-cursor component in the example shown in FIG. 4.
- 3 is a flowchart for explaining an operation in which the equalizer shown in FIG.
- FIG. 2 is a block diagram showing an example of the configuration of the first embodiment of the equalization apparatus of the present invention.
- the equalization apparatus 10 of the present embodiment includes an equalization unit 11, a phase detection unit 12 having a 2-bit transition pattern filter 12-1, a phase timing determination unit 13, a clock output unit 14, It has.
- the equalization unit 11 supports the duobinary transmission method.
- the duobinary transmission system is a transmission system that allows intersymbol interference only between adjacent signals. Thereby, the frequency band required for signal transmission between the signal transmission side and the signal reception side can be compressed. Therefore, low-band transmission is possible.
- the signal transmission side modulates data into a signal in accordance with, for example, a change of 2 bits adjacent to the data to be transmitted, and the modulated signal becomes an input signal to the reception side.
- This input signal indicates one of three values “0”, “1”, or “2” in accordance with a change in the bit value of two adjacent bits. Specifically, when the bit values of two adjacent bits are both “0”, the input signal input to the receiving side is “0”. When one of the bit values of two adjacent bits is “1” and the other is “0”, the input signal is “1”. Further, when both of two bit values of adjacent bits are “1”, the input signal is “2”.
- the equalization unit 11 determines a bit value of 0 or 1 from the waveform of the signal indicating three values as described above, and is a determination result that outputs a determined signal composed of a plurality of bits. -1 and an adder 11-2.
- the addition unit 11-2 receives a signal transmitted from the signal transmission side as an input signal. Then, an addition signal obtained by adding the received input signal and the determined signal output from the determination unit 11-1 is generated, and the generated addition signal is output to the determination unit 11-1.
- the determination unit 11-1 receives the addition signal output from the addition unit 11-2. Then, the bit value indicated by the added signal is determined from the waveform of the received added signal. This determination is performed according to the clock output from the clock output unit 14. Then, the determining unit 11-1 outputs a determined signal to the adding unit 11-2 and the phase detecting unit 12. In this way, the influence of the post-cursor component can be removed by feeding back the result of determination by the determination unit 11-1 to the addition unit 11-2.
- the phase detection unit 12 receives the determined signal output from the equalization unit 11, and uses the 2-bit transition pattern filter 12-1 to detect a 2-bit transition signal from the received determined signal.
- the 2-bit transition signal is a signal in which two consecutive bit values in the determined signal are the same, and the bit values before and after the two consecutive bit values are different from the two consecutive bit values. That is. For example, the “11” portion of the bit string “0110” or the “00” portion of the bit string “1001” is a 2-bit transition signal. Note that a 1-bit transition signal described later is a signal in which the bit values of two consecutive bits in the determined signal are different.
- the phase detection unit 12 outputs phase information indicating the phase of the 2-bit transition signal at the common voltage threshold to the phase timing determination unit 13.
- the common voltage threshold is a central potential in the differential signal.
- the phase timing determination unit 13 receives the phase information output from the phase detection unit 12, and determines the timing for generating the clock based on the phase indicated by the received phase information. Specifically, the phase timing determination unit 13 adjusts the timing for generating the clock so that the phase of the clock advances when the phase of the clock is delayed from the phase indicated by the received phase information. On the other hand, when the phase of the clock is ahead of the phase indicated by the phase information, the timing for generating the clock is adjusted so that the phase of the clock is delayed. Then, the phase timing determination unit 13 outputs timing information indicating the determined timing to the clock output unit 14.
- the clock output unit 14 receives the timing information output from the phase timing determination unit 13, generates a clock at the timing indicated by the received timing information, and outputs the generated clock to the equalization unit 11.
- FIG. 3 is a diagram illustrating an example of a 2-bit transition signal and a 1-bit transition signal of the determined signal output from the determination unit 11-1 illustrated in FIG. FIG. 3 shows a case where there is no influence by the pre-cursor component.
- the sampling point of the main bit is the position indicated by the sampling point 151.
- the main bit is a bit whose bit value is to be determined.
- the rising portions of the 1-bit transition signal 101-1 and the 2-bit transition signal 101-2 overlap at the sampling point 151 as shown in FIG. As described above, the overlapping of the rising portions of the 1-bit transition signal 101-1 and the 2-bit transition signal 101-2 at the sampling point 151 indicates that there is no influence of the pre-cursor component.
- FIG. 4 is a diagram illustrating another example of the 2-bit transition signal and the 1-bit transition signal of the determined signal output from the determination unit 11-1 illustrated in FIG. FIG. 4 shows a case where there is an influence by the pre-cursor component.
- the rising portions of the 1-bit transition signal 201-1 and the 2-bit transition signal 201-2 do not overlap at the sampling point 151 as shown in FIG. In this case, if the sampling point 151 can be moved to a position where the rising portions of the 1-bit transition signal 201-1 and the 2-bit transition signal 201-2 overlap, the influence of the pre-cursor component is eliminated.
- FIG. 5 is a diagram for explaining an operation for removing the influence of the pre-cursor component in the example shown in FIG.
- FIG. 6 is a flowchart for explaining the operation of the equalizer 10 shown in FIG. 2 for removing the influence of the pre-cursor component.
- the adding unit 11-2 receives a signal transmitted from the signal transmission side as an input signal. Then, an addition signal obtained by adding the received input signal and the determined signal output from the determination unit 11-1 is generated, and the generated addition signal is output to the determination unit 11-1.
- the determination unit 11-1 receives the addition signal output from the addition unit 11-2. Then, according to the clock output from the clock output unit 14, the bit value indicated by the added signal is determined from the waveform of the received added signal (step S1).
- the determining unit 11-1 outputs a determined signal to the adding unit 11-2 and the phase detecting unit 12.
- the phase detection unit 12 that has received the determined signal output from the determination unit 11-1 detects the 2-bit transition signal 201-2 from the received determined signal by using the 2-bit transition pattern filter 12-1. S2).
- phase detection unit 12 outputs phase information indicating the phase of the detected 2-bit transition signal 201-2 at the common voltage threshold value 152-1 to the phase timing determination unit 13.
- the phase timing determination unit 13 that has received the phase information output from the phase detection unit 12 determines the timing for generating a clock based on the phase indicated by the received phase information (step S3). As a result, the phase of the clock is fixed at the clock phase fixing position 251-1.
- the phase timing determination unit 13 outputs timing information indicating that the clock phase fixed position 251-1 is a timing for generating a clock to the clock output unit 14.
- the clock output unit 14 that has received the timing information output from the phase timing determination unit 13 generates a clock at the timing indicated by the received timing information (step S4). Then, the clock output unit outputs the generated clock to the equalization unit 11.
- step S5 equalization in the determination unit 11-1 is optimized in accordance with a change in the phase of the clock output from the clock output unit 14 (step S5).
- the common voltage threshold 152-1 is corrected by optimization of equalization in step S5 (step S6). Specifically, an intermediate value between the voltage value of the 2-bit transition signal 201-2 and the voltage value of the 1-bit transition signal 201-1 at the clock phase fixed position 251-1 becomes the corrected common voltage threshold value 152-2. .
- step S1 the determination unit 11-1 determines the bit value indicated by the addition signal from the waveform of the received addition signal according to the clock output from the clock output unit 14.
- step S6 the common voltage threshold value 152-1 is corrected to the corrected common voltage threshold value 152-2.
- the phase of the 2-bit transition signal 201-2 at the corrected common voltage threshold 152-2 is different from the phase at the common voltage threshold 152-1.
- the clock phase fixing position is also the corrected clock phase fixing position 251-2. Accordingly, the corrected common voltage threshold value 152-2 is also corrected.
- the clock phase approaches the phase of the 2-bit transition signal. That is, the phase of the clock and the phase of the 2-bit transition signal are synchronized. As a result, the rising portions of the 1-bit transition signal 201-1 and the 2-bit transition signal 201-2 overlap, and the influence of the pre-cursor component is removed.
- the equalization apparatus 10 determines the bit value indicated by the input signal from the waveform of the input signal according to the clock. Then, as a result of the determination, from the determined signal composed of a plurality of bits, the two consecutive bit values are the same, and the bit values before and after the two consecutive bit values are the two consecutive bit values. A 2-bit transition signal different from the above is detected, and the phase of the clock is synchronized with the phase of the detected 2-bit transition signal.
- the influence of the pre-cursor component can be removed from the input signal input to the signal receiving side while avoiding an increase in circuit scale and power consumption.
- the equalization unit 11 includes one determination unit and one addition unit, but may have an n-phase configuration (n is a natural number) including a plurality of determination units and addition units.
- FIG. 7 is a block diagram showing another example of the configuration example of the first embodiment of the equalization apparatus of the present invention.
- An equalizing apparatus 110 shown in FIG. 7 has a two-phase circuit configuration of the equalizing apparatus 10 shown in FIG.
- the equalization unit 111 includes two determination units 11-1 and two addition units 11-2, the influence of the post-cursor component is removed in two stages. Even in this case, the configurations and operations of the phase detection unit 12, the phase timing determination unit 13, and the clock output unit 14 for removing the influence of the pre-cursor component are the same as those of the equalization apparatus 10 shown in FIG. Therefore, description is abbreviate
- the equalizer has an n-phase configuration, the influence of the pre-cursor component is removed from the input signal input to the signal receiving side while avoiding an increase in circuit scale and power consumption. can do.
- FIG. 8 is a block diagram showing an example of the configuration of the second embodiment of the equalization apparatus of the present invention.
- the equalization apparatus includes the determination unit 11-1 corresponding to the duobinary transmission method.
- a determination unit 21-1a that is a first determination unit and a determination unit 21-1b that is a second determination unit are provided instead of the determination unit 11-1.
- a selection unit 21-3 is provided.
- the determination unit 21-1a receives the addition signal output from the addition unit 21-2. Then, the bit value indicated by the added signal is determined from the waveform of the received added signal according to the clock output from the clock output unit 14. At this time, the determination unit 21-1a determines the bit value with reference to the first voltage threshold value obtained by increasing the threshold value for determining the bit value by the voltage value corresponding to the first post-cursor included in the input signal. judge. Then, the determination unit 21-1a outputs the first determined signal composed of a plurality of bits to the selection unit 21-3 as a result of the determination.
- the determination unit 21-1b receives the addition signal output from the addition unit 21-2. Then, the bit value indicated by the added signal is determined from the waveform of the received added signal according to the clock output from the clock output unit 14. At this time, the determination unit 21-1b sets the bit value with reference to the second voltage threshold obtained by reducing the threshold for determining the bit value by the voltage value corresponding to the first post-cursor included in the input signal. judge. Then, the determination unit 21-1b outputs a second determined signal composed of a plurality of bits to the selection unit 21-3 as a result of the determination.
- the selection unit 21-3 receives the first determined signal output from the determination unit 21-1a and the second determined signal output from the determination unit 21-1b. Then, the received first determined signal or second determined signal is selected for each bit. At this time, which signal bit is selected is determined based on the bit value of the bit that has been previously selected. Then, the selection unit 21-3 outputs a signal indicating the bit value of the selected bit to the addition unit 21-2 and the phase detection unit 12 as a determined signal.
- the equalization unit 21 performs speculative execution.
- Speculative execution generally means that the computer executes code that might actually discard the result.
- the bit value indicated by the input signal is determined based on a value obtained by increasing or decreasing the common voltage threshold by the voltage value corresponding to the first post cursor. As a result, the one that correctly equalizes the input signal is selected. In other words, the result that is not correctly equalized is discarded.
- the determination units 21-1a and 21-1b perform determination in consideration of a voltage value corresponding to the first post cursor. That is, a signal including the influence of the first post-cursor is output to the phase detection unit 12 as a determined signal. Therefore, also in the present embodiment, as in the first embodiment described above, the determined signal includes the 1-bit transition signal and the 2-bit transition signal.
- phase detection unit 12 the phase timing determination unit 13, and the clock output unit 14 operate in the same manner as in the first embodiment described above, thereby avoiding an increase in circuit scale and an increase in power consumption while receiving signals.
- the influence of the pre-cursor component can be removed from the input signal input to the side.
- the equalization unit includes an n-phase (multiple determination units 21-1a and 21-1b, an addition unit 21-2, and a selection unit 21-3).
- n may be a natural number).
- FIG. 9 is a block diagram showing another example of the configuration of the second embodiment of the equalization apparatus of the present invention.
- the equalizer 120 shown in FIG. 9 has a two-phase circuit configuration of the equalizer 20 shown in FIG.
- the equalization unit 121 includes two determination units 21-1a and 21-1b, two addition units 21-2, and two selection units 21-3, the influence of the post-cursor component is expressed in two stages. Remove with.
- the configurations and operations of the phase detection unit 12, the phase timing determination unit 13, and the clock output unit 14 for removing the influence of the pre-cursor component are the same as those of the equalization apparatus 20 shown in FIG. Therefore, description is abbreviate
- the equalizer has an n-phase configuration, the influence of the pre-cursor component is removed from the input signal input to the signal receiving side while avoiding an increase in circuit scale and power consumption. can do.
- the equalization units 11 and 111 and the equalization units 21 and 121 correspond to the duobinary transmission method, and the bit value is obtained from the waveform of a signal indicating three values. The case of determining is described.
- the equalization units 11 and 111 in the first embodiment may determine the bit value from the waveform of a signal indicating a binary value.
- the determination unit 11-1 can detect the 2-bit transition signal by determining the bit value and the waveform transition. Then, the influence of the pre-cursor can be eliminated by synchronizing the phase of the detected 2-bit transition signal with the phase of the clock.
- the equalization units 21 and 121 in the second embodiment may determine the bit value from a binary signal.
- the determination units 21-1a and 21-1b can detect the 2-bit transition signal by determining the bit value and the waveform transition. Then, the influence of the pre-cursor can be eliminated by synchronizing the phase of the detected 2-bit transition signal with the phase of the clock.
- the processing in the equalizer is recorded on a recording medium that can be read by the equalizer, in addition to the above-described dedicated hardware.
- the program recorded on the recording medium may be read by the equalization device and executed.
- the recording medium that can be read by the equalizer refers to a transfer medium such as a flexible disk, a magneto-optical disk, a DVD, and a CD, and an HDD built in the equalizer.
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Abstract
Description
前記入力信号の波形から、当該入力信号が示すビット値をクロックに従って判定し、該判定の結果であり、複数のビットから構成される判定済信号から、連続する2つのビット値が同じであり、当該連続する2つのビット値の前後のビット値が当該連続する2つのビット値と異なる2ビット遷移信号を検出し、前記クロックの位相を前記検出された2ビット遷移信号の位相に同期させる。
前記入力信号の波形から、当該入力信号が示すビット値をクロックに従って判定する判定処理と、
前記判定の結果であり、複数のビットから構成される判定済信号から、連続する2つのビット値が同じであり、当該連続する2つのビット値の前後のビット値が当該連続する2つのビット値と異なる2ビット遷移信号を検出し、前記クロックの位相を前記検出された2ビット遷移信号の位相に同期させる同期処理と、を有する。
前記入力信号の波形から、当該入力信号が示すビット値をクロックに従って判定する判定機能と、
前記判定の結果であり、複数のビットから構成される判定済信号から、連続する2つのビット値が同じであり、当該連続する2つのビット値の前後のビット値が当該連続する2つのビット値と異なる2ビット遷移信号を検出し、前記クロックの位相を前記検出された2ビット遷移信号の位相に同期させる同期機能と、を実現させる。
図2は、本発明の等化装置の第1の実施形態の構成の一例を示すブロック図である。
図8は、本発明の等化装置の第2の実施形態の構成の一例を示すブロック図である。
Claims (15)
- 信号の送信側から送信された信号を入力信号として受信し、該受信した入力信号の波形の劣化を等化する等化装置であって、
前記入力信号の波形から、当該入力信号が示すビット値をクロックに従って判定し、該判定の結果であり、複数のビットから構成される判定済信号から、連続する2つのビット値が同じであり、当該連続する2つのビット値の前後のビット値が当該連続する2つのビット値と異なる2ビット遷移信号を検出し、前記クロックの位相を前記検出された2ビット遷移信号の位相に同期させる等化装置。 - 請求項1に記載の等化装置において、
前記クロックを出力するクロック出力部と、
前記クロック出力部から出力された前記クロックに従い、前記入力信号の波形から当該入力信号が示すビット値を判定し、該判定した結果を前記判定済信号として出力する等化部と、
前記等化部から出力された判定済信号を受け付け、該受け付けた判定済信号から前記2ビット遷移信号を検出し、前記クロックの位相の変化に応じて変化する電圧閾値における前記検出された前記2ビット遷移信号の位相を示す位相情報を出力する位相検出部と、
前記位相検出部から出力された位相情報を受け付け、該受け付けた位相情報が示す位相に基づいて前記クロックを発生させるタイミングを決定し、該決定されたタイミングを示すタイミング情報を出力する位相タイミング決定部と、を有し、
前記クロック出力部は、前記位相タイミング決定部から出力されたタイミング情報が示すタイミングで前記クロックを発生させ、該発生させた前記クロックを出力する等化装置。 - 請求項2に記載の等化装置において、
前記等化部は、
前記入力信号と前記判定済信号とを受け付け、該受け付けた前記入力信号と前記判定済信号とを加算した加算信号を出力する加算部と、
前記クロックに従い、前記加算信号の波形から当該加算信号が示すビット値を判定し、該判定した結果を前記判定済信号として出力する判定部と、を有する等化装置。 - 請求項2に記載の等化装置において、
前記等化部は、
前記入力信号と前記判定済信号とを受け付け、該受け付けた前記入力信号と前記判定済信号とを加算した加算信号を出力する加算部と、
前記入力信号に含まれるポストカーソルによる当該入力信号の電圧値の変化に応じた第1の電圧閾値を基準とし、前記加算信号の波形から当該加算信号が示すビット値を前記クロックに従って判定し、該判定の結果であり、複数のビットから構成される第1の判定済信号を出力する第1の判定部と、
前記入力信号に含まれるポストカーソルによる当該入力信号の電圧値の変化に応じた前記第1の電圧閾値とは異なる第2の電圧閾値を基準とし、前記加算信号の波形から当該加算信号が示すビット値を判定し、該判定の結果であり、複数のビットから構成される第2の判定済信号を出力する第2の判定部と、
前記第1の判定済信号または前記第2の判定済信号をビット毎に選択し、該選択されたビットのビット値を示す信号を前記判定済信号として出力する選択部と、を有する等化装置。 - 請求項4に記載の等化装置において、
前記選択部は、前記選択の対象となるビットよりも前に選択したビットのビット値に基づき、前記第1の判定済信号または第2の判定済信号をビット毎に選択する等化装置。 - 信号の送信側から送信された信号を入力信号として受信し、該受信した入力信号の波形の劣化を等化する等化装置における等化方法であって、
前記入力信号の波形から、当該入力信号が示すビット値をクロックに従って判定する判定処理と、
前記判定の結果であり、複数のビットから構成される判定済信号から、連続する2つのビット値が同じであり、当該連続する2つのビット値の前後のビット値が当該連続する2つのビット値と異なる2ビット遷移信号を検出し、前記クロックの位相を前記検出された2ビット遷移信号の位相に同期させる同期処理と、を有する等化方法。 - 請求項6に記載の等化方法において、
前記同期処理は、
前記判定済信号から前記2ビット遷移信号を検出する処理と、
前記クロックの位相の変化に応じて変化する電圧閾値における前記検出された前記2ビット遷移信号の位相に基づき、前記クロックを発生させるタイミングを決定する処理と、を含む等化方法。 - 請求項7に記載の等化方法において、
前記判定処理は、
前記入力信号と前記判定済信号とを加算した加算信号を生成する処理と、
前記クロックに従い、前記加算信号の波形から当該加算信号が示すビット値を判定し、該判定した結果を前記判定済信号とする処理と、を含む等化方法。 - 請求項7に記載の等化方法において、
前記判定処理は、
前記入力信号と前記判定済信号とを加算した加算信号を生成する処理と、
前記入力信号に含まれるポストカーソルによる当該入力信号の電圧値の変化に応じた第1の電圧閾値を基準とし、前記加算信号の波形から当該加算信号が示すビット値を前記クロックに従って判定し、該判定の結果であり、複数のビットから構成される第1の判定済信号を生成する処理と、
前記入力信号に含まれるポストカーソルによる当該入力信号の電圧値の変化に応じた前記第1の電圧閾値とは異なる第2の電圧閾値を基準とし、前記加算信号の波形から当該加算信号が示すビット値を判定し、該判定の結果であり、複数のビットから構成される第2の判定済信号を生成する処理と、
前記第1の判定済信号または前記第2の判定済信号をビット毎に選択し、該選択されたビットのビット値を示す信号を前記判定済信号とする選択処理と、を含む等化方法。 - 請求項9に記載の等化方法において、
前記選択処理は、前記選択の対象となるビットよりも前に選択したビットのビット値に基づき、前記第1の判定済信号または第2の判定済信号をビット毎に選択する処理である等化方法。 - 信号の送信側から送信された信号を入力信号として受信し、該受信した入力信号の波形の劣化を等化する等化装置に、
前記入力信号の波形から、当該入力信号が示すビット値をクロックに従って判定する判定機能と、
前記判定の結果であり、複数のビットから構成される判定済信号から、連続する2つのビット値が同じであり、当該連続する2つのビット値の前後のビット値が当該連続する2つのビット値と異なるである2ビット遷移信号を検出し、前記クロックの位相を前記検出された2ビット遷移信号の位相に同期させる同期機能と、を実現させるためのプログラム。 - 請求項11に記載のプログラムにおいて、
前記同期機能は、
前記判定済信号から前記2ビット遷移信号を検出する機能と、
前記クロックの位相の変化に応じて変化する電圧閾値における前記検出された前記2ビット遷移信号の位相に基づき、前記クロックを発生させるタイミングを決定する機能と、を含むプログラム。 - 請求項12に記載のプログラムにおいて、
前記判定機能は、
前記入力信号と前記判定済信号とを加算した加算信号を生成する機能と、
前記クロックに従い、前記加算信号の波形から当該加算信号が示すビット値を判定し、該判定された結果を前記判定済信号とする機能と、を含むプログラム。 - 請求項12に記載のプログラムにおいて、
前記判定機能は、
前記入力信号と前記判定済信号とを加算した加算信号を生成する機能と、
前記入力信号に含まれるポストカーソルによる当該入力信号の電圧値の変化に応じた第1の電圧閾値を基準とし、前記加算信号の波形から当該加算信号が示すビット値を前記クロックに従って判定し、該判定の結果であり、複数のビットから構成される第1の判定済信号を生成する機能と、
前記入力信号に含まれるポストカーソルによる当該入力信号の電圧値の変化に応じた前記第1の電圧閾値とは異なる第2の電圧閾値を基準とし、前記加算信号の波形から当該加算信号が示すビット値を判定し、該判定の結果であり、複数のビットから構成される第2の判定済信号を生成する機能と、
前記第1の判定済信号または前記第2の判定済信号をビット毎に選択し、該選択されたビットのビット値を示す信号を前記判定済信号とする選択機能と、を含むプログラム。 - 請求項14に記載のプログラムにおいて、
前記選択機能は、前記選択の対象となるビットよりも前に選択したビットのビット値に基づき、前記第1の判定済信号または第2の判定済信号をビット毎に選択する機能であるプログラム。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05198101A (ja) * | 1991-09-03 | 1993-08-06 | Matsushita Electric Ind Co Ltd | タイミング再生装置とオートスライサ装置 |
JPH0845185A (ja) * | 1994-08-02 | 1996-02-16 | Canon Inc | 情報再生装置 |
JPH09326170A (ja) * | 1996-06-05 | 1997-12-16 | Hitachi Ltd | 磁気ディスク記録装置の等化フィルタ係数設定方法 |
JPH1027433A (ja) * | 1996-07-09 | 1998-01-27 | Matsushita Electric Ind Co Ltd | ディジタル信号の復号装置 |
JPH10326457A (ja) * | 1997-05-26 | 1998-12-08 | Victor Co Of Japan Ltd | 自動等化システム |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4805197A (en) * | 1986-12-18 | 1989-02-14 | Lecroy Corporation | Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal |
JPH0767062B2 (ja) | 1992-02-27 | 1995-07-19 | 日本電気株式会社 | ディジタル信号記録再生装置用自動等化器 |
JP3293742B2 (ja) | 1996-06-28 | 2002-06-17 | 日本電気株式会社 | 判定帰還型信号推定器 |
JP3070569B2 (ja) | 1998-02-04 | 2000-07-31 | 日本電気株式会社 | 自動等化器及びこれに用いるサンプリングクロック生成方法並びに記録媒体 |
-
2010
- 2010-06-01 WO PCT/JP2010/059257 patent/WO2010150624A1/ja active Application Filing
- 2010-06-01 JP JP2011519716A patent/JP5423793B2/ja active Active
- 2010-06-01 US US13/378,632 patent/US8638842B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05198101A (ja) * | 1991-09-03 | 1993-08-06 | Matsushita Electric Ind Co Ltd | タイミング再生装置とオートスライサ装置 |
JPH0845185A (ja) * | 1994-08-02 | 1996-02-16 | Canon Inc | 情報再生装置 |
JPH09326170A (ja) * | 1996-06-05 | 1997-12-16 | Hitachi Ltd | 磁気ディスク記録装置の等化フィルタ係数設定方法 |
JPH1027433A (ja) * | 1996-07-09 | 1998-01-27 | Matsushita Electric Ind Co Ltd | ディジタル信号の復号装置 |
JPH10326457A (ja) * | 1997-05-26 | 1998-12-08 | Victor Co Of Japan Ltd | 自動等化システム |
Non-Patent Citations (1)
Title |
---|
KOICHI YAMAGUCHI ET AL.: "12Gb/s duobinary signaling with x2 oversampled edge equalization", IEICE TECHNICAL REPORT, vol. 105, no. 96, 20 May 2005 (2005-05-20), pages 13 - 18 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2015501589A (ja) * | 2011-10-21 | 2015-01-15 | 日本テキサス・インスツルメンツ株式会社 | 推論的判定フィードバック等化を実行するための方法及び装置 |
US9166771B2 (en) | 2013-10-25 | 2015-10-20 | Fujitsu Limited | Reception circuit |
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