WO2010073789A1 - 歪補償回路 - Google Patents
歪補償回路 Download PDFInfo
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- WO2010073789A1 WO2010073789A1 PCT/JP2009/067036 JP2009067036W WO2010073789A1 WO 2010073789 A1 WO2010073789 A1 WO 2010073789A1 JP 2009067036 W JP2009067036 W JP 2009067036W WO 2010073789 A1 WO2010073789 A1 WO 2010073789A1
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- distortion compensation
- memory unit
- input
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- output
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3258—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits based on polynomial terms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/336—A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
- H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
- H03F2201/3212—Using a control circuit to adjust amplitude and phase of a signal in a signal path
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
- H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
- H03F2201/3233—Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
Definitions
- the present invention relates to a distortion compensation circuit having a function of compensating for nonlinear characteristics of a high-power amplifier used in, for example, a radio transceiver.
- HPA High Power Amplifier
- a desired output may not be obtained due to distortion of input / output characteristics. Therefore, in order to compensate for the distortion of such an amplifier, a distortion that is generated by digital signal processing and is applied to the input of the amplifier, the reverse distortion characteristic opposite to the distortion characteristic of the amplifier is applied to the input signal of the amplifier.
- a distortion compensation circuit that obtains a desired amplifier output by performing compensation processing has been proposed (see, for example, Non-Patent Document 1).
- the distortion compensation circuit once the input signal and output signal of the amplifier are acquired, the distortion is not completely compensated.
- the input signal and output signal of the amplifier are acquired, and the inverse of the amplifier based on these input and output signals is obtained. It is necessary to repeat the procedures such as the estimation of the distortion characteristics, the distortion compensation process, the acquisition of the input / output signal of the amplifier again, and so on to compensate the distortion gradually.
- the above distortion compensation circuit requires time to perform inverse distortion characteristic estimation and distortion compensation processing from the time when the input / output signal is acquired until the effect of distortion compensation is reflected in the input signal of the amplifier. Therefore, when distortion compensation is performed based on the input / output signal acquired in a certain time zone, if the input / output signal is acquired again in the time zone immediately after the time zone in which the input / output signal is acquired, The signal does not reflect the effect of distortion compensation by the distortion compensation process, and the distortion compensation process is performed based on the input / output signal that is almost the same as the input / output signal acquired immediately before.
- the conventional distortion compensation circuit has a problem of performing such a wasteful process, and it cannot be said that distortion compensation can be performed efficiently.
- an object of the present invention is to provide a distortion compensation circuit that can perform distortion compensation more efficiently.
- a distortion compensation circuit of the present invention includes a memory unit that stores an input signal and an output signal of an amplifier, and reads out the input signal and the output signal that are stored in the memory unit.
- a model estimation unit that estimates a model representing input / output characteristics and outputs a parameter indicating the estimated model; a distortion compensation unit that performs distortion compensation of the amplifier based on the parameter output by the model estimation unit; After the input signal and the output signal for a predetermined time are stored in the memory unit, and after the distortion compensation by the parameters obtained from the input signal and the output signal stored in the memory unit is performed by the distortion compensation unit
- a control unit that controls the memory unit to re-accumulate the input signal and the output signal for obtaining a new parameter. It is characterized in Rukoto.
- the control unit accumulates the input / output signals for a predetermined time in the memory unit, and the distortion caused by the parameters obtained from the input signal and the output signal accumulated in the memory unit.
- the memory unit is controlled to re-accumulate the input signal and output signal for obtaining a new parameter, so that the input signal and output signal for a predetermined time are accumulated in the memory unit.
- the distortion compensation is performed (the input / output signal reflecting the distortion compensation by the parameter obtained from the input signal and the output signal accumulated in the memory section is obtained), The signal is not accumulated. Therefore, the input / output signal stored in the memory unit can reflect the effect of distortion compensation based on the input / output signal stored in the memory unit immediately before.
- the memory unit is configured by a memory that is set to a capacity capable of storing the input signal and the output signal for the predetermined time and that cannot be written when the memory is full. It may be a thing.
- the memory unit if the memory unit is in a memory full state, the input / output signal for a predetermined time is stored in the memory unit, so that the control unit determines that the input / output signal for the predetermined time has been stored in the memory unit.
- the memory unit can be easily grasped, and the memory unit can be controlled easily and simply so as to stop the accumulation of the input / output signals by the memory unit.
- FIG. 1 is a circuit diagram showing a hardware configuration of an amplifying apparatus 1 incorporating a distortion compensation circuit according to the present invention.
- the amplifying device 1 is for amplifying a transmission signal of a wireless communication device or the like, and includes a digital processing unit 2 functionally including the distortion compensation circuit, and a high output amplifier (HPA, hereinafter simply referred to as an amplifier). ) 4 is provided.
- HPA high output amplifier
- the digital processing unit 2 provides a transmission signal as an input signal input to the amplifier 4 to the analog processing unit 3 and acquires an output signal output from the amplifier 4 from the analog processing unit 3.
- the analog processing unit 3 includes a power supply unit 5 that applies a power supply voltage to the amplifier 4, and a DA (digital-analog) converter (DAC) is provided between the digital processing unit 2 and the signal input terminal of the amplifier 4.
- DAC digital-analog converter
- DAC digital-analog converter
- the digital processing unit 2 outputs a signal before quadrature modulation composed of an in-phase component and a quadrature component to the analog processing unit 3.
- the analog processing unit 3 includes a DA (digital-analog) converter (DAC) 6 and a low-pass filter 7 for both components of the signal. Both components analog-converted by the DA converter 6 are orthogonally modulated by the modulator 8 and input to the amplifier 4.
- DAC digital-analog converter
- the analog processing unit 3 also includes a mixer 10 that mixes the signal from the oscillator 10a between the signal output terminal of the amplifier 4 and the digital processing unit 2, a low-pass filter 11, and an AD (analog-digital) converter ( ADC) 12 is arranged and connected.
- the digital processing unit 2 acquires the output signal from the amplifier 4 through these. Therefore, in the present embodiment, the digital processing unit 2 acquires the output signal from the amplifier 4 as a signal in a state of being orthogonally modulated.
- FIG. 2 is a block diagram showing a configuration of the distortion compensation circuit 20 that the digital processing unit 2 has in terms of function.
- the distortion compensation circuit 20 performs a distortion compensation process on the amplification characteristic of the amplifier 4 based on the input signal to the amplifier 4 and the output signal of the amplifier 4 acquired from the analog processing unit 3, thereby obtaining a desired amplification characteristic.
- the sampling memory unit 21 for storing the input signal y and the output signal z of the amplifier 4 and the input / output signals y and z stored in the sampling memory unit 21 are read out to obtain the input / output characteristics of the amplifier 4.
- a model estimation unit 22 that estimates a model to be represented, a distortion compensation unit 23 that performs distortion compensation of the amplifier 4 based on the model, and a coefficient memory unit 24 that accumulates coefficients indicating the model output from the model estimation unit 22; And a control unit 25 that controls the operation of the sampling memory unit 21.
- the distortion compensator 23 performs distortion compensation processing corresponding to the distortion characteristics of the amplifier 4 on the signal (signal before distortion compensation) x given to the amplification device 1 and inputs the input signal y (after distortion compensation) to the amplifier 4 Signal).
- the amplifier 4 is supplied with an input signal y that has been subjected to distortion compensation in advance from the distortion compensation unit 23. For this reason, the amplifier 4 can output the output signal z without (or with little distortion).
- the input / output characteristic of the amplifier 4 is a non-linear characteristic and is expressed by a power series polynomial shown in the following formula (1).
- Equation (1) z (t) is the output signal of the amplifier 4 at a certain time t, y (t) is the input signal of the amplifier 4, i is the order, and n is the past ( A time width indicating whether it is a timing moved in time to the previous timing) or the future (previous timing), a in is a next coefficient corresponding to the time width n, and Equation (1) is the current signal
- past and future signals are also considered as characteristics.
- the distortion compensator 23 calculates a power series polynomial shown in the following equation (2) to obtain the input signal y (t) of the amplifier 4.
- a in ′ is a coefficient of each order indicating the inverse characteristic of the amplifier.
- the distortion compensator 23 is based on each order coefficient a in ′ indicating the inverse characteristics of the amplifier 4 as a model representing the input / output characteristics of the amplifier 4, and thereby the distortion characteristics of the amplifier 4. Is added to the signal x (t) and the distortion caused by the amplifier 4 is canceled to compensate for the distortion.
- Each order coefficient a in ′ indicating the inverse characteristic of the amplifier 4 in the above equation (2) is obtained by the model estimation unit 22.
- the model estimation unit 22 reads input / output signal data related to the input signal y (t) and the output signal z (t) of the amplifier 4 stored in the sampling memory unit 21, and based on these, the input / output signal of the amplifier 4 is read out.
- a model representing the characteristic is estimated, and the respective coefficients a in ′ are obtained as parameters indicating the estimated model.
- the signal before distortion compensation, the input signal, and the output signal are shown as x (t), y (t), and z (t), respectively. In the following description, they are also simply indicated as x, y, and z.
- the input signal y is a signal before quadrature modulation
- the analog processing unit 3 The acquired output signal z is a signal in a quadrature modulated state. Therefore, first, the model estimation unit 22 performs quadrature demodulation of the output signal z. Thereafter, after synchronizing the signal pattern, frequency, phase, and the like between the input signal y and the output signal z, these input / output signals y and z are used for the calculation of the coefficient a in ′.
- the model estimation unit 22 has an amplifier model (inverse model) in which the input signal y is expressed by a power series polynomial of the output signal z, and the output signal z read from the sampling memory unit 21 is applied to the model. Then, an estimated value of the input signal y is obtained. Further, the model estimation unit 22 estimates a model when the difference between the estimated value and the input signal y read from the sampling memory unit 21 is minimum as a model representing the current input / output characteristics of the amplifier 4. The model estimation unit 22 obtains each order coefficient of the estimated model, and outputs this coefficient as each order coefficient a in ′ indicating the inverse characteristic of the amplifier 4.
- the model estimation unit 22 when outputting the coefficient a in' coefficient a in by adding a CRC code and outputs the information indicating the.
- the model estimation unit 22 outputs the coefficient a in ′ to the coefficient memory unit 24.
- the coefficient memory unit 24 temporarily stores the coefficient a in ′.
- the accumulated coefficient a in ′ is subjected to CRC check by the control unit 25. As a result, it is possible to confirm whether or not the coefficient a in ′ has been normally transferred between the model estimation unit 22 and the coefficient memory unit 24, and subsequent distortion compensation processing is performed using an incorrect coefficient. Can be prevented.
- the coefficient memory unit 24 outputs the coefficient a in ′ to the distortion compensation unit 23 after the CRC check by the control unit 25.
- the distortion compensation unit 23 inputs the input signal y (the signal after distortion compensation) input to the amplifier 4 based on the coefficient a in ′ and the signal x before distortion compensation given to the amplifying apparatus 1. Is output to the amplifier 4 of the analog processing unit 3.
- the amplifier 4 is supplied with the input signal y in which distortion compensation has been performed on the signal x in advance, and can output an output signal z without (or with little distortion).
- the control unit 25 controls the operation of the sampling memory unit 21 as described above. Specifically, the sampling memory unit 21 is controlled by the control unit 25 to stop or start the accumulation of the input / output signals y and z of the amplifier 4. Further, the sampling memory unit 21 permits the model estimation unit 22 to read the input / output signal data related to the stored input / output signals y and z in response to the access from the model estimation unit 22.
- FIG. 3 is a sequence diagram illustrating the relationship between the processes performed by the sampling memory unit 21, the model estimation unit 22, the coefficient memory unit 24, and the distortion compensation unit 23.
- FIG. 2 also shows data, flags, and the like transmitted and received by the processing shown in FIG.
- step S1 of FIG. 3 the digital processing unit 2 converts the input signal y1 of the amplifier 4 into the analog processing unit 3 by the distortion compensation performed immediately before by the distortion compensating unit 23.
- the control unit 25 controls the sampling memory unit 21 so as to stop the accumulation of the input / output signals y and z.
- step S2 the control unit 25 causes the sampling memory unit 21 to start accumulating the input / output signals y and z (step S2).
- the sampling memory unit 21 starts accumulating the input signal y1 output from the distortion compensator 23 and the output signal z1 output from the amplifier 4 corresponding thereto.
- the start timing of accumulation of the input / output signals y and z by the sampling memory unit 21 in step S2 will be described later.
- the sampling memory unit 21 stores input / output signal data related to input / output signals y and z for a predetermined time (predetermined size) at which the model estimation unit 22 can acquire information necessary for calculating the coefficient a in ′.
- it is constituted by a memory set to a capacity at which the memory becomes full.
- the memory constituting the sampling memory unit 21 is configured such that writing is disabled when the memory is full. For this reason, the sampling memory unit 21 cannot store the input / output signals y and z any more when the memory is full.
- the sampling memory unit 21 is configured by, for example, a FIFO memory.
- the sampling memory unit 21 starts accumulation of the input / output signals y1 and z1 in step S2, and notifies the control unit 25 when the memory is full.
- the control unit 25 controls the sampling memory unit 21 to stop the accumulation of the input / output signals y and z (step S3). Specifically, the control unit 25 sends an instruction to stop the accumulation of the input / output signals y and z (an instruction to stop the writing side port of the sampling memory unit 21) to the sampling memory unit 21.
- the period from when the sampling memory unit 21 starts accumulating the input / output signals y1 and z1 in step S2 until the accumulation of the input / output signals y1 and z1 is stopped in step S3 is the first sampling period. Equivalent to. Thereafter, the sampling memory unit 21 continues to stop accumulating the input / output signals y and z until receiving an instruction to start accumulating the input / output signals y and z (an instruction to operate the write side port). .
- control unit 25 can cause the sampling memory unit 21 to store the input / output signal data related to the input / output signals y and z for the predetermined time. Subsequently, the control unit 25 provides the model estimation unit 22 with a data acquisition flag for causing the model estimation unit 22 to read out and acquire the input / output signal data related to the input / output signals y1 and z1 accumulated in the sampling memory unit 21. send. Upon receiving the data acquisition flag, the model estimation unit 22 accesses the sampling memory unit 21, reads the stored input / output signal data, and acquires the input / output signal data (step S4).
- the model estimation unit 22 that has acquired the input / output signal data performs an operation for obtaining each order coefficient a in ′ indicating the inverse characteristic of the amplifier based on the input / output signal data related to the input / output signals y1 and z1 ( Step S5).
- the model estimation unit 22 transfers the obtained coefficient a in ′ to the coefficient memory unit 24 (step S6).
- the coefficient memory unit 24 stores the transferred coefficient a in ′.
- the model estimation unit 22 sends a transfer completion flag indicating that to the control unit 25.
- the control unit 25 Upon receiving the transfer completion flag, the control unit 25 recognizes that all the coefficients a in ′ obtained by the model estimation unit 22 have been transferred and accumulated in the coefficient memory unit 24. Then, the control unit 25 performs a CRC check on the coefficient a in ′ accumulated in the coefficient memory unit 24 (step S7). When the control unit 25 finishes the CRC check for all the coefficients a in ′, the coefficient memory unit 24 transfers the coefficient a in ′ to the distortion compensation unit 23 (step S8).
- the distortion compensation unit 23 that has received the coefficient a in ′ from the coefficient memory unit 24 responds to the signal (the signal before distortion compensation) x given to the amplification device 1 based on the coefficient a in ′ according to the distortion characteristic of the amplifier 4.
- the distortion compensation process is performed (step S9), and the input signal y2 is output as a signal after distortion compensation (step S11).
- step S ⁇ b> 8 the coefficient memory unit 24 transfers the coefficient a in ′ to the distortion compensation unit 23 and simultaneously notifies the control unit 25 that the coefficient a in ′ has been transferred to the distortion compensation unit 23. Send transfer flag.
- Step S12 the control unit 25 causes the sampling memory unit 21 to start accumulating the input / output signals y and z at the timing when the waiting time T has elapsed after the coefficient a in ′ is transferred to the distortion compensation unit 23 in step S8. .
- the control unit 25 notifies the sampling memory unit 21 of an accumulation operation start command after the waiting time T has elapsed from the completion of data error detection.
- the coefficient a in ′ is transferred to the distortion compensator 23 and distortion compensation processing is performed by the distortion compensator 23, and the input signal y 2 reflecting the distortion compensation by the coefficient a in ′ is distorted.
- the time is set to a necessary and sufficient time to obtain the output signal z2 output from the compensation unit 23 and corresponding thereto.
- the sampling memory unit 21 accumulates the input signal y2 reflecting the distortion compensation by the coefficient a in ′ obtained from the input / output signals y1 and z1 and the output signal z2 output from the amplifier 4 corresponding thereto.
- a period from when the sampling memory unit 21 starts accumulating the input / output signals y2 and z2 to when the accumulation of the input / output signals y2 and z2 is stopped corresponds to the second sampling period.
- Each sampling period is determined, for example, according to a period until the memory unit 21 is determined to be full. Therefore, normally, the length of the second sampling period is different from the length of the first sampling period. However, the length of each sampling period may be the same.
- control unit 25 performs input compensation for obtaining a new coefficient a in ′ after performing distortion compensation by the coefficient a in ′ obtained from the input / output signals y1 and z1 accumulated in the sampling memory unit 21.
- the sampling memory unit 21 is controlled so as to re-accumulate the output signals y2 and z2.
- the steps S11 and S12 correspond to the steps S1 and S2, and the distortion compensation of the amplifier 4 is performed by repeating the same processing thereafter.
- the sampling memory unit 21 accumulates the input / output signals y (y1) and z (z1) for the predetermined time and the sampling memory unit 21 accumulates them.
- Z (z2) is re-accumulated so that the sampling memory unit 21 is controlled so that the input / output signals y (y1) and z (z1) for a predetermined time are accumulated in the sampling memory unit 21, and then distortion compensation is performed.
- the input / output signals y and z stored in the sampling memory unit 21 can reflect the distortion compensation effect based on the input / output signal stored in the sampling memory unit 21 immediately before.
- the sampling memory unit 21 can input and output signals for a predetermined period of time by which the model estimation unit 22 can acquire information necessary for calculating the coefficient a in ′. Since y and z are set to capacities that can be stored, and the memory is in a state where writing becomes impossible when the memory is full, if the sampling memory unit 21 is in the memory full state, the sampling memory unit 21 includes Input / output signals y and z for a predetermined time are accumulated.
- control unit 25 it is possible for the control unit 25 to easily grasp that the input / output signals for a predetermined time have been accumulated in the sampling memory unit 21, and to stop the accumulation of the input / output signals y and z by the sampling memory unit 21.
- the sampling memory unit 21 can be controlled easily and simply.
- the sampling memory unit 21 is configured by the FIFO memory, but other types of memories may be used. Further, the length of the sampling period for accumulating the input / output signals y and z may be different for each sampling. Further, as can be understood by those skilled in the art, the error detection of the coefficient a in ′ can be performed using another data error detection method instead of CRC.
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Abstract
Description
図1は、本発明に係る歪補償回路が組み込まれた増幅装置1のハードウェア構成を示す回路図である。この増幅装置1は、無線通信装置等の送信信号を増幅するためのものであり、前記歪補償回路を機能的に有するデジタル処理部2、及び、高出力増幅器(HPA、以下、単に増幅器ともいう)4を有するアナログ処理部3を備えている。
アナログ処理部3は、増幅器4に電源電圧を付与する電源部5を備えており、さらに、デジタル処理部2と増幅器4の信号入力端との間に、DA(デジタル-アナログ)変換器(DAC)6、ローパスフィルタ(LPF)7、発振器8aによる信号を混合するための混合器としての機能を有する変調器8、及びドライバ増幅器9が配置接続されている。デジタル処理部2が出力する入力信号は、これらを介して、増幅器4に与えられる。なお、デジタル処理部2は、アナログ処理部3に対して同相成分と直交成分とからなる直交変調前の信号を出力する。アナログ処理部3は、前記信号の両成分それぞれについてDA(デジタル-アナログ)変換器(DAC)6及びローパスフィルタ7を有している。DA変換器6によってアナログ変換された両成分は、変調器8によって直交変調され、増幅器4へ入力される。
歪補償回路20は、増幅器4への入力信号と、アナログ処理部3から取得する増幅器4の出力信号とに基づいて増幅器4の増幅特性に対して歪補償処理を行うことで、所望の増幅特性を得るものであり、増幅器4の入力信号y及び出力信号zを蓄積するサンプリングメモリ部21と、サンプリングメモリ部21に蓄積される入出力信号y,zを読み出して、増幅器4の入出力特性を表すモデルを推定するモデル推定部22と、前記モデルに基づいて増幅器4の歪補償を行う歪補償部23と、モデル推定部22から出力される前記モデルを示す係数を蓄積する係数メモリ部24と、サンプリングメモリ部21の動作についての制御を行う制御部25とを備えている。
モデル推定部22は、係数ain´を、係数メモリ部24に出力する。係数メモリ部24は、この係数ain´を一時的に蓄積する。蓄積された係数ain´は、制御部25によって、CRCチェックが行われる。これによって、モデル推定部22と係数メモリ部24との間で係数ain´が正常に転送されたか否かを確認することができ、誤った係数によって、その後の歪補償処理が行われてしまうのを防止できる。
制御部25は、上述のように、サンプリングメモリ部21の動作についての制御を行う。具体的には、サンプリングメモリ部21は、増幅器4の入出力信号y、zの蓄積の停止、又は開始を制御部25によって制御される。また、サンプリングメモリ部21は、モデル推定部22からのアクセスに応じて、当該モデル推定部22による、蓄積された入出力信号y、zに係る入出力信号データの読み出しを許可する。
図3は、サンプリングメモリ部21、モデル推定部22、係数メモリ部24、及び、歪補償部23によって行われるそれぞれの処理の関係を示したシーケンス図である。なお、図2には、図3中に示す処理によって相互に送受されるデータやフラグ等についても示している。
制御部25は、サンプリングメモリ部21からメモリフル状態となった旨の通知を受けると、入出力信号y、zの蓄積を停止させるようにサンプリングメモリ部21を制御する(ステップS3)。具体的には、制御部25は、入出力信号y、zの蓄積を停止する旨の命令(サンプリングメモリ部21の書き込み側ポートを停止させる旨の命令)を、サンプリングメモリ部21に送る。本実施例では、サンプリングメモリ部21がステップS2で入出力信号y1、z1の蓄積を開始してからステップS3で入出力信号y1、z1の蓄積を停止するまでの期間が、第1サンプリング期間に相当する。以降、サンプリングメモリ部21は、入出力信号y、zの蓄積を開始する旨の命令(書き込み側ポートを動作させる旨の命令)を受けるまで、入出力信号y、zの蓄積の停止を継続する。
次いで、制御部25は、サンプリングメモリ部21に蓄積された入出力信号y1、z1に係る入出力信号データを、モデル推定部22に読み出して取得させるためのデータ取得フラグを当該モデル推定部22に送る。モデル推定部22は、データ取得フラグを受け取ると、サンプリングメモリ部21にアクセスし、蓄積された入出力信号データの読み出しを行い、当該入出力信号データを取得する(ステップS4)。
係数ain´を全て係数メモリ部24に転送することで転送が完了すると、モデル推定部22は、その旨を示す転送完了フラグを制御部25に送る。
上記のように構成された歪補償回路20によれば、サンプリングメモリ部21に前記所定時間分の入出力信号y(y1)、z(z1)を蓄積させるとともに、サンプリングメモリ部21に蓄積された入出力信号y(y1)、z(z1)から得られる係数ain´による歪補償が歪補償部23によって行なわれた後に、新たな係数ain´を得るための入出力信号y(y2)、z(z2)を再蓄積するようにサンプリングメモリ部21を制御するので、サンプリングメモリ部21に所定時間分の入出力信号y(y1)、z(z1)が蓄積されてから、歪補償が行われる(サンプリングメモリ部21に蓄積された入出力信号y(y1)、z(z1)から得られる係数ain´による歪補償が反映された入出力信号y(y2)、z(z2)が得られる)までの間である時間幅Uにおいては、サンプリングメモリ部21には増幅器の入出力信号が蓄積されない。
また、本実施形態において、サンプリングメモリ部21は、モデル推定部22が係数ain´を算出するのに必要な情報を取得することができる所定時間分の入出力信号y、zを蓄積可能な容量に設定されるとともに、メモリフル状態となると書き込みが不能となるメモリにより構成されているので、サンプリングメモリ部21がメモリフル状態となれば、サンプリングメモリ部21には所定時間分の入出力信号y、zが蓄積される。このため、所定時間分の入出力信号がサンプリングメモリ部21に蓄積されたことを、制御部25に容易に把握させることができ、サンプリングメモリ部21による入出力信号y、zの蓄積を停止させるように当該サンプリングメモリ部21を制御するのを容易かつ簡易に行うことができる。
Claims (7)
- 増幅器の入力信号及び出力信号を蓄積するメモリ部と、
前記メモリ部に蓄積される前記入力信号及び前記出力信号を読み出して、前記増幅器の入出力特性を表すモデルを推定し、その推定したモデルを示すパラメータを出力するモデル推定部と、
前記モデル推定部が出力する前記パラメータに基づいて前記増幅器の歪補償を行う歪補償部と、
前記メモリ部に所定時間分の前記入力信号及び前記出力信号を蓄積させるとともに、前記メモリ部に蓄積された前記入力信号及び前記出力信号から得られる前記パラメータによる歪補償が前記歪補償部によって行われた後に、新たなパラメータを得るための前記入力信号及び前記出力信号を再蓄積するように前記メモリ部を制御する制御部と、を備えていることを特徴とする歪補償回路。 - 前記メモリ部は、前記所定時間分の前記入力信号及び前記出力信号を蓄積可能な容量に設定されるとともに、メモリフル状態となると書き込みが不能となるメモリにより構成されている請求項1に記載の歪補償回路。
- 前記メモリ部は、前記歪補償部から出力された第1入力信号と、該第1入力信号に対応して前記増幅器から出力された第1出力信号とを最初に蓄積し、前記モデル推定部は、前記第1入力信号と前記第1出力信号とに基づいて第1パラメータを生成し、前記歪補償部は、前記第1パラメータにより歪補償を行って第2入力信号を生成し、
前記メモリ部は、前記第1入力信号と前記第1出力信号とを一旦取り込むと、前記第1パラメータによる歪補償が反映された前記第2入力信号が前記歪補償部から出力されるまで、蓄積動作を停止する、請求項1に記載の歪補償回路。 - 前記メモリ部は、前記増幅器が前記第2入力信号に対応する第2出力信号を出力すると、前記蓄積動作を再開して前記第2入力信号と前記2出力信号とを取り込む、請求項3に記載の歪補償回路。
- 前記メモリ部は、前記歪補償部から前記第1入力信号が出力される期間よりも短い第1サンプリング期間で前記第1入力信号と前記第1出力信号とを1回だけ取り込む、請求項3に記載の歪補償回路。
- 前記制御部は、前記第1サンプリング期間後から所定の時間幅の期間で前記蓄積動作を停止させるように前記メモリ部を制御しつつ、前記所定の時間幅の期間に前記第1パラメータのデータ誤り検出を行う、請求項5に記載の歪補償回路。
- 前記制御部は、前記データ誤り検出の完了から所定の待ち時間の経過後に前記蓄積動作の開始命令を前記メモリ部に通知し、前記メモリ部は、前記開始命令に応答して、前記第2入力信号と該第2入力信号に対応して前記増幅器から出力される第2出力信号とを第2サンプリング期間で取り込む、請求項6に記載の歪補償回路。
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RU2011129994/08A RU2011129994A (ru) | 2008-12-24 | 2009-09-30 | Схема компенсации искажений |
BRPI0923977A BRPI0923977A2 (pt) | 2008-12-24 | 2009-09-30 | circuito de compensação da distorção |
CN200980152108.XA CN102265507B (zh) | 2008-12-24 | 2009-09-30 | 失真补偿电路 |
CA2748191A CA2748191A1 (en) | 2008-12-24 | 2009-09-30 | Distortion compensation circuit |
US13/141,588 US8471632B2 (en) | 2008-12-24 | 2009-09-30 | Distortion compensation circuit |
EP09834595.2A EP2378659B1 (en) | 2008-12-24 | 2009-09-30 | Distortion compensation circuit |
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CN105227507B (zh) * | 2014-06-13 | 2019-08-02 | 中兴通讯股份有限公司 | 非线性系统失真校正装置及方法 |
KR101684176B1 (ko) * | 2015-10-05 | 2016-12-20 | 한밭대학교 산학협력단 | 샘플 반복을 이용한 디지털 전치왜곡 방법 및 그 장치 |
CA3002959C (en) * | 2015-11-09 | 2021-04-27 | Telefonaktiebolaget Lm Ericsson (Publ) | An amplifier circuit for compensating an output signal from a circuit |
US9900016B1 (en) * | 2017-05-05 | 2018-02-20 | Intel IP Corporation | Compensation of non-linearity at digital to analog converters |
US10873299B2 (en) * | 2019-03-27 | 2020-12-22 | Intel Corporation | Trans-impedance amplifier transfer function compensation |
US11271601B1 (en) | 2020-10-19 | 2022-03-08 | Honeywell International Inc. | Pre-distortion pattern recognition |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0879143A (ja) * | 1994-09-06 | 1996-03-22 | Hitachi Denshi Ltd | 無線機 |
JP2002009556A (ja) * | 2000-06-16 | 2002-01-11 | Sony Corp | 歪補償装置及び歪補償方法 |
JP2002082843A (ja) * | 2000-09-11 | 2002-03-22 | Matsushita Electric Ind Co Ltd | バースト転送制御回路及びバースト転送制御方法 |
JP2007248115A (ja) * | 2006-03-14 | 2007-09-27 | Yokogawa Electric Corp | 波形測定装置 |
JP2008295089A (ja) * | 2004-09-21 | 2008-12-04 | Hitachi Kokusai Electric Inc | 歪補償増幅装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3872726B2 (ja) * | 2002-06-12 | 2007-01-24 | 富士通株式会社 | 送信増幅器 |
DE10247034B3 (de) * | 2002-10-09 | 2004-02-19 | Siemens Ag | Verfahren zur adaptiven Vorverzerrung digitaler Rohdatenwerte und Vorrichtung zu dessen Durchführung |
US7577211B2 (en) * | 2004-03-01 | 2009-08-18 | Powerwave Technologies, Inc. | Digital predistortion system and method for linearizing an RF power amplifier with nonlinear gain characteristics and memory effects |
GB2415308A (en) * | 2004-06-18 | 2005-12-21 | Filtronic Plc | Memory effect predistortion for a transmit power amplifier in a telecommunications system |
JP4492246B2 (ja) * | 2004-08-02 | 2010-06-30 | 富士通株式会社 | 歪み補償装置 |
CN100589321C (zh) * | 2008-03-28 | 2010-02-10 | 中兴通讯股份有限公司 | 一种实现数字预失真的装置和方法 |
US7737779B2 (en) * | 2008-08-29 | 2010-06-15 | Xilinx, Inc. | Method of and circuit for reducing distortion in a power amplifier |
-
2008
- 2008-12-24 JP JP2008327917A patent/JP2010154042A/ja active Pending
-
2009
- 2009-09-30 BR BRPI0923977A patent/BRPI0923977A2/pt not_active Application Discontinuation
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- 2009-09-30 RU RU2011129994/08A patent/RU2011129994A/ru not_active Application Discontinuation
- 2009-09-30 KR KR1020117016618A patent/KR101602004B1/ko active IP Right Grant
- 2009-09-30 CN CN200980152108.XA patent/CN102265507B/zh not_active Expired - Fee Related
- 2009-10-19 TW TW098135213A patent/TW201025832A/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0879143A (ja) * | 1994-09-06 | 1996-03-22 | Hitachi Denshi Ltd | 無線機 |
JP2002009556A (ja) * | 2000-06-16 | 2002-01-11 | Sony Corp | 歪補償装置及び歪補償方法 |
JP2002082843A (ja) * | 2000-09-11 | 2002-03-22 | Matsushita Electric Ind Co Ltd | バースト転送制御回路及びバースト転送制御方法 |
JP2008295089A (ja) * | 2004-09-21 | 2008-12-04 | Hitachi Kokusai Electric Inc | 歪補償増幅装置 |
JP2007248115A (ja) * | 2006-03-14 | 2007-09-27 | Yokogawa Electric Corp | 波形測定装置 |
Non-Patent Citations (2)
Title |
---|
LEI DING ET AL.: "A robust digital baseband predistorter constructed using memory polynomials", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 52, no. 1, January 2004 (2004-01-01), pages 159 - 165, XP011106847 * |
LEI DING: "Digital predistortion of power amplifiers for wireless application", March 2004, GEORGIA INSTITUTE OF TECHNOLOGY |
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BRPI0923977A2 (pt) | 2016-01-19 |
KR20110099132A (ko) | 2011-09-06 |
US20110254623A1 (en) | 2011-10-20 |
RU2011129994A (ru) | 2013-01-27 |
EP2378659B1 (en) | 2019-01-09 |
CN102265507B (zh) | 2014-04-16 |
CN102265507A (zh) | 2011-11-30 |
KR101602004B1 (ko) | 2016-03-17 |
CA2748191A1 (en) | 2010-07-01 |
EP2378659A1 (en) | 2011-10-19 |
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