WO2010058595A1 - Composant électronique pour câblage et son procédé de fabrication, et boîtier de dispositif électronique avec composant électronique intégré pour câblage et son procédé de fabrication - Google Patents

Composant électronique pour câblage et son procédé de fabrication, et boîtier de dispositif électronique avec composant électronique intégré pour câblage et son procédé de fabrication Download PDF

Info

Publication number
WO2010058595A1
WO2010058595A1 PCT/JP2009/006267 JP2009006267W WO2010058595A1 WO 2010058595 A1 WO2010058595 A1 WO 2010058595A1 JP 2009006267 W JP2009006267 W JP 2009006267W WO 2010058595 A1 WO2010058595 A1 WO 2010058595A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
metal layer
thin film
electronic component
lower metal
Prior art date
Application number
PCT/JP2009/006267
Other languages
English (en)
Japanese (ja)
Inventor
政道 石原
中川　宏史
Original Assignee
国立大学法人九州工業大学
九州日立マクセル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 国立大学法人九州工業大学, 九州日立マクセル株式会社 filed Critical 国立大学法人九州工業大学
Publication of WO2010058595A1 publication Critical patent/WO2010058595A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention porte sur un composant électronique pour câblage qui est utilisé tout en étant intégré à l'intérieur d'un boîtier de dispositif électronique, dans lequel un élément de circuit comprenant une puce semi-conductrice est disposé et dans lequel une section de câblage horizontale et une section de câblage verticale, qui sont connectées à l'élément de circuit et à une électrode externe, sont présentes. Une section de support comprend une plaque de support et une bande en film mince fixée à la plaque de support. La section de câblage horizontale, avec une structure à deux couches comprenant une couche métallique inférieure et une couche métallique supérieure fonctionnant en tant que masque pour former un motif sur la couche métallique inférieure, est formée sur la bande en film mince. La section de câblage verticale connectée à la couche métallique supérieure est formée par électroplacage.
PCT/JP2009/006267 2008-11-21 2009-11-20 Composant électronique pour câblage et son procédé de fabrication, et boîtier de dispositif électronique avec composant électronique intégré pour câblage et son procédé de fabrication WO2010058595A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-297474 2008-11-21
JP2008297474A JP2010123821A (ja) 2008-11-21 2008-11-21 配線用電子部品及びその製造方法、並びに該配線用電子部品を組み込んで用いる電子デバイスパッケージ及びその製造方法

Publications (1)

Publication Number Publication Date
WO2010058595A1 true WO2010058595A1 (fr) 2010-05-27

Family

ID=42198038

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/006267 WO2010058595A1 (fr) 2008-11-21 2009-11-20 Composant électronique pour câblage et son procédé de fabrication, et boîtier de dispositif électronique avec composant électronique intégré pour câblage et son procédé de fabrication

Country Status (3)

Country Link
JP (1) JP2010123821A (fr)
TW (1) TW201029122A (fr)
WO (1) WO2010058595A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6495692B2 (ja) * 2015-03-11 2019-04-03 東芝メモリ株式会社 半導体装置及びその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1145955A (ja) * 1997-07-28 1999-02-16 Kyocera Corp 素子内蔵多層配線基板およびその製造方法
JP2007158193A (ja) * 2005-12-07 2007-06-21 Matsushita Electric Ind Co Ltd 電子部品実装用基板、電子部品モジュール、電子部品実装構造体及びこれらの製造方法
JP2008235378A (ja) * 2007-03-16 2008-10-02 Nec Corp 金属ポストを有する配線基板、半導体装置及び製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5017271A (en) * 1990-08-24 1991-05-21 Gould Inc. Method for printed circuit board pattern making using selectively etchable metal layers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1145955A (ja) * 1997-07-28 1999-02-16 Kyocera Corp 素子内蔵多層配線基板およびその製造方法
JP2007158193A (ja) * 2005-12-07 2007-06-21 Matsushita Electric Ind Co Ltd 電子部品実装用基板、電子部品モジュール、電子部品実装構造体及びこれらの製造方法
JP2008235378A (ja) * 2007-03-16 2008-10-02 Nec Corp 金属ポストを有する配線基板、半導体装置及び製造方法

Also Published As

Publication number Publication date
TW201029122A (en) 2010-08-01
JP2010123821A (ja) 2010-06-03

Similar Documents

Publication Publication Date Title
KR101150322B1 (ko) 반도체 칩 패키지 및 그 제조 방법
KR101193416B1 (ko) 3차원 실장 반도체 장치 및 그의 제조 방법
JP4274290B2 (ja) 両面電極構造の半導体装置の製造方法
JP2019512168A (ja) シリコン基板に埋め込まれたファンアウト型の３ｄパッケージ構造
TWI316749B (en) Semiconductor package and fabrication method thereof
WO2009123048A1 (fr) Composant électronique utilisé pour le câblage et son procédé de fabrication
KR101195786B1 (ko) 칩 사이즈 양면 접속 패키지의 제조 방법
JP2005506678A (ja) 集積型ヒートシンク及びビルドアップ層を有する超小型電子パッケージ
KR20070101094A (ko) 전자 장치용 기판 및 그 제조 방법, 및 전자 장치 및 그제조 방법
US20130127004A1 (en) Image Sensor Module Package and Manufacturing Method Thereof
JP2009070882A (ja) 半導体チップパッケージ及びその製造方法
JP5665020B2 (ja) 配線用電子部品の製造方法
JP2010245157A (ja) 配線用部品及びその製造方法、並びに該配線用部品を組み込んで用いる電子デバイスパッケージ及びその製造方法
JP3732378B2 (ja) 半導体装置の製造方法
WO2010058595A1 (fr) Composant électronique pour câblage et son procédé de fabrication, et boîtier de dispositif électronique avec composant électronique intégré pour câblage et son procédé de fabrication
JPH0864635A (ja) 半導体装置
JP5429890B2 (ja) 配線用電子部品及びその製造方法、並びに該配線用電子部品を組み込んで用いる電子デバイスパッケージ及びその製造方法
JP5491722B2 (ja) 半導体装置パッケージ構造及びその製造方法
JP2009021267A (ja) 外部接続用電極を配置した半導体装置及びその製造方法
JP2010161101A (ja) 配線用電子部品及びその製造方法、並びに該配線用電子部品を組み込んで用いる電子デバイスパッケージ及びその製造方法
JP5982414B2 (ja) 半導体装置パッケージ構造及びその製造方法
KR20130027870A (ko) 패키지 기판 및 패키지의 제조 방법
JP2009059771A (ja) ウエハレベルチップサイズパッケージ及びその製造方法
CN107170715B (zh) 半导体封装结构及其制作方法
TW201021183A (en) Packaging substrate and method for manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09827376

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09827376

Country of ref document: EP

Kind code of ref document: A1