JP5491722B2 - 半導体装置パッケージ構造及びその製造方法 - Google Patents
半導体装置パッケージ構造及びその製造方法 Download PDFInfo
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- JP5491722B2 JP5491722B2 JP2008292360A JP2008292360A JP5491722B2 JP 5491722 B2 JP5491722 B2 JP 5491722B2 JP 2008292360 A JP2008292360 A JP 2008292360A JP 2008292360 A JP2008292360 A JP 2008292360A JP 5491722 B2 JP5491722 B2 JP 5491722B2
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- 239000004065 semiconductor Substances 0.000 title claims description 66
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- 239000002923 metal particle Substances 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
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- 229910052710 silicon Inorganic materials 0.000 claims description 4
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- 239000010409 thin film Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
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- 239000002356 single layer Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
Claims (9)
- 半導体装置パッケージ構造であって、該半導体装置パッケージ構造は、半導体基板上の配線層に接続される回路素子を、半導体基板上に配置して樹脂封止すると共に、該配線層を介して該回路素子に接続される外部接続用電極を該半導体装置パッケージ構造のおもて面に配置するものであり、
上面と、該上面とは反対側の下面と、該上面に配置された前記外部接続用電極と、該下面に配置された配線パターンと、前記外部接続用電極と該配線パターンとを接続するための開口とを有するテープと、
前記テープの前記下面に形成された内部接続用電極構造体であって、該内部接続用電極構造体は前記配線パターン及び前記配線パターンに接続された内部接続用電極を複数個一体に結合し、前記半導体基板上の前記配線層に接続されるものである、内部接続用電極構造体と、
前記テープの前記下面と前記半導体基板の上面との間に形成される樹脂封止層と
を備え、
前記テープは最初に支持板に貼り付けられて前記内部接続用電極構造体が前記テープの前記下面に形成され、前記樹脂封止層が形成された後に前記支持板を剥離して前記テープの前記上面を露出させ、前記テープは保護膜として用いられ、前記テープの前記開口は該保護膜に穴を空けて設けられ、前記外部接続用電極は前記開口により露出した前記配線パターンに接続されるものである半導体装置パッケージ構造。 - 前記半導体基板は多層有機基板であり、この多層有機基板を貫通するスルーホール内部の導体層を介して前記配線層に接続される裏面外部接続用電極を多層有機基板の裏面に形成した請求項1に記載の半導体装置パッケージ構造。
- 前記支持板は、板状のシリコン基板、ガラス、又はステンレス板である請求項1に記載の半導体装置パッケージ構造。
- 前記テープは、薄膜フィルムの絶縁基材である請求項1に記載の半導体装置パッケージ構造。
- 前記絶縁基材テープは、所定の温度で剥離する材料、又は紫外線照射で剥離する材料の接着剤を用いて、前記支持板に貼り付けられる請求項4に記載の半導体装置パッケージ構造。
- 半導体基板上の配線層に接続される回路素子を、半導体基板上に配置して樹脂封止すると共に、該配線層を介して該回路素子に接続される外部接続用電極をおもて面に配置した半導体装置パッケージ構造の製造方法において、
支持板と該支持板に貼り付けたテープからなる2層構成の支持部に配線パターン及び該配線パターンに接続された内部接続用電極を複数個一体に結合した内部接続用電極構造体を備え、
該内部接続用電極構造体の内部接続用電極を、前記半導体基板上の配線層に接続して、該半導体基板上面を前記支持部のテープ下面まで樹脂封止した後、前記支持部の支持板を剥離し、
支持板の剥離により露出したテープを、保護膜として用い、かつ、この保護膜に穴を空け、開口により露出した配線パターンと接続される外部接続用電極を形成した半導体装置パッケージ構造の製造方法。 - 前記支持部のテープ上に形成される配線パターンは、テープ上の全面に配線パターンとなるべき所定の抵抗の金属膜を蒸着あるいは貼り付け、或いはテープと金属膜を一体化したものを用いて、リソグラフィにより形成される請求項6に記載の半導体装置パッケージ構造の製造方法。
- 前記支持部のテープ上に形成される配線パターンは、ナノ金属粒子を用いてインクジェット方式又はスクリーン印刷方式により、直接パターンニングして形成される請求項6に記載の半導体装置パッケージ構造の製造方法。
- 前記配線パターンに接続される内部接続用電極は、形成した配線パターンを含む全面に、内部接続用電極形成用のレジストを塗布し、開口した開口部にめっきを施して、充填した後に、レジストを除去することにより形成する請求項7又は8に記載の半導体装置パッケージ構造の製造方法。
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JP2002158312A (ja) * | 2000-11-17 | 2002-05-31 | Oki Electric Ind Co Ltd | 3次元実装用半導体パッケージ、その製造方法、および半導体装置 |
JP3938921B2 (ja) * | 2003-07-30 | 2007-06-27 | Tdk株式会社 | 半導体ic内蔵モジュールの製造方法 |
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JP5205717B2 (ja) * | 2006-07-04 | 2013-06-05 | セイコーエプソン株式会社 | ギ酸銅錯体、銅粒子の製造方法および配線基板の製造方法 |
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