WO2010001515A1 - Dispositif d'arbitrage de bus et dispositif de navigation utilisant ce dernier - Google Patents

Dispositif d'arbitrage de bus et dispositif de navigation utilisant ce dernier Download PDF

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Publication number
WO2010001515A1
WO2010001515A1 PCT/JP2009/001842 JP2009001842W WO2010001515A1 WO 2010001515 A1 WO2010001515 A1 WO 2010001515A1 JP 2009001842 W JP2009001842 W JP 2009001842W WO 2010001515 A1 WO2010001515 A1 WO 2010001515A1
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Prior art keywords
bus
cpu
circuit
cpus
arbitration
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PCT/JP2009/001842
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English (en)
Japanese (ja)
Inventor
山田久典
小羽田哲宏
藤井慶司
北村典子
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三菱電機株式会社
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Priority to JP2010518882A priority Critical patent/JPWO2010001515A1/ja
Publication of WO2010001515A1 publication Critical patent/WO2010001515A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Definitions

  • the present invention relates to a bus arbitration device that arbitrates bus use requests of a plurality of CPUs (Central Processing Unit), and a navigation device using the bus arbitration device.
  • CPUs Central Processing Unit
  • I / O Input / Output
  • HDDs Hard Disk Drives
  • DVDs Digital Versatile Disks
  • memory cards etc. are common. These have a large-capacity storage function and are used for storing software, video, music, maps, and other various data, and greatly contribute to user convenience.
  • a write or read port mounted on the I / O device as described above is generally one port, and is connected to one CPU on a one-to-one basis.
  • FIG. 9 is a diagram showing a connection between a CPU and an I / O device in a conventional single port. As shown in FIG. 9, the CPU 100 and the I / O device 101 are connected one-to-one via the data bus 102 and the control line 103.
  • a flash memory 104 and a DRAM (Dynamic Random Access Memory) 105 are also arranged as a storage device for storing programs and data necessary for the CPU 100 to operate the components.
  • in-vehicle navigation devices in recent years are equipped with an HDD as a storage for storing music data and map data, and are further divided into a CPU for processing video and music data and a CPU for processing map data. is there.
  • an HDD as a storage for storing music data and map data
  • a CPU for processing map data is there.
  • I / O devices are generally single-port compatible on the premise of access from one CPU, and it is considered that simultaneous access from two or more CPUs is supported. It has not been.
  • I / O devices equipped with dual ports but they are expensive at present and cannot be used easily.
  • Patent Document 1 discloses a multi-CPU device that operates a single-port I / O device as if it were a dual-port I / O device. This device is provided with an arbitration circuit that arbitrates access from two CPUs to one I / O device using digital circuit technology.
  • the arbitration circuit determines that the one CPU is accessible, and the I / O device An access signal is generated at a timing that matches the specifications, and data reading and writing by the one CPU is executed. The same applies when an access signal is generated from the other CPU side.
  • the arbitration circuit When accesses by both CPUs overlap, the arbitration circuit outputs a wait signal to one of the CPUs and waits so that the two CPUs do not access the I / O device at the same time. is doing.
  • FIG. 10 is a diagram showing a configuration of a conventional multi-CPU device.
  • an LSI 106 is a dedicated LSI on which the above-described timing generation circuit is mounted, and is connected to the CPUs 100-1 and 100-2 and the HDD 101 via signal lines.
  • the LSI 106 captures all the bus signals from the CPUs 100-1 and 100-2. Therefore, as shown in FIG. 10, it is necessary to connect with a large number of signal lines for transmitting the bus signals, and unavoidably.
  • the substrate area increases.
  • navigation devices are capable of high-capacity high-speed data communication, and in addition to the original car navigation function, a processing function for handling multimedia information such as video and music has been added.
  • a processing function for handling multimedia information such as video and music has been added.
  • a configuration in which processing is shared using a plurality of CPUs is desired.
  • the present invention has been made to solve the above-described problems, and can be miniaturized with a simple configuration and uses a bus arbitration device that does not depend on the type, operation speed, or quantity of the CPU, and the same.
  • the object is to obtain a navigation device.
  • the bus arbitration device is a bus arbitration device that arbitrates bus use between two CPUs connected to a bus, and is a logical value indicating the state of assertion and negation of a bus use request signal input from the two CPUs.
  • a logic circuit that outputs a logical value indicating whether or not the bus can be used in accordance with a combination; and an inverter circuit that branches and inputs the output of the logic circuit to invert the logic.
  • an arbitration circuit unit that outputs a logical value indicating that the bus can be used is provided on a bus that connects the CPU and the access target device.
  • the exchange of the bus usable CPU and the access target device via the bus is relayed, and the bus unavailable In which and a gate portion for blocking PU from the bus.
  • a logic circuit that outputs a logic value indicating whether or not the bus can be used is output in accordance with a combination of logic values indicating the assertion of the bus use request signal and the negated state, and the output of the logic circuit is branched and input.
  • a logic value indicating that the bus can be used among the outputs of the logic circuit and the inverter circuit in the order in which the bus use request signals are asserted to a plurality of CPUs.
  • FIG. 6 is a timing chart of an access operation to an I / O device by a CPU. It is a figure which shows the structure of the arbitration circuit part of the bus arbitration apparatus by Embodiment 2 of this invention. It is a figure which shows the connection of CPU and I / O apparatus in the conventional single port. It is a figure which shows the structure of the conventional multi CPU apparatus.
  • FIG. 1 is a diagram showing a configuration of a bus arbitration device according to Embodiment 1 of the present invention, and takes as an example a case where an HDD, which is a typical device as an I / O device, is accessed from two CPUs.
  • CPUs 1 and 2 are provided with flash memories 4-1 and 4-2 and DRAMs 5-1 and 5-2, which are memories for storing programs and data necessary for each operation. ing.
  • the CPUs 1 and 2 have crystal oscillators 6-1 and 6-2 and reset ICs 7-1 and 7-2 that generate operation clock signals, respectively, and can operate at different operation clock frequencies.
  • the I / O device (access target device) 3 is an HDD accessed from the CPUs 1 and 2 (hereinafter referred to as HDD 3 as appropriate), and is equipped with an ATAPI (AT Attachment Packet Interface) standard bus I / F circuit. Yes.
  • the HDD 3 is connected to the external buses of the CPUs 1 and 2 that normally operate at a timing that matches the I / F standard, and reading or writing is executed by executing the programs of the CPUs 1 and 2.
  • the HDD 3 is a single-port storage device, and the CPUs 1 and 2 each access through one system bus line.
  • the bus arbitration device is provided between the two CPUs 1 and 2 and the I / O device 3, and requests to use the bus so as to be exclusively accessed from one CPU (CPU1 or CPU2). Mediate.
  • the configuration includes an arbitration circuit unit 8 and gate units 9-1 and 9-2.
  • the arbitration circuit unit 8 is a circuit unit that arbitrates access from the two CPUs 1 and 2 to the I / O device 3, and is connected to the CPU 1 through the two signal lines 10-1 and 11-1. It is connected to the CPU 2 via two signal lines 10-2 and 11-2.
  • the signal lines 10-1 and 10-2 are signal lines for transmitting a signal CPU_ACK for notifying the CPUs 1 and 2 of the availability of access (bus availability).
  • the signal lines 11-1 and 11-2 are signals for transmitting a signal CPU_REQ (bus use request signal) for requesting access to the I / O device 3 from the CPUs 1 and 2 (bus use request). .
  • the gate units 9-1 and 9-2 are gate ICs that receive the input of the signal CPU_ACK from the arbitration circuit unit 8 and connect or block the bus signal according to the signal CPU_ACK. For example, when the signal CPU1_ACK from the arbitration circuit unit 8 is asserted (accessible), the gate unit 9-1 connects the control line 12-1 and the data bus 13-1 to the HDD 3, and the signal CPU1_ACK is negated (accessed). If it is not possible, it will be blocked.
  • the control lines 12-1 and 12-2 are signal lines for transmitting control information from the CPUs 1 and 2, and the data buses 13-1 and 13-2 are exchanged between the CPUs 1 and 2 and the HDD 3. This is a signal line for transmitting data.
  • FIG. 2 is a diagram showing the configuration of the arbitration circuit unit in FIG.
  • the arbitration circuit unit 8 includes inverter circuits 14-1, 14-2, 17, NAND circuits 15-1, 15-2, and D-FF (Delay-Flip) which are, for example, 74 series logic ICs. Flop) 16.
  • the arbitration circuit unit 8 and the outside are connected by a total of four signal lines, signal lines 10-1 and 10-2 and signal lines 11-1 and 11-2.
  • the signal line 10-1 for transmitting the signal CPU1_ACK to the CPU 1 is connected to the output of the inverter circuit (inverter circuit) 17, and the signal line 10-2 for transmitting the signal CPU2_ACK to the CPU 2 is input to the inverter circuit 17. Connected to.
  • the signal line 11-1 for transmitting the signal CPU1_REQ from the CPU1 is connected to the inverting input of the inverter circuit 14-1 and the input of the NAND circuit 15-2.
  • the signal line 11-2 for transmitting the signal CPU2_REQ from the CPU 2 is connected to the inverting input of the inverter circuit 14-2 and the input of the NAND circuit 15-1.
  • the NAND circuit 15-1 has an input side connected to the output of the inverter circuit 14-1 and the signal line 11-2, and an output connected to the preset terminal PR of the D-FF16.
  • the NAND circuit 15-2 has an input side connected to the output of the inverter circuit 14-2 and the signal line 11-1, and an output connected to the clear terminal CL of the D-FF 16.
  • the D-FF (logic circuit) 16 is a flip-flop that holds a digital value input to an input terminal D (not shown) according to an operation clock signal input to a clock terminal CK (not shown).
  • the signal CPU_ACK is generated according to the values input to the terminal PR and the terminal CL without using the operation clock signal. Since the CPU operation clock signal is not used, the arbitration operation is not affected even if the CPUs 1 and 2 have different operation speeds.
  • the output terminal of the D-FF 16 is branched and connected to the input of the inverter circuit 17 and the signal line 10-2, and the output value of the D-FF 16 is on the signal line 10-2 as the signal CPU2_ACK.
  • the output value of the D-FF 16 transmitted and inverted by the inverter circuit 17 is transmitted as the signal CPU1_ACK on the signal line 10-1.
  • the input terminal D and the clock terminal CK are pulled up to a predetermined voltage value or pulled down.
  • the signal CPU_ACK can be asserted to either one of the CPUs 1 and 2 without collision of accesses by the CPUs 1 and 2. Therefore, after asserting the signal CPU_REQ, the CPUs 1 and 2 wait for the signal CPU_ACK to be asserted by the arbitration circuit unit 8, and start accessing the I / O device when the signal CPU_ACK is asserted.
  • FIG. 3 is a function table showing the relationship between the input / output of the arbitration circuit unit in FIG. 2 and the access right of the CPU, and shows the case where time elapses in the direction of the arrow in the table.
  • the arbitration circuit unit 8 asserts or negates the signal CPU_ACK to the CPUs 1 and 2 according to the combination of the values of the signals CPU_REQ from the CPUs 1 and 2 (logical values of high or low).
  • the access right to the / O device 3 is given.
  • the signals CPU_REQ and CPU_ACK define the low level (L) as asserted and the high level (H) as negated.
  • the terminal PR of the D-FF 16 becomes L level and the terminal CL becomes H level, so that the output of the D-FF 16 becomes H level and L level.
  • Signal CPU1_ACK and H level signal CPU2_ACK are immediately output. That is, access is permitted to the CPU 1.
  • both the signal CPU1_REQ and the signal CPU2_REQ are at the L level.
  • the output value of the D-FF 16 is maintained, and the L-level signal CPU1_ACK and the H-level signal CPU2_ACK are continuously output. Thereby, the access permission of the CPU 1 is maintained.
  • FIG. 4 is a diagram showing the configuration of the gate portion in FIG.
  • the gate units 9-1 and 9-2 can also be configured by buffer ICs 18, 19, and 20, which are 74 series general-purpose logic ICs, similarly to the arbitration circuit unit 8.
  • the buffer ICs 18, 19, and 20 are equipped with a terminal ENABLE, and determine whether the gate is on or off according to the level of the terminal ENABLE. Further, as the buffer ICs 18, 19 and 20, a three-state IC capable of setting the output terminal to high impedance when the gate is off is used.
  • the buffer IC 18 of the gate section 9-1 (or gate section 9-2) is connected to the CPU 1 (or CPU 2) via the data bus 13-1 (or data bus 13-2), and CPU1_ACK ( Alternatively, the data bus 13-1 (or data bus 13-2) is connected or disconnected according to the value of CPU2_ACK).
  • the buffer IC 19 in the gate unit 9-1 (or gate unit 9-2) transmits a control signal output from the CPU 1 (or CPU 2) to the I / O device 3 (or control line 12-1). -2) Connected via a control line (hereinafter referred to as a control line (output)), and the control line (output) is connected or disconnected according to the value of CPU1_ACK (or CPU2_ACK).
  • the buffer IC 20 of the gate unit 9-1 (or the gate unit 9-2) transmits a signal input from the I / O device 3 to the CPU 1 (or CPU 2), the control line 12-1 (or the control line 12- 2) Connection is made via a control line (hereinafter referred to as a control line (input)), and the control line (input) is connected or disconnected according to the value of CPU1_ACK (or CPU2_ACK).
  • FIG. 5 is a function table showing the input / output relationship of the gate part in FIG.
  • an L level (or H level) digital signal is input from the data bus 13-1 to the input terminal A, and an L level (asserted) signal CPU1_ACK is input to the terminal ENABLE.
  • the buffer IC 18 outputs the L-level (or H-level) output value Y, that is, the value transmitted through the data bus 13-1, to the I / O device 3 side as it is.
  • the buffer IC 18 receives an L level (or H level) digital signal from the data bus 13-1 to the input terminal A.
  • the output value Y is set to high impedance (Z), and the data bus 13-1 and the I / O device 3 are disconnected.
  • the buffer ICs of the gate units 9-1 and 9-2 input the signal CPU_ACK output from the arbitration circuit unit 8 to the terminal ENABLE, thereby connecting the data bus and the control line to the CPUs 1 and 2. It can be connected or disconnected, and signal line collision can be avoided.
  • FIG. 6 is a diagram showing an example of the sequence of the arbitration operation according to the first embodiment, and shows a case where the CPU 1 makes a request prior to the CPU 2 shown in FIG.
  • the CPU 1 asserts the signal CPU1_REQ (L level), and requests the arbitration circuit unit 8 for the access right to the I / O device 3 (step ST1).
  • the arbitration circuit unit 8 receives the signal CPU1_REQ from the CPU 1 via the signal line 10-1, if the signal CPU1_ACK is not at the L level at this time, the CPU 1 has no access permission, so the CPU 1 enters a waiting state (step S1). ST2).
  • the signal CPU2_REQ is asserted (L level), and the arbitration circuit unit 8 is requested to access the I / O device 3 (step ST1a).
  • the arbitration circuit unit 8 inputs the signal CPU2_REQ from the CPU 2 via the signal line 10-2, if the signal CPU2_ACK is not at the L level at this time, the CPU 2 is not permitted to access, so the CPU 2 enters a waiting state. (Step ST2a).
  • the CPU 1 When reading or writing to the I / O device 3 is completed, the CPU 1 negates (H level) the signal CPU1_REQ (step ST4).
  • the arbitration circuit unit 8 when an H-level signal CPU1_REQ is input from the CPU 1 via the signal line 10-1, the signal CPU2_ACK immediately becomes L level.
  • the gate unit 9-2 connects the control line 12-2 and the data bus 13-2, and the CPU 2 can execute reading or writing with respect to the I / O device 3 (step ST3a).
  • the CPU 2 negates (H level) the signal CPU2_REQ (step ST4a).
  • the arbitration circuit unit 8 sets the signal CPU2_ACK to the L level and Allow immediate access.
  • signal CPU 2 _REQ is at H level when CPU 1 sets signal CPU 1 REQ to L level.
  • the arbitration circuit unit 8 sets the signal CPU1_ACK to the L level and permits access.
  • the arbitration circuit unit 8 sets the signal CPU1_ACK to the L level again when the signal CPU2_REQ is at the H level. Allow access to. Similarly, even when the CPU 2 makes a request again after making a request (CPU 2 request ⁇ CPU 2 request), the CPU 2 is permitted to access (see FIG. 7C).
  • the arbitration circuit unit 8 detects that the signal CPU1_REQ is at the L level, Even when the CPU2_REQ becomes L level, the L level of the signal CPU1_ACK is maintained, and the signal CPU2_ACK is not set to L level. For this reason, the CPU 2 waits for access, but as soon as the signal CPU1_REQ goes to H level, the signal CPU2_ACK goes to L level and the CPU 2 access is permitted.
  • the arbitration circuit unit 8 determines that the signal CPU2_REQ is at the L level. For example, even if the signal CPU1_REQ subsequently becomes L level, the L level of the signal CPU2_ACK is maintained, and the access to the CPU 1 is permitted when the signal CPU2_REQ is negated.
  • the arbitration circuit unit 8 immediately gives an acknowledgment to the requesting CPU, and even when the requests overlap, the arbitration circuit unit 8 has requested the request first.
  • the circuit configuration is such that an acknowledge is given to the CPU, the other CPU is made to wait, and after the access process of the CPU requested previously is completed, an acknowledge is given to the other CPU. With this circuit configuration, it is possible to minimize waiting time in arbitration between the CPUs 1 and 2 without performing complicated timing processing.
  • the signal CPU_REQ can be realized by setting the general-purpose output port OUTPUT of the CPU to high or low.
  • the signal CPU_ACK can be realized by inputting the general-purpose input port INPUT of the CPU and confirming the polarity of the input port by polling. However, when the processing is more urgent, the interrupt port of the CPU is input and the interrupt is performed. Acknowledgment confirmation may be performed based on an interrupt event that occurs in response to a change in port polarity.
  • the processing can be performed at a higher speed.
  • the signal CPU_REQ of the other CPU is L level.
  • the signal CPU_ACK can be set to L level with a delay time of several nanoseconds. This time difference is one cycle or less in the CPU processing cycle, and the influence on other processing operations can be almost ignored.
  • the signal CPU_REQ and the signal CPU_ACK can be realized by changing the level of the general-purpose output port OUTPUT, input port INPUT, or interrupt port installed in the CPU. Therefore, in the multi-CPU system, the bus arbitration device according to the present invention can be incorporated regardless of the type of CPU.
  • the HDD has been described as an example of the I / O device 3, the present invention is not limited to this.
  • a general-purpose memory card such as a DVD playback device, a CF (Compact Flash) card, or an SD card may be used. Further, it can be used even with a device equipped with a PCI bus or a special dedicated bus, and can also be applied to a serial bus type I / F.
  • the bus arbitration device of the present invention can be effectively applied to a navigation device equipped with a plurality of CPUs and capable of processing by multiple CPUs.
  • a navigation device equipped with a multimedia data CPU that processes video, music data, and the like and a navigation CPU that processes map data and the like. That is, in the configuration shown in FIG. 1, the CPU 1 and 2 can be provided with a multimedia data CPU and a navigation CPU, and an HDD or the like for storing data necessary for the processing of these CPUs can be realized as the I / O device 3. It is.
  • the bus arbitration device of the present invention By applying the bus arbitration device of the present invention to such a navigation device, even if the multimedia data CPU and the navigation CPU access one I / O device (for example, HDD), the bus Processing is possible without contention.
  • the board area can be reduced with a simple configuration having a small circuit scale combined with a general-purpose logic IC, and the navigation apparatus itself can be downsized.
  • the bus arbitration device of the present invention does not require a CPU operation clock signal in the arbitration operation, and can exchange signals via a standardized general-purpose port regardless of the CPU type, such as a navigation device. It can be easily applied to other devices.
  • the logical value indicating whether the bus can be used is output and the assertion state of the signal CPU_REQ D-FF 16 that maintains the previous output value when a plurality of logical values indicating the same are input simultaneously, and an inverter circuit 17 that branches and inputs the output of the D-FF 16 to invert the logic.
  • a logical value indicating that the bus can be used is output from the outputs of the D-FF 16 and the inverter circuit 17, and when the bus usage requests of the CPUs 1 and 2 overlap, Until the signal CPU_REQ is negated with respect to the CPU that previously asserted the signal CPU_REQ. And it outputs a logic value indicating a scan usable.
  • the arbitration operation by the arbitration circuit unit 8 does not depend on the operation clock signal of the CPU, and only the input of the signal CPU_REQ and the output of the signal CPU_ACK are required.
  • a general-purpose port of the CPU can be used.
  • the present invention can be easily applied to multi-CPU devices without being limited by the CPU type or operation speed.
  • Embodiment 2 shows a configuration in which the bus arbitration of three or more CPUs is performed.
  • FIG. 8 is a diagram showing a configuration of an arbitration circuit unit of the bus arbitration device according to the second embodiment of the present invention, and shows a circuit configuration for performing bus arbitration of four CPUs 1 to 4. 8 also includes inverter circuits 14-1 to 14-6, 17-1 to 17-3, NAND circuits 15-1 to 15-6, D-FF 16-1 to 16-3 and NOR circuits 21-1, 21-2, 22-1 to 22-4.
  • the arbitration circuit unit 8 and the outside are connected by a total of eight signal lines including four signal lines that transmit the signal CPU_REQ and four signal lines that transmit the signal CPU_ACK.
  • a first configuration section including inverter circuits 14-1, 14-2, 17-1, NAND circuits 15-1, 15-2 and D-FF 16-1, inverter circuit 14-3, 14-4 and 17-2, NAND circuits 15-3 and 15-4, and a second configuration section (arbitration circuit section) composed of D-FF 16-2, inverter circuits 14-5, 14-6, and 17- 3.
  • the third configuration section composed of NAND circuits 15-5 and 15-6 and D-FF 16-3 operates in the same manner as the configuration shown in FIG. 2 of the first embodiment. To do.
  • the NOR circuit 21-1 inverts the signal CPU_REQ from the CPUs 1 and 2
  • the NOR circuit 21-2 inverts the signal CPU_REQ from the CPUs 3 and 4.
  • the NOR circuits 21-1 and 21-2 output values corresponding to the signals to the inverter circuits 14-3 and 14-4 and the NAND circuits 15-3 and 15-4. .
  • the NOR circuits (output selection units) 22-1 and 22-2 receive the respective output values in the first configuration unit and the output values via the inverter circuit 17-2 in the second configuration unit.
  • Output selection units) 22-3 and 22-4 receive the respective output values in the third configuration unit and the output values of the D-FF 16-2 in the second configuration unit. With this connection relationship, the NOR circuits 22-1 to 22-4 generate signals CPU_ACK to the CPUs 1 to 4 according to the output values of the first to third components.
  • the D-FFs 16-1 to 16-3 do not use the operation clock signal but use the output value corresponding to the values input to the terminal PR and the terminal CL. Therefore, even if the CPUs 1 to 4 have different operation speeds, the arbitration operation is not affected.
  • CPU1 request ⁇ CPU2 to 4 request
  • the arbitration circuit unit 8 indicates that the signals CPU2_REQ to CPU4_REQ are at H level when the CPU1 sets the signal CPU1_REQ to L level. Sets the signal CPU1_ACK to the L level and immediately allows the CPU1 to access.
  • the D-FF 16-1 in the first configuration unit outputs an H level signal
  • the D-FF 16 in the third configuration unit. -3 maintains the previous output level.
  • the second component receives an L level signal from the NOR circuit 21-1 and an H level signal from the NOR circuit 21-2, and the D-FF 16-2 outputs an H level signal.
  • the NOR circuit 22-1 inverts and inputs the L level signal from the inverter circuit 17-1 in the first component and the L level signal from the inverter circuit 17-2 in the second component.
  • the signal CPU1_ACK is generated and output.
  • the NOR circuit 22-2 inverts the H level signal from the D-FF 16-1 in the first component and the L level signal from the inverter circuit 17-2 in the second component, An H level signal CPU2_ACK is generated and output.
  • the NOR circuit 22-3 inverts the L level or H level signal from the inverter circuit 17-3 in the third component and the H level signal from the D-FF 16-2 in the second component. Input, generate and output H level signal CPU3_ACK. Similarly, the NOR circuit 22-4 outputs an L level or H level signal from the D-FF 16-3 in the third component and an H level signal from the D-FF 16-2 in the second component. Inverted input generates and outputs an H level signal CPU4_ACK. Thereby, access is permitted only to CPU1.
  • the arbitration circuit unit 8 When the CPU 1 completes the access process to the I / O device 3 and negates the signal CPU1_REQ, the arbitration circuit unit 8 in the order of asserting the signal CPU_REQ (L level) among the CPUs 2 to 4 , The signal CPU_ACK is set to L level to permit access.
  • CPU1 request ⁇ CPU1 request
  • signals CPU2_REQ to CPU4_REQ are at H level when CPU1 sets signal CPU1_REQ to L level
  • arbitration circuit unit 8 CPU1_ACK is set to L level and access is permitted. The same applies to CPUs 2-4.
  • the arbitration circuit unit 8 determines that if the signal CPU1_REQ is at L level, any of the signals CPU2_REQ to CPU4_REQ is at L level subsequently.
  • the signal CPU1_ACK is maintained at the L level, and the signals CPU2_ACK to CPU4_ACK are not set to the L level. For this reason, access of the CPUs 2 to 4 is awaited, but when the signal CPU1_REQ becomes H level, the signal CPU_ACK of the CPUs 2 to 4 is set to L level in the order of requests and access is permitted.
  • the case where the number of CPUs is four is shown. However, when the number of CPUs is three, the first configuration unit and the second configuration unit described above are provided, and the D-FF 16-2 in the second configuration unit is provided. May be the signal CPU3_ACK. In the case of n (5 or more), the first to (n-1) th components are provided, and the NOR circuit that generates the signal CPU_ACK for each CPU is connected as in FIG. Can do.
  • a logical value indicating whether or not a bus can be used is output according to a combination of logical values indicating the assertion and negation states of the signal CPU_REQ, and the signal CPU_REQ is asserted.
  • D-FFs 16-1 to 16-3 that maintain the previous output value when a plurality of logical values indicating the same are input simultaneously, and inverter circuits that branch-input the outputs of D-FFs 16-1 to 16-3 and invert the logic First to third components having 17-1 to 17-3, and output values of D-FFs 16-1 to 16-3 and inverter circuits 17-1 to 17-3 of the first to third components Accordingly, the logic indicating that the bus can be used among the outputs of the D-FFs 16-1 to 16-3 and the inverter circuits 17-1 to 17-3 in order of asserting the signal CPU_REQ to the CPUs 1 to 4.
  • the previous output value maintained in the D-FFs 16-1 to 16-3 is used for the CPU that previously asserted the signal CPU_REQ.
  • Arbitration circuit unit provided on the NOR circuits 22-1 to 22-4 for outputting logical values indicating that the bus can be used until the signal CPU_REQ is negated, and the buses connecting the CPUs 1 to 4 and the I / O device 3.
  • the gate units 9-1 and 9-2 that relay the exchange between the bus-usable CPU and the I / O device 3 via the bus and block the unusable CPU from the bus; Is provided.
  • the present invention is not limited to the D-FF. That is, any circuit that outputs and maintains the same digital value as that of the D-FF according to each of the two input digital values without using the CPU clock signal may be used.
  • the bus arbitration device can be reduced in size with a simple configuration, and is connected to the bus in order to obtain a bus arbitration device that does not depend on the CPU type, operation speed, and quantity.
  • a bus arbitration device that arbitrates bus use between two CPUs a logical value indicating whether or not the bus can be used is set in accordance with a combination of logical values indicating assertion and negation of a bus use request signal input from the two CPUs.
  • the output value of a road part it comprised so that the exchange of the bus-usable CPU and the said access object apparatus via the said bus could be relayed, and the gate part which interrupted

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  • Bus Control (AREA)

Abstract

La présente invention concerne un dispositif d'arbitrage de bus comprenant : un D-FF (16) pour délivrer en sortie une valeur logique indiquant la disponibilité d'un bus sur la base d'une combinaison des valeurs logiques indiquant les états de signaux CPU_REQ et, lorsque les signaux CPU_REQ sont certifiés simultanément par des CPU (1, 2), maintenir une valeur de sortie précédente ; et un circuit inverseur (17) pour inverser logiquement la sortie du D-FF (16). Le dispositif d'arbitrage de bus délivre en sortie, parmi les sorties du D-FF (16) et du circuit inverseur (17), une valeur logique indiquant que le bus est disponible pour les CPU (1, 2) dans l'ordre dans lequel les signaux CPU_REQ ont été certifiés. Lorsque les requêtes d'utilisation du bus des CPU (1, 2) se chevauchent, le dispositif d'arbitrage de bus continue de délivrer en sortie, en utilisant la valeur de sortie précédente maintenue dans le D-FF (16), la valeur logique indiquant que le bus est disponible pour la CPU (1 ou 2) qui a certifié la première le signal CPU_REQ jusqu'à ce que ce signal soit nié.
PCT/JP2009/001842 2008-07-04 2009-04-22 Dispositif d'arbitrage de bus et dispositif de navigation utilisant ce dernier WO2010001515A1 (fr)

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JP2010518882A JPWO2010001515A1 (ja) 2008-07-04 2009-04-22 バス調停装置及びこれを用いたナビゲーション装置

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JP2008175682 2008-07-04
JP2008-175682 2008-07-04

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109947019A (zh) * 2019-03-27 2019-06-28 中国铁道科学研究院集团有限公司 列车网络输入输出系统的处理装置及并行工作控制方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63132365A (ja) * 1986-11-22 1988-06-04 Nec Corp バス調停制御方式
JPS6476254A (en) * 1987-09-18 1989-03-22 Fujitsu Ltd Device for arbitrating bus
JPH01193959A (ja) * 1988-01-28 1989-08-03 Toshiba Corp 共通バス調停回路
JPH02141858A (ja) * 1988-11-22 1990-05-31 Victor Co Of Japan Ltd Ｄｍａコントローラ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413660A (en) * 1987-07-07 1989-01-18 Toyota Central Res & Dev Bus arbiter
JPH01211060A (ja) * 1988-02-18 1989-08-24 Yokogawa Electric Corp アクセス制御権調停回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63132365A (ja) * 1986-11-22 1988-06-04 Nec Corp バス調停制御方式
JPS6476254A (en) * 1987-09-18 1989-03-22 Fujitsu Ltd Device for arbitrating bus
JPH01193959A (ja) * 1988-01-28 1989-08-03 Toshiba Corp 共通バス調停回路
JPH02141858A (ja) * 1988-11-22 1990-05-31 Victor Co Of Japan Ltd Ｄｍａコントローラ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109947019A (zh) * 2019-03-27 2019-06-28 中国铁道科学研究院集团有限公司 列车网络输入输出系统的处理装置及并行工作控制方法

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