WO2009141848A1 - パターン発生器およびそれを用いたメモリの試験装置 - Google Patents
パターン発生器およびそれを用いたメモリの試験装置 Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
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- the present invention relates to a pattern generator used in a memory testing apparatus.
- a DRAM (Dynamic Random Access Memory) having a multi-bank configuration is used as a main storage device of an electronic computer such as a personal computer or a workstation.
- a DRAM having a multi-bank configuration enables high-speed data transfer by transferring data in each bank in order with a small latency and without interruption.
- a bank address specifying a bank and a row address (row address) specified for each bank are applied to the memory, and then a column address (column address) is further applied. It is necessary to specify an access destination cell and perform data access such as reading and writing.
- a memory is accessed by applying a row address to each bank while sequentially switching a plurality of banks. After that, returning to the first bank, while switching a plurality of banks again, the same row address as before is applied to each bank to perform memory access.
- the row address is generated by the pattern generator, but it is useless to repeatedly generate the same row address.
- the address save / load circuit saves the row address once given to each bank to the memory (referred to as row address memory), and loads and uses the row address the next time the same row address in the same bank is accessed. To do. JP 2000-123597 A International Publication No. 2004/113941 Pamphlet
- the user When testing a memory under test using a test apparatus having an address save / load function, the user needs to program a pattern program according to the test contents.
- the user needs to save the row address in the row address memory of the address save / load circuit and generate an address to be used when loading the row address separately from the address for the memory under test. That is, since the generation of an address that is not directly related to access to the memory under test must be described in the pattern program, there is a problem that programming becomes complicated.
- the present invention has been made in view of such problems, and one of its purposes is to provide a pattern generator that can be controlled by a simpler pattern program than before.
- An embodiment of the present invention relates to a pattern generator mounted on a test apparatus that inspects a memory under test having a multi-bank configuration.
- the pattern generator includes an address arithmetic circuit that generates a row address indicating an access destination of the memory under test, and a row address memory that stores the row address generated by the address arithmetic circuit for each bank.
- the pattern generator includes a bank address to be applied to the memory under test, reads a memory control signal generated by a program, a save address when writing the row address to the row address memory, and a row address from the row address memory Used as the load address when
- the bank address is used as an address signal when accessing the row address memory, it is not necessary to describe generation of an address signal for the row address memory by the pattern program, so that programming can be simplified. The burden on the user of the test apparatus can be reduced.
- a pattern generator is a control signal for setting a burst length when accessing a memory, receives a control signal generated by a program, and reads out from the row address memory for a period corresponding to the burst length.
- An output holding circuit for holding the row address may be further provided.
- the row address is read from the row address memory by the load instruction at the start of the burst transfer, the row address is held for the necessary cycle by the output holding circuit thereafter. Since it is not necessary to describe a load instruction for each, the burden of programming can be further reduced.
- the address arithmetic circuit may be configured to be able to generate a save address and a load address for the row address memory in addition to the row address.
- the pattern generator selects either a memory control signal or a save address generated by the address arithmetic circuit, and outputs a write address setting unit for outputting a row address to the row address memory, and a memory control signal And a read address setting unit that selects one of the load addresses generated by the address arithmetic circuit and outputs it as an address when the row address is read from the row address memory.
- the pattern generator further includes a data setting unit that selects either a row address generated by the address arithmetic circuit or a row address generated according to a program, and outputs the selected data signal as a data signal to be written to the memory for the row address. You may prepare.
- the pattern generator may further include an output selection circuit that selects either the row address read from the row address memory or the row address generated by the address arithmetic circuit.
- Another embodiment of the present invention is a memory testing apparatus.
- This apparatus includes one of the pattern generators described above. According to this test apparatus, the burden on the user when programming the pattern program can be reduced.
- the pattern generator can be controlled with a simpler pattern program than before.
- DESCRIPTION OF SYMBOLS 100 ... Test apparatus, 102 ... Timing generator, 104 ... Pattern generator, 106 ... Waveform shaper, 108 ... Write driver, 110 ... Comparator, 112 ... Logic comparison part, 200 ... DUT, 2 ... Address save load circuit, 10 DESCRIPTION OF SYMBOLS: Address calculation circuit, 12 ... Row address memory, 14 ... Data setting circuit, 16 ... Write address setting circuit, 18 ... Read address setting circuit, 20 ... Output selection circuit, 22 ... Output holding circuit.
- FIG. 1 is a block diagram showing an overall configuration of a test apparatus 100 according to an embodiment.
- the test apparatus 100 has a function of determining the quality of the DUT 200 or specifying a defective portion.
- the DUT 200 is a memory (RAM) having a multi-bank configuration and further has a burst transfer function.
- the test apparatus 100 includes a timing generator 102, a pattern generator 104, a waveform shaper 106, a write driver 108, a comparator 110, and a logic comparison unit 112.
- the pattern generator 104 generates a timing set signal (hereinafter referred to as “TS signal”) and supplies it to the timing generator 102.
- the timing generator 102 generates a periodic clock CKp and a delay clock CKd based on the timing data specified by the TS signal, supplies the periodic clock CKp to the pattern generator 104, and supplies the delayed clock CKd to the waveform shaper 106. Supply.
- the pattern generator 104 generates an address signal ADRS indicating each of the blocks which are a plurality of storage areas of the DUT 200 and a plurality of test pattern data Dt to be written in each of the plurality of blocks, and the waveform shaper 106 To supply.
- the waveform shaper 106 generates a test pattern signal St corresponding to the test pattern data Dt generated by the pattern generator 104 based on the delay clock CKd supplied from the timing generator 102. Then, the waveform shaper 106 supplies the address signal ADRS supplied from the pattern generator 104 and the generated test pattern signal St to the DUT 200 via the write driver 108.
- the pattern generator 104 generates in advance expected value data Dexp that is output data that the DUT 200 should output in accordance with the address signal ADRS and the test pattern signal St, and supplies the expected value data Dexp to the logic comparison unit 112.
- the comparator 110 reads the cell data Do corresponding to the address signal ADRS from the DUT 200 and outputs it to the logic comparison unit 112.
- the logical comparison unit 112 compares the data Do read from the DUT 200 with the expected value data Dexp supplied from the pattern generator 104 to determine whether the DUT 200 is good or bad.
- a bank address BA for designating a bank and a row address (row address) designated for each bank are applied to the memory, and then a column address (column address) is further applied.
- the data access is performed by specifying the access destination cell.
- the following processing may be executed. 1. While sequentially switching a plurality of banks, a row address for each bank is applied to perform memory access. 2. Returning to one of the banks, the memory access is performed by applying the same row address as that of the previous bank.
- the row address is generated by the pattern generator 104, but it is useless to repeatedly generate the same row address. Also, when testing a memory that supports burst transfer, it is necessary to access another bank during execution of burst read / burst write for a certain bank. In this case, two row addresses are stored. It is necessary at the same time. Therefore, the pattern generator 104 is provided with an address saving / loading circuit capable of saving / loading the generated row address. The configuration of the address save / load circuit according to the embodiment will be described in detail below.
- the address save / load circuit 2 saves a row address once given to each bank in a memory (referred to as a row address memory), and loads the row address when accessing the same row address of the same bank next time. Have The test apparatus 100 accesses the DUT 200 using the load address loaded by the address save / load circuit 2.
- FIG. 2 is a block diagram showing a part of the configuration of the pattern generator 104 having the address save / load circuit 2.
- the pattern generator 104 includes an address calculation circuit 10 and an address save / load circuit 2.
- the figure also shows commands and control signals generated by a pattern program for controlling the test.
- the address arithmetic circuit 10 generates an address signal indicating an access destination of the memory that is the DUT 200 according to the control signal S1 according to the pattern program.
- the address signal is applied to the DUT 200 via an output selection circuit 20 and an output holding circuit 22 described later, or once held in the address save / load circuit 2 and then applied to the DUT 200.
- the address arithmetic circuit 10 mainly has a function of generating a row address ADRS_ROW and a column address ADRS_COL for the DUT 200. Further, a read address adrs_r and a write address adrs_w for the row address memory 12 described later are also generated. Hereinafter, these signals are collectively referred to simply as an address signal.
- the bank address BA that designates the bank of the DUT 200 is not generated by the address arithmetic circuit 10, but is generated as a control signal (hereinafter referred to as a memory control signal MCNT) by a pattern program. I want to be.
- the various commands and control signals generated by the pattern program need to be generated for each cycle of the program and are not persistent in themselves. That is, when a command or a control signal is generated in a cycle by the pattern program, the command or control signal is invalid in the next cycle. If you want to keep the same value for a certain control signal, you need to program the same code in successive cycles.
- the address save / load circuit 2 includes a row address memory 12, a data setting circuit 14, a write address setting circuit 16, a read address setting circuit 18, an output selection circuit 20, and an output holding circuit 22.
- the row address memory 12 stores the row address ADRS_ROW generated by the address arithmetic circuit 10 for each bank of the DUT 200.
- the row addresses ADRS_ROW1 to ADRS_ROW4 of the first bank BANK1 to the fourth bank BANK4 are stored in the first address # 1 to the fourth address # 4 of the row address memory 12, respectively.
- the row address memory 12 has a general configuration and includes a write data terminal WD, a write address terminal WA, a write enable terminal WE, a read data terminal RD, and a read address terminal RA.
- the data setting circuit 14 sets a data signal wd to be applied to the write data terminal WD of the row address memory 12. Specifically, the data setting circuit 14 receives the row address ADRS_ROW generated by the address arithmetic circuit 10 and outputs this as write data wd to the write data terminal WD.
- the row address adrs_row_prog generated by the pattern program is also input to the data setting circuit 14.
- the data setting circuit 14 selects the row address adrs_row_prog generated by the pattern program instead of the row address ADRS_ROW generated by the address arithmetic circuit 10 and outputs it to the write data terminal WD of the row address memory 12. You can also.
- the bank address BA designating the bank of the DUT 200 is generated as the memory control signal MCNT by the pattern program.
- the memory control signal MCNT including the bank address BA is supplied to the write address setting circuit 16 and the read address setting circuit 18. Is input.
- the write address setting circuit 16 receives a memory control signal MCNT including the bank address BA, and gives an address (hereinafter referred to as a write address terminal WA) of the row address memory 12.
- a memory control signal MCNT including the bank address BA
- WA write address terminal
- Set sa (called save address). Normally, it is sufficient to use the memory control signal MCNT as it is or a predetermined bit in it as the save address sa. That is, the write address setting circuit 16 selects a bit to be the save address sa from a plurality of bits of the memory control signal MCNT.
- the write address setting circuit 16 receives the write address adrs_w generated by the address arithmetic circuit 10.
- the write address setting circuit 16 may select the write address adrs_w instead of the memory control signal MCNT and apply it to the write address terminal WA of the row address memory 12.
- the read address setting circuit 18 receives a memory control signal MCNT including the bank address BA, and gives an address (hereinafter, referred to as a read address terminal RA of the row address memory 12). Set la (called load address).
- the read address adrs_r generated by the address arithmetic circuit 10 is input to the read address setting circuit 18.
- the read address setting circuit 18 can select the read address adrs_r instead of the memory control signal MCNT and apply it to the read address terminal RA of the row address memory 12.
- the save command signal SAVE generated by the pattern program is input to the write enable terminal WE of the row address memory 12.
- the save command signal SAVE is asserted, the data input to the write data terminal WD is written into an area corresponding to the save address signal sa.
- the data of the load address la applied to the read address terminal RA is output from the read data terminal RD of the row address memory 12.
- the output selection circuit 20 receives the row address generated by the address arithmetic circuit 10 and the row address output from the read data terminal RD of the row address memory 12. The output selection circuit 20 selects the row address output from the read data terminal RD of the row address memory 12 when the load command signal LOAD generated by the pattern program is asserted, and when negated, the address calculation circuit 10. The address signal from is selected.
- the output holding circuit 22 receives the holding command signal HOLD generated by the pattern program.
- the holding command signal HOLD includes data for setting the number of cycles in which the output holding circuit 22 should hold the input signal. When performing a burst read test of the DUT 200, the number of cycles is set according to the burst length.
- the above is the configuration of the pattern generator 104. Next, the operation of the pattern generator 104 will be described.
- Step 1 The row address ADRS_ROW1 of the first bank BANK1 is accessed.
- Step 2. The row address ADRS_ROW2 of the second bank BANK2 is accessed.
- Step 3. The row address ADRS_ROW3 of the third bank BANK3 is accessed.
- Step 4. The row address ADRS_ROW4 of the fourth bank BANK4 is accessed.
- Step 5. The row address ADRS_ROW1 of the first bank BANK1 is accessed again.
- a memory control signal MCNT including a bank address BA designating the first bank BANK1 to be accessed is generated by the pattern program. Further, the address arithmetic circuit 10 generates a row address ADRS_ROW1 and a column address ADRS_COL that specify an access destination of the DUT 200. The test apparatus 100 accesses the DUT 200 using the bank address BA, addresses ADRS_ROW1, and ADRS_COL included in the memory control signal MCNT.
- the data setting circuit 14 selects the row address ADRS_ROW1 generated by the address arithmetic circuit 10 and supplies it to the write data terminal WD of the row address memory 12.
- step 2 to 4 the same processing as in step 1 is repeated.
- row addresses ADRS_ROW1 to ADRS_ROW4 are saved in addresses # 1 to # 4 of the row address memory 12, respectively.
- the memory control signal MCNT including the bank address BA indicating the first bank BANK1 is generated by the pattern program.
- the row address ADRS_ROW 1 is supplied to the DUT 200 via the output holding circuit 22.
- the pattern generator 104 uses the memory control signal MCNT including the bank address BA as the save address sa and the load address la for the row address memory 12. That is, since the user does not need to make a description about the save address sa and the load address la when programming the pattern program, the burden of programming is reduced.
- the write address setting circuit 16 and the read address setting circuit 18 of the pattern generator 104 in FIG. 2 access the row address memory 12 based on the addresses adrs_w and adrs_r generated by the address arithmetic circuit 10, respectively.
- the write address setting circuit 16 and the read address setting circuit 18 of the pattern generator 104 in FIG. 2 access the row address memory 12 based on the addresses adrs_w and adrs_r generated by the address arithmetic circuit 10, respectively.
- the write address setting circuit 16 and the read address setting circuit 18 can give the addresses adrs_w and adrs_r generated by the address arithmetic circuit 10 to the row address memory 12. Therefore, since the user can give an arbitrary address separately from the memory control signal MCNT (that is, the bank address BA), the flexibility of the test can be increased.
- Steps 1 to 4 are the same as those described above.
- the memory control signal MCNT including the bank address BA indicating the first bank BANK1 is generated by the pattern program.
- the pattern program sets a cycle corresponding to the burst length to the hold command signal HOLD and asserts the load command signal LOAD. Then, the row address ADRS_ROW1 saved in the address # 1 can be supplied to the DUT 200 via the output holding circuit 22 during the set cycle.
- the output selection circuit 20 selects the row address loaded from the row address memory 12 when the load command signal LAOD is asserted, and selects the row address generated by the address arithmetic circuit 10 when negated. Therefore, if the output holding circuit 22 is not provided, the load command signal LOAD must be asserted every cycle during the burst transfer, and the load command must be described in the pattern program every cycle. The program becomes complicated. In particular, since a plurality of burst lengths can be set, it is very troublesome to code a program according to the burst length. On the other hand, according to the address save / load circuit 2 according to the embodiment, by providing the output holding circuit 22, the load instruction and the holding instruction are described only once at the beginning of burst transfer in the pattern program. Therefore, coding can be simplified.
- the present invention can be used for a memory testing apparatus.
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Abstract
Description
この試験装置によれば、ユーザがパターンプログラムをプログラミングする際の負担を軽減できる。
1. 複数のバンクを順に切り換えながら、バンクごとのロウアドレスを印加してメモリアクセスする。
2. いずれかのバンクに戻り、そのバンクの、前回と同じロウアドレスを印加してメモリアクセスする。
ステップ1. 第1バンクBANK1のロウアドレスADRS_ROW1にアクセスする。
ステップ2. 第2バンクBANK2のロウアドレスADRS_ROW2にアクセスする。
ステップ3. 第3バンクBANK3のロウアドレスADRS_ROW3にアクセスする。
ステップ4. 第4バンクBANK4のロウアドレスADRS_ROW4にアクセスする。
ステップ5. 再度、第1バンクBANK1のロウアドレスADRS_ROW1にアクセスする。
パターンプログラムによって、アクセス先の第1バンクBANK1を指定するバンクアドレスBAを含むメモリ制御信号MCNTが生成される。また、アドレス演算回路10によりDUT200のアクセス先を指定するロウアドレスADRS_ROW1、カラムアドレスADRS_COLが生成される。試験装置100は、メモリ制御信号MCNTに含まれるバンクアドレスBA、アドレスADRS_ROW1、ADRS_COLを利用してDUT200にアクセスする。
パターンプログラムにより、第1バンクBANK1を示すバンクアドレスBAを含むメモリ制御信号MCNTが生成される。リードアドレス設定回路18は、バンクアドレスBAを含むメモリ制御信号MCNTを受け、バンクアドレスBAに応じたロードアドレスlaを設定する。具体的には、第1バンクBANK1を指定するバンクアドレスBAからロードアドレスla(=#1)を生成し、ロウアドレス用メモリ12のリードアドレス端子RAに供給する。その結果、ロウアドレス用メモリ12のリードデータ端子RDからは、アドレス#1にセーブされているロウアドレスADRS_ROW1が出力される。
比較のために、図2のパターン発生器104のライトアドレス設定回路16およびリードアドレス設定回路18がそれぞれ、アドレス演算回路10により生成されるアドレスadrs_wおよびadrs_rにもとづいてロウアドレス用メモリ12にアクセスする場合の処理について検討する。
ステップ1~4については上述した処理と同様である。
パターンプログラムにより、第1バンクBANK1を示すバンクアドレスBAを含むメモリ制御信号MCNTが生成される。リードアドレス設定回路18は、バンクアドレスBAを含むメモリ制御信号MCNTを受け、バンクアドレスBAに応じたロードアドレスla(=#1)を生成する。
Claims (6)
- マルチバンク構成を有する被試験メモリを検査する試験装置に搭載されるパターン発生器であって、
前記被試験メモリのアクセス先を示すロウアドレスを生成するアドレス演算回路と、
前記アドレス演算回路により生成された前記ロウアドレスをバンクごとに記憶するロウアドレス用メモリと、
を備え、
前記被試験メモリに印加するバンクアドレスを含み、プログラムにより生成されるメモリ制御信号を、前記ロウアドレス用メモリに前記ロウアドレスを書き込む際のセーブアドレス、ならびに前記ロウアドレス用メモリから前記ロウアドレスを読み出す際のロードアドレスとして利用することを特徴とするパターン発生器。 - 前記メモリにアクセスする際のバースト長を設定するために前記プログラムにより生成される制御信号を受け、バースト長に応じた期間、前記ロウアドレス用メモリから読み出した前記ロウアドレスを保持する出力保持回路をさらに備えることを特徴とする請求項1に記載のパターン発生器。
- 前記アドレス演算回路は、前記ロウアドレスに加えて、前記ロウアドレス用メモリに対するセーブアドレスおよびロードアドレスを生成可能に構成され、
前記パターン発生器は、
前記メモリ制御信号と前記アドレス演算回路によって生成される前記セーブアドレスのいずれかを選択して、前記ロウアドレス用メモリに前記ロウアドレスを書き込む際のアドレスとして出力するライトアドレス設定部と、
前記メモリ制御信号と前記アドレス演算回路によって生成される前記ロードアドレスのいずれかを選択して、前記ロウアドレス用メモリから前記ロウアドレスを読み出す際のアドレスとして出力するリードアドレス設定部と、
をさらに備えることを特徴とする請求項1または2に記載のパターン発生器。 - 前記パターン発生器は、
前記アドレス演算回路によって生成されるロウアドレスと、プログラムに応じて生成されるロウアドレスのいずれかを選択して、前記ロウアドレス用メモリに書き込むべきデータ信号として出力するデータ設定部をさらに備えることを特徴とする請求項1から3のいずれかに記載のパターン発生器。 - 前記ロウアドレス用メモリから読み出したロウアドレスと前記アドレス演算回路により生成されるロウアドレスのいずれかを選択する出力選択回路をさらに備えることを特徴とする請求項1から3のいずれかに記載のパターン発生器。
- 請求項1から5のいずれかに記載のパターン発生器を備えることを特徴とするメモリの試験装置。
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PCT/JP2008/001273 WO2009141848A1 (ja) | 2008-05-21 | 2008-05-21 | パターン発生器およびそれを用いたメモリの試験装置 |
US12/991,876 US8074134B2 (en) | 2008-05-21 | 2008-05-21 | Pattern generator and memory testing device using the same |
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2008
- 2008-05-21 US US12/991,876 patent/US8074134B2/en active Active
- 2008-05-21 KR KR1020107028625A patent/KR101021727B1/ko active IP Right Grant
- 2008-05-21 JP JP2010512847A patent/JP4669089B2/ja not_active Expired - Fee Related
- 2008-05-21 WO PCT/JP2008/001273 patent/WO2009141848A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5263632A (en) * | 1975-11-19 | 1977-05-26 | Matsushita Electric Ind Co Ltd | Memory allocating method for display device |
JPH0462646A (ja) * | 1990-07-02 | 1992-02-27 | Nippon Telegr & Teleph Corp <Ntt> | 画像変換処理装置 |
JPH0553550A (ja) * | 1991-08-28 | 1993-03-05 | Toshiba Corp | 表示メモリ制御装置 |
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KR101021727B1 (ko) | 2011-03-15 |
US20110119539A1 (en) | 2011-05-19 |
US8074134B2 (en) | 2011-12-06 |
KR20110014658A (ko) | 2011-02-11 |
JPWO2009141848A1 (ja) | 2011-09-22 |
JP4669089B2 (ja) | 2011-04-13 |
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