WO2009133625A1 - 配線基板およびその製造方法、電子装置の製造方法 - Google Patents
配線基板およびその製造方法、電子装置の製造方法 Download PDFInfo
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- WO2009133625A1 WO2009133625A1 PCT/JP2008/058427 JP2008058427W WO2009133625A1 WO 2009133625 A1 WO2009133625 A1 WO 2009133625A1 JP 2008058427 W JP2008058427 W JP 2008058427W WO 2009133625 A1 WO2009133625 A1 WO 2009133625A1
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- metal layer
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Definitions
- the present invention generally relates to an electronic device, and more particularly to a wiring board used in the electronic device and a manufacturing method thereof.
- porous silica has an elastic modulus of 4 to 8 GPa, which is lower in mechanical strength than conventional interlayer insulating materials.
- Patent Document 1 proposes a technique for forming a solder layer on a Cu wiring pattern on a wiring board in the form of a laminated structure in which a tin (Sn) layer and a bismuth (Bi) layer are sequentially laminated. ing.
- the solder layer melts at a temperature of 139 ° C. due to the eutectic reaction of Sn and Bi, and other elements such as a semiconductor chip can be bonded to the connection electrode at a low temperature. It is considered to be.
- the thickness of the Sn layer formed on the Cu layer is set large, and even if a large amount of Sn atoms are taken into the Cu electrode pad, the Sn layer remains on the surface of the Cu electrode pad. It is necessary to prevent the depletion of Sn atoms.
- the film thickness of the Sn layer increases, and in the case where a fine pattern is formed at a fine pitch, There arises a problem that adjacent electrode pads are short-circuited through a thick solder layer. JP 2001-274201 A JP 2003-174252 A
- a base a Cu wiring pattern formed on the base, a first metal layer formed on a surface of the Cu wiring pattern, and a surface of the first metal layer are formed.
- the first metal layer is less reactive with Cu than the second metal layer, and the first metal layer and the second metal layer are Provided are a wiring board that generates a eutectic reaction, and a method of manufacturing an electronic device using the wiring board.
- the step of forming a first metal layer on the Cu wiring pattern formed on the substrate and the eutectic between the first metal layer and the first metal layer are formed on the first metal layer.
- a first metal layer having a lower reactivity with Cu is formed on the surface of the Cu wiring pattern, and a second metal having a higher reactivity with Cu and causing a eutectic reaction with the first metal layer is formed thereon.
- the first metal layer diffuses into the Cu wiring pattern during the reflow process and is depleted on the surface of the Cu wiring pattern, thereby eliminating the problem that the desired eutectic reaction does not occur.
- a reflow process at a lower temperature than before can be performed, and a low-K material having low heat resistance can be used for the semiconductor chip.
- FIG. 2 is a diagram (part 1) for explaining a manufacturing process of the wiring board of FIG. 1;
- FIG. 8 is a diagram (part 2) for explaining a manufacturing process of the wiring board of FIG. 1;
- FIG. 8 is a diagram (No. 3) for explaining the production process of the wiring board in FIG. 1;
- FIG. 2B It is a figure which expands and shows a part of FIG. 2B.
- FIG. 2C FIG. 2 is a diagram (part 1) demonstrating that Sn—Bi eutectic solder is formed.
- FIG. 2 is a diagram (part 2) demonstrating that Sn—Bi eutectic solder is formed.
- FIG. 1 is a diagram (part 1) demonstrating that Sn—Bi eutectic solder is formed.
- FIG. 3 is a diagram (part 3) demonstrating that an Sn—Bi eutectic solder is formed.
- FIG. 3 is a view (No. 1) showing a mounting process of a semiconductor chip on the wiring board of FIG. 2;
- FIG. 3 is a view (No. 2) showing a mounting process of a semiconductor chip on the wiring board of FIG. 2;
- It is a figure which shows the temperature curve used in 1st Embodiment.
- It is a figure which shows the wiring board by the modification of 1st Embodiment.
- FIG. (2) explaining the manufacturing process of the wiring board by 2nd Embodiment.
- FIG. (4) explaining the manufacturing process of the wiring board by 2nd Embodiment. It is FIG. (5) explaining the manufacturing process of the wiring board by 2nd Embodiment. It is FIG. (6) explaining the manufacturing process of the wiring board by 2nd Embodiment. It is FIG. (1) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (2) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (3) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (4) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG.
- FIG. (5) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (6) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (7) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (The 8) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (9) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (10) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (11) explaining the manufacturing process of the wiring board by 3rd Embodiment. It is FIG. (12) explaining the manufacturing process of the wiring board by 3rd Embodiment.
- FIG. 1 shows a configuration of a wiring board 10 according to the first embodiment.
- the wiring board 10 has a base 11 made of an epoxy material, and Cu wiring patterns 11A and 11B are formed thereon.
- the Cu wiring patterns 11A and 11B constitute electrode pads and carry solder layers 12A and 12B each having a Sn / Bi laminated structure in which a Bi layer 12 and a Sn layer 13 are sequentially laminated.
- the Bi layer 12 is in direct contact with the Cu electrode pads 11A and 11B, but Bi does not form an intermetallic compound with Cu, so Bi atoms in the Bi layer 12 are Cu electrodes. Even if it diffuses into the pad 11A or 11B, the degree is negligible, and the situation where the Bi layer 12 disappears does not occur. For this reason, when the Sn layer 13 is formed on the Bi layer 12, the Bi layer 12 and the Sn layer 13 surely cause a eutectic reaction by reflow, and the solder layers 12A and 12B are surely at a low temperature of less than 200 ° C. Melt.
- a Cu wiring layer including the Cu electrode pads 11A and 11B is formed on the resin substrate 11 at a pitch of 25 ⁇ m by an electroless plating method or an electrolytic plating method performed through a resist pattern (not shown). .
- the width W of the electrode pads 11A and 11B is set to 20 ⁇ m, and as a result, the gap G between the electrode pads 11A and 11B is 5 ⁇ m.
- the Cu electrode pads 11A and 11B formed on the substrate 11 are first washed with 10% sulfuric acid for 30 seconds, then washed with pure water for 30 seconds, and further in a dry nitrogen atmosphere. Dry in.
- a Bi plating layer 12 is formed on the surfaces of the Cu electrode pads 11A and 11B.
- the film thickness is about 1 ⁇ m on average.
- each island has a size of about 2 to 5 ⁇ m.
- FIG. 3 is an enlarged view showing a state in the vicinity of the surface of the Cu electrode pad 11A or 11B in FIG. 2B.
- the formation process of the Bi plating layer 12 is carried out by using bismuth nitrate 1 to 10 g / L, thiouric acid 5 to 60 g / L, and nitric acid 5 to 10 mL.
- the electroless plating bath at 70 ° C. using an electrolytic plating solution is carried out for 5 minutes.
- the Bi plating layer 12 can be formed so as to cover about 60% of the surface area of the Cu electrode pads 11A and 11B.
- the structure of FIG. 2B is washed in pure water for 30 seconds, and the surfaces of the Cu electrode pads 11A and 11B are washed with 10% sulfuric acid for 30 seconds, and further pure water. Wash for 30 seconds.
- the Sn plating layer 13 is formed with a film thickness of about 1 ⁇ m by the Sn electroless plating bath on the structure thus cleaned, and the laminated solder described in FIG.
- the wiring board 10 having the layers 12A and 12B is obtained.
- the formation process of the Sn plating layer 13 is as follows: SnCl 2 is 25 g / L, CS (NH 2 ) 2 is 70 g / L, hydrochloric acid is 50 g / L, NaHPO 2 .2H 2 O is 15 g / L.
- the electroless plating bath at 70 ° C. using an electroless plating solution containing L and a surfactant at a rate of 0.5 g / L is carried out for 10 minutes.
- an Sn plating layer 13 is continuously formed on the Cu electrode pads 11A and 11B so as to cover the island-like Bi plating layer 12.
- the Sn plating layer 13 is formed to have substantially the same thickness as the Bi plating layer 12 in consideration of the eutectic point composition (Sn42 wt% -Bi58 wt%).
- the Sn plating layer 13 formed in this way is partly in direct contact with the Cu electrode pad 11A or 11B as shown in FIG. 4, but its area is relatively small, and therefore the structure of FIG. 2C.
- the laminated solder layers 12A and 12B are reflowed in FIG. 5, it is possible to cause an effective eutectic reaction between the Bi plating layer 12 and the Sn plating layer 13.
- FIGS. 5A to 5C show the results of reflowing a sample having a solder layer in which a Bi plating layer and a Sn plating layer similar to those of the wiring substrate 10 of FIG. 1 are laminated by heat treatment.
- the Bi plating layer and the Sn plating layer are formed on a substantially circular Cu pattern by the steps of FIGS. 2A to 2C.
- the Bi plating layer is formed directly on the Cu pattern with an average film thickness of about 1.0 ⁇ m, and the Sn plating layer is formed on the Bi plating layer with a film thickness of about 0.7 ⁇ m. ing.
- an RMA type flux is applied to the sample surface, and heating is performed at a rate of temperature increase of 2 ° C./min.
- FIG. 5A shows the state of the sample surface when the temperature of the sample reaches 130 ° C., but no change has occurred in the state of the sample surface since the start of temperature increase.
- FIG. 5B shows the state of the sample surface when the temperature of the sample reaches 140 ° C., slightly exceeding the 139 ° C. which is the Sn—Bi eutectic point.
- FIG. 5C shows the state of the sample surface when the temperature is raised to 150 ° C., and it can be seen that the solder layer continues to melt.
- the wiring board 10 of FIG. Even if a part of the Sn plating layer 13 is in direct contact with the Cu electrode pads 11A and 11B, the diffusion of Sn atoms into the Cu electrode pad 11A or 11B is effectively suppressed in the majority of the Sn plating layer 13. It was confirmed that melting occurred near the eutectic point of 139 ° C. This is considered to be an effect that the Bi plating layer 12 is interposed between the Sn plating layer 13 and the Cu electrode pad 11A or 11B.
- Table 1 below shows the presence or absence of the formation of the SnCu diffusion layer, that is, the Cu 6 Sn 5 intermetallic compound immediately after the formation of the Sn plating layer 13 performed on the structure of FIG.
- the thickness of the Bi plating layer 12 and the Sn plating layer 13 indicates whether or not the solder layers 12A and 12B are melted when reflowing is performed at 180 ° C., and whether or not there is a short circuit between the adjacent electrodes 11A and 11B.
- Comparison samples (samples # 5 and 6) with various changes in the number and comparison samples (samples # 1 to 3) corresponding to the conventional example in which the order of the Bi plating layer 12 and the Sn plating layer 13 is changed It is a table shown.
- the sample of the present invention is sample # 4. However, the results in Table 1 are for the case where Cu electrode pads 11A and 11B having a width W of 20 ⁇ m are arranged at intervals of 5 ⁇ m.
- the film thickness of the Sn plating layer 13 is preferably limited to about 1 ⁇ m. Is concluded.
- the electroless plating step for forming the Bi plating layer 12 in FIG. 2B is performed using BiCl 3 at 30 g / L, C 5 H 5 O 7 Na 3 .2H 2 O at 100 g / L, C 10 H. 14 At 40 ° C. using an electroless plating solution containing 30 g ⁇ L of Na 2 O 3 .2H 2 O, 40 g / L of N (CH 2 COOH) 3 and 5 g / L of SnCl 2 .2H 2 O It is also possible to carry out with an electroless plating bath.
- the semiconductor chip 31 is flip-chip mounted on the wiring substrate 10 of FIG. 1 as shown in FIG. 6A, and reflow is performed by, for example, temperature curve heat treatment shown in FIG. , 12B is induced at a temperature below 200 ° C., and the electronic device 30 on which the semiconductor chip 31 is mounted can be manufactured as shown in FIG. 6B.
- the solder layers 12A and 12B are changed to Sn—Bi alloy solder layers 12Eu having a eutectic composition or a composition close to the eutectic composition.
- the electrode pads 31A and 31B on the lower surface of the semiconductor chip 31 can be bonded to the Cu electrode pads 11A and 11B at a low temperature of less than 200 ° C., respectively.
- the maximum temperature is less than 200 ° C., damage to the semiconductor chip can be avoided even when a porous low dielectric constant material is used as the interlayer insulating material of the semiconductor chip.
- the maximum temperature is raised from 139 ° C., which is the Sn—Bi eutectic point, so that the amount ratio of the Bi plating layer 12 and the Sn plating layer 13 is somewhat the same. Even if it deviates from the crystal point composition, the solder layer can be surely melted.
- solder layers 12A and 12B can be reflowed to form the wiring substrate 10A changed to the Sn—Bi alloy solder layer 12Eu.
- 9A to 9F are views showing a manufacturing process of the wiring board 20 according to the second embodiment of the present invention. However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.
- Cu electrode pads 11A and 11B are formed on the base 11 of the wiring board 20 as in the case of FIG. 2A.
- the Cu electrode pads 11A and 11B are formed in the step of FIG. 9B.
- An Sn sacrificial layer 13S is formed on the electrode pads 11A and 11B by an electroless plating method so as to have a film thickness of, for example, about 1 ⁇ m.
- the Cu electrode pads 11A and 11B in the structure of FIG. 9A are washed with 10% sulfuric acid for 30 seconds, and then with pure water for 30 seconds. This is performed after washing and drying in nitrogen gas.
- the structure of FIG. 9A is obtained by adding SnCl 2 at 25 g / L, CS (NH 2 ) 2 at 70 g / L, HCl at 50 g / L, NaHPO 2 .2H 2 O at 15 g / L, and surfactant. Is immersed in an electroless plating solution containing 0.5 g / L and an electroless plating bath is performed at 70 ° C. for 3 minutes to form the Sn sacrificial layer 13S.
- the structure of FIG. 9B is changed to 1-10 g / L of bismuth nitrate, 5-60 g / L of thiourea, and nitric acid. It is immersed in an electroless plating solution containing 5 to 10 mL and subjected to an electroless plating bath at 50 ° C. for 10 minutes. As a result, as shown in FIG. 9C, the Bi plating layer 12 is formed with a film thickness of about 1 ⁇ m on the Cu electrode pads 11A and 11B.
- the Bi plating layer 12 is formed, Sn atoms constituting the Sn sacrificial layer 13S diffuse into the Cu pad electrode 11A or 11B. As a result, an interface region 11S containing the intermetallic compound Cu 6 Sn 5 is formed along the surface of the Cu pad electrode 11A or 11B.
- the thickness of the Sn sacrificial layer 13S serving as the Sn atom supply source is as thin as about 1 ⁇ m, so the interface region 11S is in the range of about 0.2 ⁇ m on the surface of the Cu electrode pad 11A or 11B. It is limited to. Further, the Sn sacrificial layer 13S does not remain on the surfaces of the Cu electrode pads 11A and 11B. That is, there is no Sn layer between the Cu electrode pad 11A or 11B and the Bi plating layer 12.
- FIG. 9C is washed with pure water for 30 seconds. Further, at the stage of FIG. 9D, for example, a Cu electroless plating solution “Sulcup PRX” manufactured by Uemura Kogyo Co., Ltd. is used, and the structure of FIG. Immerse in an electrolytic plating solution and perform an electroless plating bath at 40 ° C. for 5 minutes. As a result, a Cu sacrificial layer 11T having a thickness of about 0.5 ⁇ m is formed outside the Bi plated layer 12 as shown in FIG. 9D.
- FIG. 9D is washed in pure water for 30 seconds, and further SnCl 2 is 25 g / L, CS (NH 2 ) 2 is 70 g / L, HCl is 50 g / L, NaHPO 2 .2H 2 O is 15 g. / L, immersed in an electroless plating solution containing 0.5 g / L of a surfactant, and subjected to an electroless plating bath at 70 ° C. for 3 minutes to form the Sn plating layer 13 as shown in FIG. 9E. .
- the Bi plating layer 12 when the Bi plating layer 12 is formed, the Bi plating layer 12 is formed on the Sn sacrificial layer 13S having a good affinity for the Bi layer. It is flat and no island growth occurs as in the previous embodiment. For this reason, when forming the Sn plating layer 13, the diffusion of Sn atoms from the Sn plating layer 13 to the Cu electrode pad 11A or 11B is prevented and formed more efficiently than in the previous embodiment. It becomes possible to control the composition of the solder layers 12A and 12B having the Sn / Bi multilayer structure more precisely in the vicinity of the eutectic composition. Accordingly, the melting points of the solder layers 12A and 12B can be further reduced. [Third Embodiment] Next, a third embodiment of the present invention applied to a wiring substrate having a core substrate will be described with reference to FIGS. 10A to 10L.
- through vias 61A and 61B made of Cu plugs are formed in the core substrate 61. Further, wiring patterns 11a and 11b are formed on the upper surface, and Cu wiring patterns 11c and 11d are formed on the lower surface. Is formed.
- a low dielectric constant resin film 62A is formed on the upper surface of the core substrate 61 so as to cover the wiring patterns 11a and 11b, and on the lower surface of the core substrate 61, the wiring patterns 11c, A low dielectric constant resin film 62B such as NCS is formed to cover 11d.
- openings 62a and 62b exposing the Cu wiring patterns 61a and 61b are formed in the low dielectric constant resin film 62A, respectively, and the Cu wiring is formed in the low dielectric constant resin film 62B. Openings 62c and 62d that expose patterns 61c and 61d, respectively, are formed.
- a Cu seed layer 63A is formed on the low dielectric constant resin layer 62A by electroless plating so as to cover the openings 62a and 62b, and at the same time on the low dielectric constant resin layer 62B.
- a Cu seed layer 63B is formed by electroless plating so as to cover the openings 62c and 62d.
- a resist pattern R1 having an opening corresponding to the wiring pattern to be formed is formed on the Cu seed layer 63A.
- the wiring to be formed on the Cu seed layer 63B is formed.
- a resist pattern R2 having an opening corresponding to the pattern is formed.
- electrolytic plating is performed using the Cu seed layers 63A and 63B as electrodes, and Cu wiring patterns 64A to 64H are formed in the openings.
- the resist patterns R1 and R2 are removed, the Cu seed layers 63A and 63B exposed by sputtering are removed, and the formed Cu wiring patterns 64A to 64H are separated.
- FIGS. 10G to 10I a solder resist film R3 is formed on the upper surface of the wiring board including the wiring patterns 64A to 64D except for the pad electrode forming portion on the upper surface of the wiring board thus formed.
- the pad electrode forming portions 65A to 65C are formed so as to be exposed.
- FIG. 10G is a plan view showing the upper surface of the wiring board
- FIGS. 10H and 10I are cross-sectional views taken along lines AB and CD, respectively.
- electroless plating is performed using the solder resist film R3 as a mask.
- the Bi plating layer 66 corresponding to the Bi plating layer 12 in the previous embodiment is formed, and then the previous execution.
- the Sn plating layer 67 corresponding to the Sn plating layer 13 in the form is formed with a film thickness of about 1 ⁇ m.
- the Bi plating layer 66 and the Sn plating layer 67 form a eutectic solder layer having a Sn—Bi-based laminated structure. As described above, the Bi plating layer 66 and the Sn plating layer 67 are formed on the portion contacting the Cu pad electrodes 65A to 65C. A plating layer 66 is formed. Therefore, unlike the eutectic solder layer having a conventional laminated structure in which the Sn plating layer is in direct contact, Sn atoms are not depleted.
- the film thickness of the solder layer formed on the Cu electrode pad can be reduced, a short circuit does not occur even in a configuration in which the Cu electrode pads are arranged at fine intervals.
- Bi plating layer 12 or 66 instead of the Bi plating layer 12 or 66, it is possible to use another metal element that has low reactivity with Cu and does not form an intermetallic compound with Cu.
- Bi instead of Bi, it is possible to use lead (Pb), indium (In), silver (Ag), or an alloy containing Bi, Pb, In, or Ag as a main component.
- another metal forming eutectic solder with the plating layer 12 or 66 for example, gold (Au), or an alloy containing Sn or Au as a main component can be used. .
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Abstract
Description
11 基体
11A,11B,65A~65C Cu電極パッド
11S Cu電極パッド表面領域
11T Cu犠牲層
12.66 Biメッキ層
12A,12B はんだ層
12Eu Sn-Bi共晶はんだ
13,67 Snメッキ層
13S Sn犠牲層
13T Cu犠牲層
13U Snメッキ層界面領域
30 電子装置
31 半導体チップ
31A,31B 電極パッド
61 コア基板
61A,61B スルービア
61a~61d,64A~64H Cu配線パターン
62A,62B 低誘電率樹脂膜
62a~62d 開口部
63A,63B Cuシード層
図1は、第1の実施形態による配線基板10の構成を示す。
[第2の実施形態]
図9A~9Fは、本発明の第2の実施形態による配線基板20の製造工程を示す図である。ただし図中、先に説明した部分に対応する部分には同一の参照符号を付し、説明を省略する。
[第3の実施形態]
次にコア基板を有する配線基板に対して適用した本発明の第3の実施形態について、図10A~10Lを参照しながら説明する。
Claims (10)
- 基体と、
前記基体上に形成されたCu配線パターンと、
前記Cu配線パターンの表面に形成された第1の金属層と、
前記第1の金属層の表面に形成された第2の金属層と、
を含み、
前記第1の金属層は、前記第2の金属層と比べて、Cuとの反応性が低く、
前記第1の金属層と第2の金属層は共晶反応を生じる配線基板。 - 前記第2の金属層はCuと金属間化合物を形成し、前記第1の金属層は、Cuと金属間化合物を形成しない請求項1記載の配線基板。
- 前記共晶反応は、139℃以上、150℃以下の温度で生じる請求項1または2記載の配線基板。
- 前記第1の金属層は、ビスマス、鉛、インジウム、銀、あるいはこれらのいずれかを主成分とする合金よりなり、前記第2の金属層は、錫、金、あるいはこれらのいずれかを主成分とする合金よりなる請求項1~3のうち、いずれか一項記載の配線基板。
- さらに前記Cu電極パターンは、前記第1の金属層との界面に沿って、前記第2の金属層を構成する金属元素を含む第1の界面領域を有し、前記第2の金属層は、前記第1の金属層との界面に沿って、Cuを含む第2の界面領域を有する請求項1~4のうち、いずれか一項記載の配線基板。
- 請求項1~5のうち、いずれか一項記載の配線基板上に電子部品を、前記電子装置の端子が前記第2の金属層と当接するように載置する工程と、
前記第1および第2の金属層をリフローさせ、前記電子部品の前記端子を前記Cu配線パターンに接合する工程と、
を含むことを特徴とする電子装置の製造方法。 - 基体上に形成されたCu配線パターン上に第1の金属層を形成する工程と、
前記第1の金属層上に、前記第1の金属層との間で共晶反応を生じる第2の金属層を形成する工程と、
リフローを行い、前記第1の金属層と第2の金属層との間に共晶反応を生じさせる工程と、
を含み、
前記第1の金属層は前記第2の金属層と比べてCuとの反応性が低い配線基板の製造方法。 - 前記第2の金属層はCuと金属間化合物を形成し、第2の金属層はCuと金属間化合物を形成しない請求項7記載の配線基板の製造方法。
- さらに前記基体と前記第1の金属層との間に、前記第2の金属層と同じ組成の第1の犠牲層を形成する工程と、前記第1の金属層と前記第2の金属層との間に、Cuよりなる第2の犠牲層を形成する工程を含み、前記第1の犠牲層は前記第1の金属層の形成工程で消失し、前記第2の犠牲層は、前記第2の金属層の工程で消失する請求項7または8記載の配線基板の製造方法。
- 前記第1の金属層は、ビスマス、鉛、インジウム、銀、あるいはこれらのいずれかを主成分とする合金よりなり、前記第2の金属層は、錫、金、あるいはこれらのいずれかを主成分とする合金よりなる請求項7~9のうち、いずれか一項記載の配線基板の製造方法。
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KR1020107024278A KR101184108B1 (ko) | 2008-05-02 | 2008-05-02 | 배선 기판 및 그 제조 방법, 전자 장치의 제조 방법 |
JP2010509984A JP5067481B2 (ja) | 2008-05-02 | 2008-05-02 | 配線基板およびその製造方法、電子装置の製造方法 |
PCT/JP2008/058427 WO2009133625A1 (ja) | 2008-05-02 | 2008-05-02 | 配線基板およびその製造方法、電子装置の製造方法 |
US12/908,404 US8713792B2 (en) | 2008-05-02 | 2010-10-20 | Method of manufacturing a printed wiring board |
US14/221,431 US20140202739A1 (en) | 2008-05-02 | 2014-03-21 | Printed wiring board having metal layers producing eutectic reaction |
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PCT/JP2008/058427 WO2009133625A1 (ja) | 2008-05-02 | 2008-05-02 | 配線基板およびその製造方法、電子装置の製造方法 |
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US12/908,404 Continuation US8713792B2 (en) | 2008-05-02 | 2010-10-20 | Method of manufacturing a printed wiring board |
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JP (1) | JP5067481B2 (ja) |
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JP2015536893A (ja) * | 2012-10-12 | 2015-12-24 | コーニング インコーポレイテッド | 低弾性率層および残留強度を有する物品 |
US11434166B2 (en) | 2012-10-12 | 2022-09-06 | Corning Incorporated | Articles with a low-elastic modulus layer and retained strength |
US11479501B2 (en) | 2012-10-12 | 2022-10-25 | Corning Incorporated | Articles with a low-elastic modulus layer and retained strength |
US11919803B2 (en) | 2012-10-12 | 2024-03-05 | Corning Incorporated | Articles with a low-elastic modulus layer and retained strength |
JP2016029682A (ja) * | 2014-07-25 | 2016-03-03 | イビデン株式会社 | プリント配線板 |
Also Published As
Publication number | Publication date |
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KR101184108B1 (ko) | 2012-09-18 |
US8713792B2 (en) | 2014-05-06 |
US20140202739A1 (en) | 2014-07-24 |
JPWO2009133625A1 (ja) | 2011-08-25 |
JP5067481B2 (ja) | 2012-11-07 |
KR20100126584A (ko) | 2010-12-01 |
US20110031002A1 (en) | 2011-02-10 |
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