WO2009121200A1 - 平衡多层基板应力的方法及多层基板 - Google Patents
平衡多层基板应力的方法及多层基板 Download PDFInfo
- Publication number
- WO2009121200A1 WO2009121200A1 PCT/CN2008/000630 CN2008000630W WO2009121200A1 WO 2009121200 A1 WO2009121200 A1 WO 2009121200A1 CN 2008000630 W CN2008000630 W CN 2008000630W WO 2009121200 A1 WO2009121200 A1 WO 2009121200A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal layer
- layer
- area
- multilayer substrate
- redundant
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0277—Bendability or stretchability details
- H05K1/028—Bending or folding regions of flexible printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09136—Means for correcting warpage
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0969—Apertured conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Definitions
- the present invention relates to a method and a multilayer for balancing a multilayer reaction force, and more particularly to a method for balancing a soft multilayer substrate due to a large difference in area and position of different metal layers or dielectric layers. Stress, thereby avoiding the method of multi-layer stress balancing multi-layer stress and multi-layer.
- a multi-layer substrate has a plurality of dielectric layers formed by coating, and a corresponding metal layer is respectively formed by various lithography techniques between the dielectric layers, and the dielectric layer and the metal layer overlap to form a plurality of layers.
- the substrate is used to realize a multilayer substrate having the advantages of thin thickness and material simplification, and is particularly suitable for fabricating a flexible multilayer substrate. Since the dielectric layer formed by the coating method is a wet film, there is a process step of drying these dielectric layers to harden them. Due to the circuit design, each metal layer has a different area and the position in the multilayer substrate is also different. In contrast, the corresponding dielectric layers have different areas.
- the drying and hardening process steps are performed, because the dielectric layers shrink in different proportions (
- the dielectric layer has the same material and the same shrinkage rate, but the ratio of shrinkage to each other is different due to its shape, area, and volume.)
- the stress imbalance occurs between the dielectric layers and the metal layers of the multilayer substrate, resulting in more Layer ⁇ 1 ⁇ 2 raw warp.
- the dielectric layer is not formed by coating, the area, thickness and even the structural material of each layer are not the same, which causes stress imbalance, resulting in warpage of the multilayer.
- Multi-layer warpage with severe warpage will affect the accuracy of subsequent system assembly, and even assembly due to severe warpage.
- the flexible characteristics are the main purpose of the development of the soft substrate industry. Therefore, after the flexible multi-layer substrate is fabricated into a commodity, some of the specific regions or even the whole may be often flexed at will, such as the above-mentioned stress and the occurrence of warpage are not solved, and the confirmation is confirmed. It will be more likely to cause a short product life and a bottleneck that cannot be effectively commercialized.
- the main object of the present invention is to provide a method for balancing multi-layer stress and a multilayer 1 which can balance the stress caused by the difference in area and position of different metal layers or dielectric layers to avoid warpage. song.
- the present invention provides a method for balancing the stress of a multilayer substrate for a multilayer substrate having at least a first metal layer and a second metal layer, the first area of the first metal layer being greater than The second area of the second metal layer, the one location layer where the second metal layer is disposed is provided with at least one redundant metal layer, and the area of the redundant metal layer is added to the second area to be equivalent to the first area.
- the redundant metal layer and the second metal layer are parallel to the intermediate faces of the first metal layer and the second metal layer, and correspond to the first metal layer.
- the method of the present invention can still be utilized when the first metal layer and the second metal layer further comprise at least a third metal layer.
- the second surface dielectric layer of the other surface of the plurality of layers may be provided with a redundancy corresponding to the position of the opening. Open the hole.
- the present invention also provides a multilayer substrate comprising a first metal layer and a second metal layer, the first area of the first metal layer being greater than the second area of the second metal layer, the second metal layer being The one location layer further includes at least one second redundant metal layer, and the area of the at least one second redundant metal layer plus the second area is equivalent to the first area.
- the present invention can balance the stress generated by the difference in the area and position of different metal layers or dielectric layers during the manufacturing process or in the use of the multilayer substrate, that is, to make more Layer 1
- the area and position of different metal layers or dielectric layers are relatively homogenized to avoid warpage.
- FIG. 1 is a schematic view showing a method for balancing multi-layer stress and a first embodiment of a multilayer 1 according to the present invention
- FIG. 2 is a schematic view showing a method of balancing multi-layer stress and a second embodiment of the multilayer of the present invention
- FIG. 3 is a schematic view showing a method of balancing multi-layer stress and a third embodiment of the multilayer of the present invention
- FIG. 4 is a schematic view showing a method of balancing a multi-layer reaction force of the present invention and a fourth embodiment of the multilayer;
- Figure 5 is a schematic view showing a method of balancing multilayer stress and a fifth embodiment of the multilayer of the present invention.
- DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Figure 1, a schematic diagram of a first embodiment of a method of multi-layering and balancing multilayer stress in accordance with the present invention is illustrated. The left side of Figure 1 is a three-dimensional exploded view of the multilayer, and the right side is the corresponding sectional view. 1 shows a first metal layer 102, a corresponding first dielectric layer 122, and second metal layers 1 12 and 14 and a corresponding second dielectric layer 222.
- the aforementioned first dielectric layer 122 and second dielectric layer 222 are formed by coating.
- stress imbalance occurs between the dielectric layers and the metal layers, resulting in warpage of the multilayer substrate.
- the metal layer area, thickness, and even the structural material of each layer are not the same, which causes stress imbalance, which causes warpage of the multilayer substrate.
- the concept of relatively homogenizing the area and position of different metal layers or dielectric layers by the present invention can balance the stress of the multilayer substrate and avoid warpage.
- the first area of the first metal layer 102 occupies most of the multilayer and is large.
- the second area of the second metal layer 112, 114 In the position layer where the second metal layers 112, 114 are located, the second redundant metal layers 202, 204, 206 are disposed on the premise of not affecting the design of the circuit, so that the area of the second redundant metal layer is added to the second area. After the same as the first area.
- the second redundant metal layers 202, 204, and 206 and the second metal layers 112 and 114 are parallel to the intermediate faces of the first metal layer 102 and the second metal layers 112 and 114, and correspond to the first metal layer 102. It is possible to balance the stress of the multilayer and avoid warping.
- the multilayer substrate further includes a fourth metal layer 102a, a corresponding fourth dielectric layer 122a, and fifth metal layers 112a and 114a and a corresponding fifth dielectric layer 222a.
- the fourth metal layer 102a is located outside the first metal layer 102
- the fifth metal layers 112a and 114a are located outside the second metal layer 112, 114.
- the fifth redundant metal layers 202a, 204a 206a are disposed so as not to affect the design of the circuit, so that the area of the fifth redundant metal layer Adding the fifth area is equivalent to the fourth area.
- the fifth redundant metal layers 202a, 204a, 206a and the fifth metal layers 112a, 114a correspond to the intermediate portions of the fourth metal layer 102a and the fifth metal layers 112a, 114a, corresponding to the fourth metal layer 102a.
- the present invention can also be applied to balance the multi-layer anti- stress.
- FIG. 2 a schematic diagram of a second embodiment of the method of the present invention and a method of balancing multilayer stress is illustrated.
- the left side of Figure 2 is a three-dimensional exploded view of the multilayer, and the right side is the corresponding cross-sectional view.
- the first metal layer 102, the corresponding first dielectric layer 122 and the second metal layers 112 and 114, and the corresponding second dielectric layer 222 of the multilayer substrate are shown in FIG.
- the pattern of the first metal layer 102 is complicated but the first area occupied by the first metal layer 102 is still For the second area larger than the second metal layers 112, 114, therefore, the position layer of the second metal layer 112 and 114 of the present invention is provided on the premise of not affecting the design of the circuit, and the second area is small and the distribution is trivial.
- the redundant metal layers 202, 204, 206 are still intended to have the area of the second redundant metal layer plus the second area corresponding to the first area.
- the second redundant metal layers 202, 204, 206 and the second metal layers 112, 114 are parallel to the intermediate faces of the first metal layer 102 and the second metal layers 112, 114, corresponding to the first metal layer 102, It is possible to balance the stress of the multilayer substrate to avoid warpage.
- Schematic diagram of the example Similarly, the left side of FIG. 3 is a perspective exploded view of the multilayer substrate, and the right side is a corresponding cross-sectional view.
- the multilayer 1 has a first metal layer 102, a corresponding first dielectric layer 122 and second metal layers 112 and 114, and a corresponding second dielectric layer 222.
- a third metal layer 302 and a corresponding third dielectric layer 322 are further included between the first metal layer 102 and the second metal layer 112.
- the area occupied by the third metal layer 302 is smaller than the second area occupied by the second metal layer 112, and is of course smaller than the first area occupied by the first metal layer 102.
- the third metal layer 302 and the third dielectric layer 322 are sandwiched In the meantime, the difference between the first metal layer 102 and the second metal layer 112 can be ignored.
- the area and position difference of the first metal layer 102 and the second metal layer 112 are directly considered. Just fine. That is, as described above, in terms of the overall consideration of the multilayer substrate, the inside thereof has a symmetrical structure.
- the present invention can provide a second area of the second redundant metal layer 202, 206 and a second area of a larger area on the premise that the second metal layers 112 and 114 are located without affecting the design of the circuit.
- the remaining metal layer 204 is still oriented to add the second area of the second redundant metal layer to the first area.
- the second redundant metal layers 202, 204, and 206 and the second metal layers 112 and 114 are parallel to the intermediate faces of the first metal layer 102 and the second metal layers 112 and 114, and correspond to the first metal layer 102. That is, the stress of the multilayer substrate can be balanced to avoid warpage.
- FIG. 4 a schematic diagram of a fourth embodiment of the multi-layer substrate of the present invention and a method for balancing the stress of the multi-layer substrate is illustrated.
- the left side of FIG. 4 is a perspective exploded view of the multilayer substrate, and the right side corresponds to Sectional view.
- the multilayer 1 has a first metal layer 102, a corresponding first dielectric layer 122, and second metal layers 1 12 and 14 and a corresponding second dielectric layer 222.
- the first area occupied by the first metal layer 102 is relatively larger than the second area of the second metal layer 112.
- the first redundant space 402 is disposed in the first metal layer 102 in this embodiment. 404, 406, 408, and 410, and subtracting the area of the first redundant space from the first area to be equivalent to the second area, and the metal layer 102 other than the first redundant spaces 402, 404, 406, 408, and 410
- the stress of the plurality of layers can be balanced to prevent warpage from occurring.
- the first metal layer 102 and the second metal layer 112 have a fourth dielectric layer and a fifth dielectric layer on the outer side or the inner side.
- the fourth area of the fourth metal layer is greater than the fifth area of the fifth metal layer.
- FIG. 5 a schematic diagram of a fifth embodiment of the method of multi-layered and balanced multilayer reaction of the present invention is illustrated.
- a plurality of layers of the pad layer 500 are shown, and an opening 502 is formed in the first surface dielectric layer 522.
- the multilayer layer further includes a second surface dielectric layer 524 on the other surface of the plurality of layers.
- a redundant opening 602 is disposed at the position of the second surface dielectric layer 524 corresponding to the opening 502, so that the multilayer can be balanced. The stress that prevents warpage from occurring.
- the concept of relatively homogenizing the area and position of different metal layers or dielectric layers can still be utilized by the present invention, and the redundant opening is provided at the position corresponding to the opening. Holes, which balance the stress of the multilayer substrate to avoid warpage.
- the first to fifth embodiments when manufacturing a multi-layer substrate, can be used alone or in combination with different circuit designs to relatively homogenize different metal layers or dielectric layers of the multilayer substrate. That is, it can balance the stress caused by the difference in material of different layers, so as to avoid warpage.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020107018159A KR101229956B1 (ko) | 2008-03-31 | 2008-03-31 | 다층기판의 응력 평형 방법 및 다층기판 |
EP08733855.4A EP2270851B1 (en) | 2008-03-31 | 2008-03-31 | Method of balancing multilayer substrate stress and multilayer substrate |
PCT/CN2008/000630 WO2009121200A1 (zh) | 2008-03-31 | 2008-03-31 | 平衡多层基板应力的方法及多层基板 |
JP2011501082A JP5404763B2 (ja) | 2008-03-31 | 2008-03-31 | 多層基板の応力をバランスする方法及び多層基板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2008/000630 WO2009121200A1 (zh) | 2008-03-31 | 2008-03-31 | 平衡多层基板应力的方法及多层基板 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2009121200A1 true WO2009121200A1 (zh) | 2009-10-08 |
Family
ID=41134788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2008/000630 WO2009121200A1 (zh) | 2008-03-31 | 2008-03-31 | 平衡多层基板应力的方法及多层基板 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP2270851B1 (zh) |
JP (1) | JP5404763B2 (zh) |
KR (1) | KR101229956B1 (zh) |
WO (1) | WO2009121200A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113518503A (zh) * | 2021-03-31 | 2021-10-19 | 深圳市景旺电子股份有限公司 | 多层印刷线路板及其制作方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08288316A (ja) * | 1995-04-14 | 1996-11-01 | Citizen Watch Co Ltd | 半導体装置 |
JPH1117064A (ja) * | 1997-06-24 | 1999-01-22 | Toshiba Corp | 半導体パッケージ |
US5888630A (en) * | 1996-11-08 | 1999-03-30 | W. L. Gore & Associates, Inc. | Apparatus and method for unit area composition control to minimize warp in an integrated circuit chip package assembly |
US6380633B1 (en) * | 2000-07-05 | 2002-04-30 | Siliconware Predision Industries Co., Ltd. | Pattern layout structure in substrate |
CN1400661A (zh) * | 2002-08-28 | 2003-03-05 | 威盛电子股份有限公司 | 具有平衡结构的构装集成电路 |
CN1494133A (zh) * | 2002-10-30 | 2004-05-05 | 矽品精密工业股份有限公司 | 一种防止翘曲现象发生的基板 |
US20060024921A1 (en) * | 2004-07-27 | 2006-02-02 | Jui-Tsen Huang | [method of relieving wafer stress] |
CN1797726A (zh) * | 2004-12-20 | 2006-07-05 | 全懋精密科技股份有限公司 | 半导体构装的芯片埋入基板结构及制法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0513957A (ja) * | 1991-07-02 | 1993-01-22 | Mitsubishi Electric Corp | プリント配線板 |
JPH06252556A (ja) * | 1993-02-24 | 1994-09-09 | Mitsubishi Electric Corp | 多層セラミック基板 |
JP2599674Y2 (ja) * | 1993-12-28 | 1999-09-13 | 株式会社ミツバ | 基板のノイズ対策用パターン構造 |
JP2001068860A (ja) * | 2000-08-07 | 2001-03-16 | Ibiden Co Ltd | 多層プリント配線板 |
JP2002261402A (ja) * | 2001-03-01 | 2002-09-13 | Alps Electric Co Ltd | 電子回路ユニットの回路基板 |
JP2003218279A (ja) * | 2002-01-23 | 2003-07-31 | Shinko Electric Ind Co Ltd | 回路基板およびその製造方法 |
JP2004200265A (ja) * | 2002-12-17 | 2004-07-15 | Nikon Corp | プリント配線板 |
US7652213B2 (en) * | 2004-04-06 | 2010-01-26 | Murata Manufacturing Co., Ltd. | Internal conductor connection structure and multilayer substrate |
KR20070046422A (ko) * | 2005-10-31 | 2007-05-03 | 엘지이노텍 주식회사 | 저온 동시소성 세라믹 다층기판의 실장 패드 |
JP2008071963A (ja) * | 2006-09-14 | 2008-03-27 | Denso Corp | 多層配線基板 |
-
2008
- 2008-03-31 WO PCT/CN2008/000630 patent/WO2009121200A1/zh active Application Filing
- 2008-03-31 JP JP2011501082A patent/JP5404763B2/ja active Active
- 2008-03-31 KR KR1020107018159A patent/KR101229956B1/ko active IP Right Grant
- 2008-03-31 EP EP08733855.4A patent/EP2270851B1/en not_active Not-in-force
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08288316A (ja) * | 1995-04-14 | 1996-11-01 | Citizen Watch Co Ltd | 半導体装置 |
US5888630A (en) * | 1996-11-08 | 1999-03-30 | W. L. Gore & Associates, Inc. | Apparatus and method for unit area composition control to minimize warp in an integrated circuit chip package assembly |
JPH1117064A (ja) * | 1997-06-24 | 1999-01-22 | Toshiba Corp | 半導体パッケージ |
US6380633B1 (en) * | 2000-07-05 | 2002-04-30 | Siliconware Predision Industries Co., Ltd. | Pattern layout structure in substrate |
CN1400661A (zh) * | 2002-08-28 | 2003-03-05 | 威盛电子股份有限公司 | 具有平衡结构的构装集成电路 |
CN1494133A (zh) * | 2002-10-30 | 2004-05-05 | 矽品精密工业股份有限公司 | 一种防止翘曲现象发生的基板 |
US20060024921A1 (en) * | 2004-07-27 | 2006-02-02 | Jui-Tsen Huang | [method of relieving wafer stress] |
CN1797726A (zh) * | 2004-12-20 | 2006-07-05 | 全懋精密科技股份有限公司 | 半导体构装的芯片埋入基板结构及制法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113518503A (zh) * | 2021-03-31 | 2021-10-19 | 深圳市景旺电子股份有限公司 | 多层印刷线路板及其制作方法 |
CN113518503B (zh) * | 2021-03-31 | 2022-08-09 | 深圳市景旺电子股份有限公司 | 多层印刷线路板及其制作方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20110003316A (ko) | 2011-01-11 |
EP2270851B1 (en) | 2016-12-28 |
EP2270851A1 (en) | 2011-01-05 |
JP2011517063A (ja) | 2011-05-26 |
KR101229956B1 (ko) | 2013-02-06 |
JP5404763B2 (ja) | 2014-02-05 |
EP2270851A4 (en) | 2011-06-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7223687B1 (en) | Printed wiring board and method of fabricating the same | |
US20100139965A1 (en) | Embedded circuit substrate and manufacturing method thereof | |
JP2002031883A5 (zh) | ||
TWI556703B (zh) | 多層基板及其製造方法 | |
US20130186677A1 (en) | Printed circuit board and method of manufacturing the same | |
US20150101857A1 (en) | Printed circuit board and method for manufacturing the same | |
WO2009121200A1 (zh) | 平衡多层基板应力的方法及多层基板 | |
TWI432121B (zh) | 平衡多層基板應力之方法及多層基板結構 | |
JP2711004B2 (ja) | 動的屈曲領域を有する多層回路の製造方法及び該方法により製造されたフレキシブル回路 | |
US20020036354A1 (en) | Semiconductor device | |
JPH1172848A (ja) | 透過型スクリーン | |
JPH0992980A (ja) | フレキシブル部分を有する多層プリント配線板及びその製造方法 | |
US20110212307A1 (en) | Method to decrease warpage of a multi-layer substrate and structure thereof | |
US20110212257A1 (en) | Method to decrease warpage of a multi-layer substrate and structure thereof | |
CN101547570B (zh) | 平衡多层基板应力的方法及多层基板 | |
WO2019128171A1 (zh) | 无芯板制作方法及其制造构件、支撑载体及其制作方法 | |
JP2000252625A (ja) | 多層配線基板及びその製造方法 | |
KR20160060937A (ko) | 디태치 코어기판, 그 제조 방법 및 회로기판 제조방법 | |
TWI679926B (zh) | 基板結構及其製作方法 | |
JP7136930B2 (ja) | 多層回路基板およびその製造方法 | |
TWI343775B (en) | Circuit substrate, manufacturing method of circuit substrate and printed circuit board | |
US20140138132A1 (en) | Printed circuit board and manufacturing method thereof | |
TWM589637U (zh) | 霧面乾膜結構 | |
KR100914978B1 (ko) | 반도체 소자 및 그의 제조 방법 | |
JP2003218514A (ja) | 配線基板用基材および配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08733855 Country of ref document: EP Kind code of ref document: A1 |
|
REEP | Request for entry into the european phase |
Ref document number: 2008733855 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2008733855 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 20107018159 Country of ref document: KR Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011501082 Country of ref document: JP |
|
NENP | Non-entry into the national phase |
Ref country code: DE |