1343775 ‘· 九、發明說明： • 【發明所屬之技術領域】 本發明涉及電路板技術領域，特別涉及一種線路基 板、線路基板之製作方法及電路板之製作方法。 【先前技術】 多層印刷電路板係由大於兩層之導電線路與絕緣材料 交替黏結於一起且層間導電線路按設計要求進行互連之印 鲁刷電路板。多層印刷電路板因具有裝配密度高等優點而得 到了廣泛之應用，參見文獻Takahashi，A. Ooki，N. Nagai，A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab., High density multilayer printed circuit board for HITAC M-880 » IEEE Trans, on Components, Packaging, and Manufacturing Technology, 1992，15(4): 418-425。多層印刷電路板有硬 性、軟性、軟硬結合等複數類型。多層軟性電路板由於體 積小、重量輕，可自由彎曲、捲繞或折疊等特點近來發展 ®迅速。 目前，為提高製作效率適應大批量之製作多層軟硬結 合電路板，一般係將複數線路板（軟板）與基板（硬板） 貼合，使基板外表面形成與複數線路板相對應之複數線路 區。再對該複數線路區同時進行曝光、顯影、蝕刻，於每 個線路區形成與相對應之線路板之導電線路相對應之外層 線路，以形成能實現内層與外層電連接之導電線路。於製 作外層線路時，通常採用一張光罩與整個基板對位然後完 1343775 ，成曝光。該光罩具有該複數線路區所需之線路圖形，即與 複數線路板相對應之線路圖形。由於該線路板已做好導電 線路，故該線路圖形必須根據預先設計之複數線路板與基 板之分佈位置來設計。當光罩上之線路圖形與複數線路板 準確對位時，才能於基板之每個線路區製作出位置準確之 外層線路。 准，複數線路板於與基板貼合時，由於複數次貼合過 鲁輊中可旎存在誤差，以及加熱貼合會引起線路板或基板之 不同材料發生不同程度之漲縮，從而使複數線路板於基板 之間實際分佈位置與預先設計之位置之間存在偏差，即偏 位此時，如果採用前述方法製作線路，可能出現光罩與 ，數線路板之導電線路出現對位誤差。經後續製作後，^ 仵到之軟硬結合板不能實現導電線路與外層線路良好之電 連通，嚴重地會使整個軟硬結合板報廢。 φ 【發明内容】 有鑑於此，提供一種線路基板、線路基板之製作方法 及電路板之製作方法，以解決該問題，提高内層導電線路 與外層線路之對位精度實屬必要。 以下將以實施例說明一種線路基板、線路基板之製作 方法及電路板之製作方法。 °亥線路基板，其包括第一基板及複數線路板。該第一 基板包括第-基材層及貼合於第一基材層之第一金屬層。 A複數線路板數量為n ’其具有相同導電線路，η為大於丄 8 1343775 ，之自然數。該複數線路板之導電線路貼合於第一基材層， 使複數線路板中之一線路板繞位於第一基板之旋轉中心旋 轉角度me後之導電線路與其餘（n_u個線路板中之一線 路板之導電線路重合，m為小於η之自然數，度。 該線路基板之製作方法，其包括以下步驟：首先，提 •供第一基板及複數線路板。該第一基板包括第一基材層及 貼合於第一基材層之第一金屬層。該複數線路板數t量為曰 _其設有相同之導電線路，η為大於！之自然數。然後，將複 數線路板中之一線路板壓合於第一基板上，再繞位於第一 基板之旋轉中心將第一基板旋轉角度111卜〇1為=於η之自 然數，θ=360/η度，將其餘㈤）個線路板分別於旋轉前 該-線路板所在之位置壓合於第一，使壓合後該立餘 (η-1)個線路板之導電線路分別與旋轉前該一線路板^導 電線路重合，從而形成線路基板。 該電路板之製作方法，其採㈣料基板製作線路1343775 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 [Prior Art] A multilayer printed circuit board is a printed circuit board in which two or more layers of conductive lines are alternately bonded to an insulating material and the interlayer conductive lines are interconnected as designed. Multilayer printed circuit boards have been widely used due to their high assembly density, see the literature Takahashi, A. Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab., High density. Multilayer printed circuit board for HITAC M-880 » IEEE Trans, on Components, Packaging, and Manufacturing Technology, 1992, 15(4): 418-425. Multilayer printed circuit boards are of a complex type such as hard, soft, soft and hard. Multi-layer flexible boards have recently developed rapidly due to their small size and light weight, which can be freely bent, wound or folded. At present, in order to improve production efficiency and adapt to large-scale production of multi-layer soft and hard circuit boards, generally, a plurality of circuit boards (soft boards) are bonded to a substrate (hard board), so that the outer surface of the substrate forms a plurality corresponding to the plurality of circuit boards. Line area. The plurality of line regions are simultaneously exposed, developed, and etched, and the outer layer lines corresponding to the conductive lines of the corresponding circuit boards are formed in each of the line regions to form a conductive line capable of electrically connecting the inner layer and the outer layer. When making an outer layer, a mask is usually used to align with the entire substrate and then 1343775 is exposed. The reticle has a line pattern required for the plurality of line regions, i.e., a line pattern corresponding to the plurality of circuit boards. Since the board is already electrically conductive, the pattern must be designed based on the pre-designed layout of the multiple boards and boards. When the line pattern on the reticle is accurately aligned with the plurality of circuit boards, an outer layer of accurate position can be produced in each line region of the substrate. When the plurality of circuit boards are bonded to the substrate, the errors may occur due to the plurality of times of lamination, and the heating and bonding may cause different materials of the circuit board or the substrate to be shrunk to different degrees, thereby making the plurality of lines There is a deviation between the actual distribution position of the board between the substrates and the pre-designed position, that is, the offset position. At this time, if the circuit is fabricated by the foregoing method, a misalignment error may occur between the photomask and the conductive lines of the plurality of circuit boards. After the subsequent fabrication, the soft and hard bonding board can not achieve good electrical connection between the conductive line and the outer layer, which seriously causes the entire soft and hard bonding board to be scrapped. φ [Summary of the Invention] In view of the above, a circuit board, a method of manufacturing a circuit board, and a method of manufacturing a circuit board are provided to solve the problem, and it is necessary to improve the alignment accuracy of the inner layer conductive line and the outer layer line. Hereinafter, a circuit board, a method of manufacturing the circuit board, and a method of manufacturing the circuit board will be described by way of embodiments. A circuit board comprising a first substrate and a plurality of circuit boards. The first substrate includes a first substrate layer and a first metal layer bonded to the first substrate layer. The number of A complex circuit boards is n ', which has the same conductive line, and η is a natural number greater than 丄 8 1343775. The conductive circuit of the plurality of circuit boards is adhered to the first substrate layer, and one of the plurality of circuit boards is wound around the conductive center of the rotation angle of the rotation center of the first substrate and the rest (one of the n_u circuit boards) The conductive lines of the circuit board are coincident, and m is a natural number less than η. The manufacturing method of the circuit substrate comprises the following steps: First, providing a first substrate and a plurality of circuit boards. The first substrate comprises a first base. a material layer and a first metal layer adhered to the first substrate layer. The number of the plurality of circuit boards is 曰_ which is provided with the same conductive line, and η is a natural number greater than! Then, the plurality of circuit boards are One of the circuit boards is pressed onto the first substrate, and then rotated around the center of rotation of the first substrate to rotate the first substrate by an angle of 111, 〇1 is = natural number of η, θ=360/η degrees, and the remaining (five) The circuit boards are respectively pressed to the first position at the position where the circuit board is located before the rotation, so that the conductive lines of the balance (n-1) circuit boards are respectively coincident with the conductive lines of the one circuit board before the rotation. Thereby forming a circuit substrate. The manufacturing method of the circuit board, the (four) material substrate production line
板，其包括以下步驟：首先，於線路基板定義複數加工區， 該加工區數量冑η ’每個加工區對應於一線路板。然後，於 第-金屬層表面塗佈光阻層，對複數線路板中之―、加工區 對應之光阻層進行曝光。再將線路基板繞位於第一基板2 旋轉令心旋轉角度ΓΠΘ，使其餘⑹）個加工區分別^ 轉前該-加工區曝光所在之位置’並分別對㈤）個加工 區對應之光阻層進行曝光。最後，經顯影、_，從而於 第-金屬層形成與複數線路板之導電線路相對應之導 路。 9 1343775 與先前技術相比，該線路基板之具有相同導電線路之η ' 個線路板係以一線路板之導電線路為參照物依次旋轉Θ角 分別設置其餘（η-1)個線路板之導電線路。利用該線路基 板製作電路板中進行曝光時，根據η個線路板之分佈規律， 將線路基板旋轉πιθ角，使每個線路板均位於相同之位置並 採用相同之光罩進行曝光。即進行曝光之每個線路板之導 電線路之位置相重合。該方法以分別確定η個線路板設置 於第一基板之位置以提高曝光對位之精度。另外，即使壓 * 合時存在偏位，只要每次曝光時於前一步之對位基礎上進 行微調即可對位，節約複數次曝光之時間。 【實施方式】 下面將結合附圖及實施例對本技術方案提供之線路基 板、線路基板之製作方法及電路板之製作方法作進一步詳 細說明。 圖1至圖5為電路板之製作過程，其包括以下步驟。 第一步，提供第一基板及複數線路板。 請參閱圖1及圖2，本實施例中，提供第一基板110a 及第二基板ll〇b，以備後續製作所需線路基板。第一基板 110a及第二基板110b可為軟板或硬板。第一基板110a包 括第一基材層Ula及設置於第一基材層111a表面之第一金 屬層112a。相應地，第二基板110b包括相貼合之第二基材 層111b與第二金屬層112b。該第一金屬層112a與第二金 屬層112b用於後續製作導電線路。該第一基材層111a及第 1343775 … 二基材層lllb可為單層絕緣基材層’亦可為導電線路層與 •絕緣層形成之複合基材層。當然’亦可僅提供第一基板 110a，用於製作所需線路基板，是否需要第二基板1101)根 據實際設計需要而定。 該複數線路板可為軟板或硬板’單層板或多層板’其 形狀、尺寸及數量根據實際需要而定’只要線路板已製作 好之線路即可。請參閲圖1及圖2，本實施例中’提供具有 相同導電線路之四個線路板，即第一線路板120a、第二線 •路板120b、第三線路板120c及第四線路板120d。該第一 線路板120a、第二線路板120b、第三線路板l20c及第四 線路板120d均為單層絕緣層及設置於該絕緣層相對兩表面 之導電線路構成之矩形雙面線路板。第一線路板120a具有 相對設置之第一導電線路121a及第二導電線路122a。相應 地，第二線路板120b具有相對設置之第三導電線路121b 及第四導電線路122b。第三線路板120c具有相對設置之第 •五導電線路121c及第六導電線路（圖未示）。第四線路板 120d具有相對設置之第七導電線路121d及第八導電線路 (圖未示）。其中，第一導電線路i21a、第二導電線路122a、 第三導電線路121b、第四導電線路122b、第五導電線路 121c、第六導電線路、第七導電線路121d及第八導電線路 具有相同之線路圖形。當然，線路板相對兩表面之導電線 路亦可具有不同之線路圖形。 第二步，製作線路基板1〇〇。 請參閱圖1及圖2 ’本實施例中，將第一線路板12〇a 11 1343775 之第一導電線路121a直接壓合於第一基板ll〇a之第一基 •材層111a。然後繞旋轉中心A將第一基板110a逆時針旋轉 90度，將第二線路板120b位於第一次旋轉前第一線路板 120a所在之位置’並壓合於第二基板110b ’使壓合後第二 線路板120b之第三導電線路121b及第四導電線路122b分 別與旋轉前第·線路板120a之第·導電線路121 a及第·一 導電線路122a重合。再繞旋轉令心A將第一基板ll〇a逆 時針旋轉90度，將第三線路板位於第一次旋轉前第 翁一線路板120a所在之位置，並壓合於第二基板110b，使壓 合後第三線路板120c之第五導電線路121c及第六導電線 路分別與第一次旋轉前第一導電線路121a及第二導電線路 122a重合。接著繞旋轉中心A將第一基板ll〇a逆時針旋轉 90度，將第四線路板120d位於第一次旋轉前第一線路板 120a所在之位置’並壓合於第二基板ii〇b，使壓合後第四 線路板120d之第七導電線路I21d及第八導電線路分別與 鲁第一次旋轉前第一導電線路121a及第二導電線路U2a重 合。該旋轉中心A為第一基板li〇a内之任意點，只要第一 基板110a繞該旋轉中心a旋轉後，仍有足夠大小之第一基 板110a位於第一次旋轉前第一線路板12〇a所在位置，用 於壓合第二線路板12〇b、第三線路板12〇c及第四線路板 120d即可。 然後’將第一基板ll0a之第—基材層nia直接貼合於 第:導電線路l21a、第三導電料mb、第五導電線路mc 及第七導電線路121d上，使四個線路板不相互重疊地壓合 12 ^/75 於第__ «., 暴板ll〇a與第二基板110b之間，從而形成用於製 作又面線路之線路基板100。 &果線路板相對兩表面設置之導電線路不同，只要分 Μ Μ合於同一基材層之複數線路板之導電線路相同即可。 即’貼合於第一基材層111&之第一導電線路12ia、第三導 電線路121b、第五導電線路121c與第七導電線路121d相 同’而貼合於第二基材層111b之第二導電線路122a、第四 導電線路122b、第六導電線路與第八導電線路相同。 線路板之數量可根據實際需要以及線路板相對於第一 基板110a之尺寸大小而決定，當需要壓合η (η為大於1 之自然數）個設有相同之導電線路之線路板於第一基板 110a之第一基材層iiia形成線路基板1〇〇時，其壓合過程 為：將η個線路板中之一線路板壓合於第一基板ll〇a上。 然後，繞位於第一基板110a之旋轉中心A將第一基板110a 旋轉角度πιθ，θ = 360/η度，m為小於η之自然數，將其餘 (η-1)個線路板分別於旋轉前該一線路板所在之位置壓合 於第一基板ll〇a，使壓合後該其餘（η-1)個線路板之導電 線路分別與旋轉前該一線路板之導電線路重合，從而形成 線路基板100。 該線路基板1〇〇包括第一基板ll〇a及η個線路板’ η 為大於1之自然數。該第一基板ll〇a包括第一基材層111a 及貼合於第一基材層111a之第一金屬層112a。該η個線路 板具有相同導電線路，該複數線路板之導電線路貼合於第 一基材層111a，使η個線路板中之一線路板繞位於第一基 13 1343775 板110a之旋轉中心A旋轉角度πιθ後之導電線路與其餘 (η-1)個線路板中之一線路板之導電線路重合，0=36〇/η 度，m為小於η之自然數。 為清楚說明如何對線路基板100進行電路板之製作， 本實施例中，利用相互垂直且經過旋轉中心Α之兩條虛線 將線路基板100定義出四個大小相等且相連接之加工區（如 圖1所示），即第一加工區101、第二加工區1〇2、第三加 工區103及第四加工區104。該第一加工區1〇；[、第二加工 區102、第三加工區103及第四加工區1〇4分別與該第一線 路板l2〇a、第二線路板120b、第三線路板12〇c與第四線 路板l2〇d相對應，用於製作分別與第一導電線路ma及 第二導電線路12ib、第三導電線路mb及第四導電線路 122b、第五導電線路mc及第六導電線路以及第七導電線 路121d及第八導電線路相對應之導電線路。 第步線上路基板100之金屬層塗佈光阻層。 本貫把例中，線上路基板100之第一金屬層112a製作 線路’因此於第一金屬層U2a之表面塗佈光阻層。該光阻 層可為正光阻材料或負光阻材料製成。 第=v對已塗佈光阻層之線路基板1〇〇進行曝光。 ^貫^例中，線路基板1〇〇之第一金屬層112a之四個 加工區上需製作相同之導電線路，故採用同—光罩即可完 成第-金屬2 ll2a之曝光。請參閱圖3,為降低成本且方 便知作本貫知例採用與每個加工區大小相等之光罩細， 即光罩200與四分之一第一金屬層大小相同，其具有 1343775 第一金屬層112a之第一加工區ιοί所需形成之線路圖形， 其與第一導電線路121a、第三導電線路121b、第五導電線 路121c及第七導電線路i21d相對應。 本實施例有四個加工區需要分別曝光，因此以下將分 四個步驟分別詳細說明對本實施例中已塗佈光阻層之第一 金屬層112a之四次曝光過程（請參閱圖4A至圖4D)。 a.第一次曝光。 請參閱圖3及圖4A，將光罩200與第一加工區進 行對位，使光罩200之線路圖形與第一線路板12〇a之第— 導電線路121a之位置相對應。然後對第一加工區1〇1進行 曝光，使第一加工區101對應之光阻層於光之化學作用下 發生變化，將光罩200之圖形轉移至第一加工區1〇1對應 之光阻層，用於經顯影及蝕刻後於第一加工區1〇1對應^ 第一金屬層112a形成與第一導電線路121a對應導電線 路。最後自第一加工區101取下光罩2〇〇即完成第一次曝 光。圖4A中與第一導電線路1213相交叉之虛線圖形為轉 移至第一加工區101對應之光阻層之光罩2〇〇圖形。圖犯 至圖4D中均以相同之標記方式標出轉移至每個加工區對 應之光阻層之圖形。 b ·第-一次曝光。 請參_ 4B’將已塗佈光阻層之線路基板1〇〇繞旋轉 中二A逆時針方疋轉90 ，使第二加工㊣1〇2位於與a步驟 中第-加工區101相同之位置，即與第二加工區皿相對 之第三導電線路㈣位於與a步驟中第一導電線路ma 15 1343775 完全重合之位置。然後使用光罩200與第二加工區102對 位元，重複a步驟之曝光過程完成第二次曝光，從而將光 罩200之圖形轉移至第二加工區102對應之光阻層，以經 顯影及蝕刻後於第二加工區102對應之第一金屬層112a形 成與第三導電線路121b對應之導電線路。 由於第二次曝光與第一次曝光之位置相同且使用相同 之光罩，故第二次對位只需於第一次對位之基礎上微調即 可實現精確對位，曝光只需重複與上一步相同操作即可， 因此既提高對位精度，又節省複數次曝光之時間。 c. 第三次曝光。 請參閱圖4C，將已塗佈光阻層之線路基板100繼續繞 旋轉中心A逆時針旋轉90度，使與第三加工區103對應之 第五導電線路121c位於與a步驟中第一導電線路121a完全 重合之位置。然後使用光罩200與第三加工區103對位元， 重複a步驟之曝光過程完成第三次曝光，從而將光罩200 之圖形轉移至第三加工區103對應之光阻層，以經顯影及 蝕刻後於第三加工區103對應之第一金屬層112a形成與第 五導電線路121c對應之導電線路。 d. 第四次曝光。 請參閱圖4D，將已塗佈光阻層之線路基板100繼續繞 旋轉中心A逆時針旋轉90度，使與第四加工區104相對之 第七導電線路121d位於與a步驟中第一導電線路121a完 全重合之位置。然後使用光罩200與第四加工區104對位 元，重複a步驟之曝光過程完成第四次曝光，從而將光罩 16 1343775 之光阻層，以經顯影 金屬層112a形成與 200之圖形轉移至第四加工區ι〇4對應 及钱刻後於第四加工區104對應之第一 第七導電線路121d對應之導電線路。 當然，b至d步驟中線路基板1〇〇亦可繞旋轉中心a 順時針方向依次旋轉，只要使第三導電線路121b、第五導 電線路121c及第七導電線路121(1均有機會位於與a步驟 中第一導電線路121a相同位置即可。 着 如果對貼合於第一基板11〇3之η個線路板形成之線路 基板1〇〇進行曝光，其中線路基板定義複數加工區，每個 加工區對應於一線路板。首先於第一金屬層112&表面塗佈 光阻層。然後，對η個線路板中之一加工區對應之光阻層 進行曝光。再將線路基板1〇〇繞位於第一基板11〇a之旋^ 中心A旋轉角度ηιθ ’使其餘（n-D個加工區分別位於旋 轉前該一加工區曝光所在之位置，並分別對其餘（nq)個 加工區對應之光阻層進行曝光，從而將光罩2〇〇之圖形轉 籲移至光阻層，以經顯影、蝕刻於第一金屬層U2a形成與η 個線路板之導電線路相對應之導電線路。 由於線路板相對兩表面具有相同之導電線路，而第二 基板110b之第二金屬層112b所需製作之導電線路與第一 基板110a之第一金屬層112a所需製作之導電線路相同。因 此重複第三步及第四步之操作於第二金屬層112!?形成光阻 層並對其進行曝光，將光罩200之圖形轉移至光阻層上， 以經顯影及蝕刻於第二金屬層U2b形成分別與第二導電線 路122a、第四導電線路122b、第六導電線路及第八導電線 17 1343775 路相對應之導電線路。 請參閱圖5，對已曝光之線路基板1〇〇進行顯影及蝕 刻，使第一金屬層112a與第二金屬層112b經顯影及蝕刻 形成相應之第一外層導電線路31〇及第二導電線路32〇。具 •體地，第一外層導電線路310包括與第一導電線路12u、 第三導電線路121b、第五導電線路121c及第七導電線路 121d相對應之導電線路，第二導電線路32〇包括與第二導 鲁電線路122a、第四導電線路122b、第六導電線路及第八導 電線路相對應之導電線路。最後去除光阻從而完成包括第 一外層導電線路310及第二導電線路32〇之電路板3〇〇之 製作。 後續還可根據實際需要，進一步對電路板3〇〇選擇性 地進行其他製作，例如鑽孔、電鍍、印刷文字、防焊曝光 等。其中，如果該製作有需要對位元元之步驟均可採用該 電路板之製作方法中第四步曝光步驟中之對位元方法來完 _成。最後切割電路板300,從而完成最終電路板產品之: 製作過程。 綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本技術方案實施例提供之線路基板之仰視圖。 18 1343775 圖2係沿圖1中V-V線之線路基板之剖面圖。 圖3係本技術方案實施例提供之光罩之俯視圖。 圖4A係本技術方案實施例提供之第一次曝光後線路 基板仰視圖。 圖4B係本技術方案實施例提供之第二次曝光後線路 基板仰視圖。 圖4C係本技術方案實施例提供之第三次曝光後線路 基板仰視圖。 圖4D係本技術方案實施例提供之第四次曝光後線路 基板仰視圖。 圖5係本技術方案實施例提供之電路板之剖面圖。 【主要元件符號說明】 線路基板 100 第一基板 110a 第二基板 110b 第一基材層 111a 第一金屬層 112a 第二基材層 111b 第二金屬層 112b 第一線路板 120a 第二線路板 120b 第三線路板 120c 第四線路板 120d 19 1343775 第一導電線路 第二導電線路 第三導電線路 第四導電線路 第五導電線路 第七導電線路 第一加工區 第二加工區 •’第三加工區 第四加工區 光罩 電路板 第一外層導電 第二外層導電 121a 122a 121b 122b 121c 121d 101 102 103 104 200 300 線路 310 線路 320 20The board includes the following steps: First, a plurality of processing areas are defined on the circuit substrate, and the number of processing areas 胄η' corresponds to a circuit board. Then, a photoresist layer is coated on the surface of the first metal layer to expose the photoresist layer corresponding to the processing region in the plurality of wiring boards. Then, the circuit substrate is wound around the first substrate 2 to rotate the rotation angle ΓΠΘ, so that the remaining (6)) processing regions are respectively rotated to the position where the processing region is exposed and respectively correspond to (5) the photoresist layer corresponding to the processing region. Exposure. Finally, the developing, _, thereby forming a guide corresponding to the conductive lines of the plurality of wiring boards in the first metal layer. 9 1343775 Compared with the prior art, the η ' circuit boards of the circuit substrate having the same conductive line are electrically connected with the conductive lines of one circuit board as the reference objects, and the remaining (η-1) circuit boards are respectively electrically conductive. line. When the circuit board is used for exposure, the circuit substrate is rotated by an angle of πιθ according to the distribution rule of the n circuit boards, so that each of the circuit boards is located at the same position and exposed by the same mask. That is, the positions of the conductive lines of each of the boards subjected to exposure coincide. The method determines the position where the n circuit boards are disposed on the first substrate to improve the accuracy of the exposure alignment. In addition, even if there is a bias at the time of pressing, as long as the fine adjustment is performed on the basis of the previous step at each exposure, the alignment can be performed, and the time of the plurality of exposures can be saved. [Embodiment] Hereinafter, a circuit board, a circuit board manufacturing method, and a circuit board manufacturing method provided by the present technical solution will be further described in detail with reference to the accompanying drawings and embodiments. 1 to 5 show the manufacturing process of the circuit board, which includes the following steps. In the first step, a first substrate and a plurality of circuit boards are provided. Referring to FIG. 1 and FIG. 2, in the embodiment, the first substrate 110a and the second substrate 110b are provided for subsequent fabrication of the required circuit substrate. The first substrate 110a and the second substrate 110b may be a soft board or a hard board. The first substrate 110a includes a first substrate layer U1a and a first metal layer 112a disposed on a surface of the first substrate layer 111a. Correspondingly, the second substrate 110b includes a second substrate layer 111b and a second metal layer 112b which are attached to each other. The first metal layer 112a and the second metal layer 112b are used to subsequently fabricate conductive lines. The first base material layer 111a and the first base material layer 111b may be a single-layer insulating base material layer' or a composite base material layer formed of a conductive circuit layer and an insulating layer. Of course, it is also possible to provide only the first substrate 110a for fabricating the desired circuit substrate, and whether the second substrate 1101 is required, depending on actual design requirements. The plurality of circuit boards may be soft boards or hard boards 'single-layer boards or multi-layer boards' whose shape, size and number are determined according to actual needs' as long as the circuit board has been fabricated. Referring to FIG. 1 and FIG. 2, in the present embodiment, 'four circuit boards having the same conductive line, that is, the first circuit board 120a, the second line board 120b, the third circuit board 120c, and the fourth circuit board are provided. 120d. The first circuit board 120a, the second circuit board 120b, the third circuit board l20c, and the fourth circuit board 120d are each a rectangular double-sided circuit board composed of a single-layer insulating layer and conductive lines disposed on opposite surfaces of the insulating layer. The first circuit board 120a has a first conductive line 121a and a second conductive line 122a disposed opposite each other. Correspondingly, the second circuit board 120b has oppositely disposed third conductive lines 121b and fourth conductive lines 122b. The third circuit board 120c has a fifth conductive line 121c and a sixth conductive line (not shown) disposed opposite to each other. The fourth circuit board 120d has a seventh conductive line 121d and an eighth conductive line (not shown) disposed opposite to each other. The first conductive line i21a, the second conductive line 122a, the third conductive line 121b, the fourth conductive line 122b, the fifth conductive line 121c, the sixth conductive line, the seventh conductive line 121d, and the eighth conductive line have the same Line graphics. Of course, the conductive lines of the circuit board relative to the two surfaces may also have different line patterns. In the second step, the circuit substrate 1 is fabricated. Referring to FIG. 1 and FIG. 2', in the embodiment, the first conductive line 121a of the first circuit board 12A11 1343775 is directly pressed against the first substrate layer 111a of the first substrate 110a. Then, the first substrate 110a is rotated 90 degrees counterclockwise around the rotation center A, and the second circuit board 120b is located at the position where the first circuit board 120a is located before the first rotation and is pressed against the second substrate 110b to be pressed. The third conductive line 121b and the fourth conductive line 122b of the second wiring board 120b overlap with the first conductive line 121a and the first conductive line 122a of the pre-rotation first wiring board 120a. Revolving the rotation causes the core A to rotate the first substrate 11A counterclockwise by 90 degrees, and the third circuit board is located at the position of the first circuit board 120a before the first rotation, and is pressed against the second substrate 110b. The fifth conductive line 121c and the sixth conductive line of the third circuit board 120c after pressing are respectively overlapped with the first conductive line 121a and the second conductive line 122a before the first rotation. Then, the first substrate 11A is rotated counterclockwise by 90 degrees around the rotation center A, and the fourth circuit board 120d is located at the position where the first circuit board 120a is located before the first rotation and is pressed against the second substrate ii〇b. The seventh conductive line I21d and the eighth conductive line of the fourth circuit board 120d after pressing are respectively overlapped with the first conductive line 121a and the second conductive line U2a before the first rotation. The rotation center A is an arbitrary point in the first substrate li〇a. As long as the first substrate 110a rotates around the rotation center a, the first substrate 110a of sufficient size is still located before the first rotation of the first circuit board 12〇. a location for pressing the second circuit board 12〇b, the third circuit board 12〇c, and the fourth circuit board 120d. Then, the first substrate layer nia of the first substrate 110a is directly bonded to the first conductive line 126a, the third conductive material mb, the fifth conductive line mc, and the seventh conductive line 121d, so that the four circuit boards do not mutually 12 ^ / 75 is overlapped and laminated between the __ «., the slab ll 〇 a and the second substrate 110 b to form a circuit substrate 100 for making a further line. & The circuit board is different from the conductive lines disposed on the two surfaces, as long as the conductive lines of the plurality of circuit boards that are coupled to the same substrate layer are the same. That is, the first conductive trace 12ia, the third conductive trace 121b, the fifth conductive trace 121c, and the seventh conductive trace 121d which are bonded to the first base material layer 111& are bonded to the second base material layer 111b. The two conductive lines 122a, the fourth conductive line 122b, and the sixth conductive line are the same as the eighth conductive line. The number of circuit boards can be determined according to actual needs and the size of the circuit board relative to the first substrate 110a. When it is required to press η (n is a natural number greater than 1), the circuit boards having the same conductive lines are first. When the first substrate layer iiia of the substrate 110a forms the circuit substrate 1 ,, the pressing process is: pressing one of the n circuit boards onto the first substrate 11a. Then, the first substrate 110a is rotated by an angle πιθ, θ = 360/η degrees around the rotation center A of the first substrate 110a, m is a natural number smaller than η, and the remaining (η-1) circuit boards are respectively before the rotation. The position of the circuit board is pressed against the first substrate 11a, so that the conductive lines of the remaining (n-1) circuit boards are respectively coincident with the conductive lines of the circuit board before the rotation, thereby forming a line. Substrate 100. The circuit substrate 1A includes a first substrate 11a and n circuit boards 'n is a natural number greater than one. The first substrate 11a includes a first substrate layer 111a and a first metal layer 112a bonded to the first substrate layer 111a. The n circuit boards have the same conductive line, and the conductive lines of the plurality of circuit boards are attached to the first base material layer 111a, so that one of the n circuit boards is wound around the rotation center A of the first base 13 1343775 board 110a. The conductive line after the rotation angle πιθ coincides with the conductive line of one of the remaining (n-1) circuit boards, 0=36〇/η degrees, and m is a natural number smaller than η. In order to clearly explain how to fabricate the circuit board 100, in this embodiment, four circuit boards 100 of equal size and connected are defined by two dashed lines perpendicular to each other and passing through the center of rotation (see figure 1)), that is, the first processing zone 101, the second processing zone 1〇2, the third processing zone 103, and the fourth processing zone 104. The first processing area 1〇; [the second processing area 102, the third processing area 103, and the fourth processing area 1〇4 are respectively associated with the first circuit board 12a, the second circuit board 120b, and the third circuit board 12〇c corresponds to the fourth circuit board l2〇d, for making the first conductive line ma and the second conductive line 12ib, the third conductive line mb and the fourth conductive line 122b, the fifth conductive line mc and the first The six conductive lines and the seventh conductive line 121d and the eighth conductive line correspond to the conductive lines. The metal layer of the first line substrate 100 is coated with a photoresist layer. In the present example, the first metal layer 112a of the line substrate 100 is formed as a line. Therefore, a photoresist layer is applied on the surface of the first metal layer U2a. The photoresist layer can be made of a positive photoresist material or a negative photoresist material. The first =v exposes the wiring substrate 1 to which the photoresist layer has been applied. In the example, the same conductive line needs to be formed on the four processing areas of the first metal layer 112a of the circuit substrate 1 , so that the exposure of the first metal ll2a can be completed by using the same mask. Referring to FIG. 3, in order to reduce the cost and conveniently know that the reticle is equal in size to each processing area, that is, the reticle 200 is the same size as the quarter first metal layer, and has 1343775 first. The circuit pattern to be formed in the first processing region ιοί of the metal layer 112a corresponds to the first conductive line 121a, the third conductive line 121b, the fifth conductive line 121c, and the seventh conductive line i21d. In this embodiment, four processing areas need to be separately exposed. Therefore, the four exposure processes of the first metal layer 112a of the photoresist layer coated in this embodiment will be described in detail in four steps (please refer to FIG. 4A to FIG. 4D). a. First exposure. Referring to Figures 3 and 4A, the mask 200 is aligned with the first processing zone such that the wiring pattern of the mask 200 corresponds to the position of the first conductive line 121a of the first wiring board 12A. Then, the first processing area 1〇1 is exposed, so that the photoresist layer corresponding to the first processing area 101 is changed under the action of light, and the pattern of the photomask 200 is transferred to the light corresponding to the first processing area 1〇1. The resist layer is used to form a conductive line corresponding to the first conductive line 121a corresponding to the first metal layer 112a in the first processing area 1〇1 after development and etching. Finally, the first exposure is completed by removing the mask 2 from the first processing zone 101. The dotted line pattern intersecting the first conductive line 1213 in Fig. 4A is a mask 2 pattern transferred to the photoresist layer corresponding to the first processing area 101. The figure is shown in Figure 4D in the same way as the pattern of the photoresist layer transferred to each processing area. b · First exposure. Referring to _ 4B', the circuit substrate 1 coated with the photoresist layer is rotated 90 degrees counterclockwise, so that the second processed positive 1 〇 2 is located in the same manner as the first processing region 101 in step a. The position, i.e., the third conductive line (4) opposite the second processing zone, is located at a position that completely coincides with the first conductive line ma 15 1343775 in step a. Then, using the mask 200 and the second processing region 102, the exposure process of step a is repeated to complete the second exposure, thereby transferring the pattern of the mask 200 to the photoresist layer corresponding to the second processing region 102 for development. And after the etching, the first metal layer 112a corresponding to the second processing region 102 forms a conductive line corresponding to the third conductive line 121b. Since the second exposure is the same as the first exposure and the same mask is used, the second alignment can be precisely adjusted based on the first alignment, and the exposure only needs to be repeated. The same operation can be performed in the previous step, so that the alignment accuracy is improved and the time of multiple exposures is saved. c. The third exposure. Referring to FIG. 4C, the circuit substrate 100 coated with the photoresist layer is further rotated 90 degrees counterclockwise around the rotation center A, so that the fifth conductive line 121c corresponding to the third processing region 103 is located in the first conductive line with the step a. 121a is completely coincident. Then, the photomask 200 and the third processing region 103 are used to align the pixel, and the exposure process of step a is repeated to complete the third exposure, thereby transferring the pattern of the reticle 200 to the photoresist layer corresponding to the third processing region 103 for development. After the etching, the first metal layer 112a corresponding to the third processing region 103 forms a conductive line corresponding to the fifth conductive line 121c. d. Fourth exposure. Referring to FIG. 4D, the circuit substrate 100 coated with the photoresist layer is further rotated 90 degrees counterclockwise around the rotation center A, so that the seventh conductive line 121d opposite to the fourth processing region 104 is located in the first conductive line with the a step. 121a is completely coincident. Then, the photomask 200 and the fourth processing region 104 are used to align the pixel, and the exposure process of step a is repeated to complete the fourth exposure, thereby forming the photoresist layer of the photomask 16 1343775 into the pattern of the developed metal layer 112a and 200. The conductive line corresponding to the first seventh conductive line 121d corresponding to the fourth processing area 104 is corresponding to the fourth processing area ι4. Of course, in the step b to d, the circuit substrate 1 〇〇 can also be rotated clockwise around the rotation center a, as long as the third conductive line 121b, the fifth conductive line 121c, and the seventh conductive line 121 (1 have a chance to be located In the step a, the first conductive line 121a may be in the same position. If the circuit substrate 1A formed by the n circuit boards attached to the first substrate 11〇3 is exposed, wherein the circuit substrate defines a plurality of processing areas, each The processing area corresponds to a circuit board. First, a photoresist layer is coated on the surface of the first metal layer 112 & then, the photoresist layer corresponding to one of the n circuit boards is exposed. Then the circuit substrate is 〇〇 Rotating the center A rotation angle ηιθ ' of the first substrate 11〇a to make the rest (nD processing areas are respectively located at the position where the processing area is exposed before the rotation, and respectively corresponding to the remaining (nq) processing areas The resist layer is exposed to transfer the pattern of the mask 2 to the photoresist layer to be developed and etched into the first metal layer U2a to form a conductive line corresponding to the conductive lines of the n boards. board The conductive lines prepared for the second metal layer 112b of the second substrate 110b are the same as those of the first metal layer 112a of the first substrate 110a. Therefore, the third step is repeated. And the fourth step operates on the second metal layer 112 to form a photoresist layer and exposes the pattern, and transfers the pattern of the mask 200 onto the photoresist layer to be developed and etched into the second metal layer U2b to form respectively. a conductive line corresponding to the second conductive line 122a, the fourth conductive line 122b, the sixth conductive line, and the eighth conductive line 17 1343775. Referring to FIG. 5, the exposed circuit substrate 1 is developed and etched, The first metal layer 112a and the second metal layer 112b are developed and etched to form corresponding first outer conductive lines 31 and second conductive lines 32. The first outer conductive line 310 includes the first conductive The conductive line of the line 12u, the third conductive line 121b, the fifth conductive line 121c, and the seventh conductive line 121d, and the second conductive line 32 includes a second conductive line 122a and a fourth conductive line 122. b, the sixth conductive line and the eighth conductive line corresponding to the conductive line. Finally, the photoresist is removed to complete the fabrication of the circuit board 3 including the first outer conductive line 310 and the second conductive line 32. In actual need, the circuit board 3 can be further selectively fabricated, such as drilling, electroplating, printing text, solder resist exposure, etc., wherein the circuit board can be used if the fabrication requires a step of the alignment element. In the manufacturing method, the bit method in the fourth step of the exposing step is completed. Finally, the circuit board 300 is cut, thereby completing the final circuit board product: the manufacturing process. In summary, the invention has indeed met the invention patent. Essentials, 提出 file a patent application in accordance with the law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the present invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a bottom view of a circuit substrate provided by an embodiment of the present technical solution. 18 1343775 FIG. 2 is a cross-sectional view of the circuit substrate taken along line V-V of FIG. 1. 3 is a top plan view of a reticle provided by an embodiment of the present technical solution. 4A is a bottom view of the circuit substrate after the first exposure provided by the embodiment of the present technical solution. 4B is a bottom view of the circuit substrate after the second exposure provided by the embodiment of the present technical solution. 4C is a bottom view of the circuit substrate after the third exposure provided by the embodiment of the present technical solution. 4D is a bottom view of the circuit substrate after the fourth exposure provided by the embodiment of the present technical solution. FIG. 5 is a cross-sectional view of a circuit board provided by an embodiment of the present technical solution. [Main element symbol description] circuit substrate 100 first substrate 110a second substrate 110b first substrate layer 111a first metal layer 112a second substrate layer 111b second metal layer 112b first circuit board 120a second circuit board 120b Three circuit board 120c fourth circuit board 120d 19 1343775 first conductive line second conductive line third conductive line fourth conductive line fifth conductive line seventh conductive line first processing area second processing area • 'third processing area number Four processing zone reticle circuit board first outer layer conductive second outer layer conductive 121a 122a 121b 122b 121c 121d 101 102 103 104 200 300 line 310 line 320 20