1358251 九、發明說明： -【發明所屬之技術領域】 - 本發明涉及電路板製造技術，尤其涉及一種具有較好 :平整度之電路板預製品以及一種可減少電路板翹曲度之電 .路板組裝方法。 【先前技術】 於資訊、通訊及消費性電子產業中，電路板為所有電 子產品不可或缺之基本構成要件。隨著電子產品往小型 籲化、高速化方向發展，電路板亦從單面電路板往雙面電路 板、多層電路板方向發展。多層電路板由於具有較多佈線 面積與較高裝配密度而得到廣泛應用，請參見Takahashi，A. 等人於 1992 年發表於 IEEE Trans, on Components, Packaging, and Manufacturing Technology 之文獻 “High density multilayer printed circuit board for HITAC M〜880” 。 I 電路板之製作組裝工藝通常包括下料、形成導電圖形 與導通孔、鍍金、成型、組裝等步驟。下料係指將原材料 如覆銅層壓板裁切成便於生產之適當尺寸之基板，該基板 包括與電路板產品相對應之成品區以及用於支撐成品區以 便於放置基板之廢料區。其次，將廢料區之銅層去除並於 成品區形成導電圖形與導通孔》即》將成品區之銅層製成 包括導電線路與連接端點之圖案，並實現層間導電線路之 互連。再次，進行成型工序即以模切或衝壓去除廢料區後 即可獲得電路板產品。最後，於電路板產品上組裝上電子 U58251 儿器件，實現電子元器件與電路板產品之訊號連接，以獲 知、、且裝有電子元益件之電路板成品。惟，以上工藝具有如 、下缺點：第一，由於基板中廢料區沒有銅層，而成品區具 ·.有銅層，造成成品區與廢料區之製作工藝不同，易於造成 ·:成品區與廢料區漲縮不一致而引起整個電路板基板之翹 曲，並且通常來說，電路板基板之兩端上鍾較為嚴重，中 央部位則較為平坦；第二，若電路板發生翹曲時進行組装， 籲則可忐造成電路板與電子元器件不能精確對位元與有效連 接，從而造成組裝失效。 有鑑於此，提供一種具有較好平整度之電路板預製品 以及一種可減少電路板之翹曲度、提高電路板組裝效果之 電路板組裘方法實屬必要。 【發明内容】 以下將以實施例說明一種電路板預製品以及電路板組 裝方法。 # 一種電路板預製品，其包括成品區與位於成品區周圍 之廢料區，該成品區與廢料區均具有導電層，該成品區之 .導電層形成有導電圖形，該廢料區之導電層厚度隨著與成 品區中心之距離之增大而增加。 一種電路板組裝方法，其包括以下步驟：提供如上該 電路板預製品；於成品區組裝電子元器件；去除廢料區， 以獲得組裝有電子元器件之電路板成品。 本技術方案之電路板預製品中，首先，廢料區亦具有 導電層’從而使得廢料區亦具有與成品區相似之生產製 1358251 程，從而可減輕因成品區與廢料區製作工藝不同而引起之 组曲，其次，廢料區之導電層厚度隨者與成品區中心之距 -離之增大而增加，使得廢料區中越遠離成品區中心之部分 •.具有越大之重量，從而該部分之重量可牵制電路板預製品 -之兩端以減輕電路板預製品之翹曲度，並使得整個電路板 預製品具有較好平整度。本技術方案之電路板組裝方法 中，利用先於成品區組裝電子元器件再去除廢料區之工 藝，使得組裝電子元器件時成品區處於較為平坦之狀態， *從而保證電子元器件與電路板之對位精度與組裝精度，使 得電路板具有較好組裝效果。 【實施方式】 下面將結合附圖及複數實施例，對本技術方案提供之 電路板預製品以及電路板組裝方法作進一步之詳細說明。 請一併參閱圖1及圖2,本技術方案第一實施例提供之 電路板預製品10包括成品區101與廢料區102。 φ 該電路板預製品10係指已進行導電線路工序、尚未進 行成型工序之電路板。電路板預製品10可為單面電路板、 雙面電路板或者多層電路板。本實施例中，電路板預製品 10為長方形之單面電路板，其包括導電層11與絕緣層12。 該導電層11可為銅層、銀層或金層，本實施例中為銅層。 該絕緣層12可為硬性樹脂層，如環氧樹脂、玻纖布等，亦 可為柔性樹脂層，如聚醯亞胺（Polyimide，PI )、聚乙烯對 笨二曱酸乙二醇酉旨（Polyethylene Terephtalate，PET)、聚四氟 乙稀（Teflon)、聚硫胺（Polyamide)、聚甲基丙烯酸曱酯 1358251. (Polymethylmethacrylate)、聚碳酸酉旨（Polycarbonate)或聚醯 、亞胺-聚乙烯-對苯二甲酯共聚物（Polyamide ' polyethylene-terephthalate copolymer)等。 該成品區101係指電路板預製品10中與最後成型之電 :路板成品外型相對應之區域。本實施例中，該成品區 為長方形，位於電路板預製品10之中央部位。該廢料區102 係指電路板預製品10中位於成品區101周圍，於生產製造 鲁完成後將進行去除之區域，用於生產製造過程中給成品區 101提供支撐’並起到便於放置整個電路板預製品10之作 用。 該導電層11包括於成品區101之導電圖形部U1與於 廢料區102之板翹校正部112。該導電圖形部lu與板翹校 正部112位於同一平面，均附著於絕緣層12之表面。該導 電圖形部111係指由導電層U形成之、包括導電線路二n 與連接端點1112之導電圖形，用於實現訊號傳輸以及與電 #子元器件連接。該板翹校正部112之厚度隨著與成品區\〇ι 中心之距離之增大而增加。該成品區1〇1中心係指成品區 101之幾何中心。由於一般來說，電路板預製品1〇中越遠 離成品區101中心之部分之翹曲度越大，板翹校正部 厚度之增加使得廢料區1〇2距成品區1〇1越遠之部分具有 越大之重量，因此，廢料區102之重量變化規律與電路板 預製品10之翹曲度變化規律相對應。 由 部112之重量可牽制電路板預製品10中遠離成品=二 心之部分之翹曲度，因此，板翹校正部112可減輕電路板 1358251 預製品10兩端之上翹，校正電路板預製品10之翹曲度， •使得整個電路板預製品10具有較好之平整度。 ' 板翹校正部112可藉由研磨拋光、電解拋光等處理方 \法使得厚度隨著與成品區101中心之距離之增大而連續地 :呈線性或非線性增加，亦可藉由影像轉移工序以及電鍍或 蝕刻工序使得厚度隨著與成品區101中心之距離之增大而 斷續地呈階梯性增加。本實施例中，板翹校正部112之厚 度呈階梯性增加，其具有一第一表面112a以及複數與第一 鲁表面112a平行之第二表面112b，該第一表面112a與絕緣 層12接觸，該複數第二表面112b與第一表面112a之間距 依次增加。該第二表面112b之數量不限，本實施例中為四 個。 具體地，板翹校正部112依次包括第一導電材料層 1121、第二導電材料層1122、第三導電材料層1123以及第 四導電材料層1124。該四個第二表面112b依次位於第一導 $電材料層1121、第二導電材料層1122、第三導電材料層1123 以及第四導電材料層1124。亦即，該第一導電材料層1121 附著於絕緣層12,且遍佈整個廢料區102。該第二導電材 料層1122附著於第一導電材料層1121，其分佈面積介於第 一導電材料層Π21與第三導電材料層1123之間，且僅分 佈於廢料區102中遠離成品區101之區域。該第三導電材 料層1123位於第二導電材料層1122與第四導電材料層 1124之間，其分佈面積亦介於第二導電材料層1122與第四 導電材料層1124之間，且分佈於廢料區102中更遠離成品 1358251 區101之區域。該第四導電材料層1124之分佈面積最小， -且分佈於廢料區102中最遠離成品區101之區域。 - 該複數第二表面112b與第一表面112a之間距之增加 二幅度不限，即，該第一導電材料層1121、第二導電材料層 :1122、第三導電材料層1123以及第四導電材料層1124之 厚度不限。本實施例中，該複數第二表面112b與第一表面 112a之間距等幅增加，且該第一導電材料層1121之厚度與 導電圖形部111之厚度相同，即板翹校正部112之最小厚 @度與導電圖形部111之厚度相同，且該第一導電材料層 1121、第二導電材料層1122、第三導電材料層1123以及第 四導電材料層1124之厚度亦相同。 當然，第一導電材料層1121之厚度與導電圖形部111 之厚度、第二導電材料層1122之厚度亦可不相同，該第二 導電材料層1122、第三導電材料層1123以及第四導電材料 層1124之厚度亦可不同。例如，第三導電材料層1123之 鲁厚度可介於第二導電材料層1122與第四導電材料層1124 之間，即第二導電材料層1122、第三導電材料層1123以及 第四導電材料層1124之厚度可逐漸增加，以使得廢料區102 中距成品區101愈遠之部分具有愈大之重量，以可更好地 牽制電路板預製品10中遠離成品區101中心之部分之翹曲 度。 本技術方案第一實施例所示之電路板預製品10可藉由 如下步驟製作： 首先，請參閱圖3，提供一覆銅基板100，其具有成品 11 1358251 區101以及廢料㊣102。該覆銅基板1〇〇為單面覆銅基板， 其包括一第一導電材料層1121與一絕緣層12。 。。其-人，凊參閱圖4,藉由影像轉移工序與蝕刻工序將成 ..σσ區ι〇1之第一導電材料層1121形成導電圖形部m。 • 再次，藉由影像轉移工序與電鍍工序於廢料區102形 成板龜校正部112。 —第一步，請一併參閱圖4及圖5,於覆銅基板；L00表面 藉由貼覆或塗覆形成光阻層13，使得成品區ι〇ι之導電圖 形。卩111與廢料區1〇2之第一導電材料層均被光阻層 13覆蓋。本實施例中，該光阻層13為正型光阻。當然，其 亦可為負型光阻。 第二步，請一併參閱圖1及圖藉由光罩14對光阻 層13進行曝光。該光罩14中與廢料區1〇2對應之部分具 有與第二導電材料層1122相對應之開口 14〇。曝光後，與 開口 140相對應之、經過光線照射之光阻層13發生分解反 籲應’未經光線照射之光阻層13則不發生反應。 第三步，將電路板基板1〇浸置於顯影液中，發生分解 反應之光阻層13被溶解，裸露出其下之銅箔層1121，而未 發生为解反應之光阻層13則不被溶解，仍附著於導電圖形 部111以及銅箔層1121之表面，如圖7所示。 第四步，將電路板基板10浸置於電鍍槽（圖未示）中， 使得電鍍槽中之導電材料沉積於未被光阻層13覆蓋之銅猪 層1121表面，即，於廢料區102與開口 ι4〇相對應之區域 鍍上第二導電材料層1122，如圖8所示。 12 1358251. 第五步，請一併參閱圖8及圖9,移除殘留於第一導電 •材料層1121以及導電圖形部111表面之光阻層13,即可獲 -得具有第一導電材料層1121以及第二導電材料層1122之 .電路板半成品。 ; 第六步，重複如上步驟以於第二導電材料層1122上沉 _ 積形成第三導電材料層1123,並於第三導電材料層1123上 沉積形成第四導電材料層1124。從而，即可於廢料區102 形成包括第一導電材料層1121、第二導電材料層1122、第 ®三導電材料層1123以及第四導電材料層1124之板翹校正 部112，並形成於成品區101具有導電圖形部111、於廢料 區102具有板翹校正部112之導電層11，從而獲得包括上 述導電層11之電路板預製品10，如圖1所示。 請參閱圖10,本技術方案第二實施例提供之電路板預 製品20與第一實施例提供之電路板預製品10大致相同， 其不同之處在於，板翹校正部212之最大厚度與導電圖形 •部211之厚度相同，即，廢料區202之導電層21之最大厚 度與導電圖形之厚度相同。本實施例中，廢料區202之導 電層21厚度之階梯性變化可於將成品區201之導電層21 形成導電圖形後，藉由對廢料區202之導電層21進行多次 影像轉移工序與多次蝕刻工序實現。 請參閱圖11，本技術方案第三實施例提供之電路板預 製品30與第二實施例提供之電路板預製品20大致相同， 其不同之處在於，板翹校正部312之厚度隨著與成品區301 中心之距離之增大而連續線性增加。板翹校正部312具有 13 1358251 相對之第一表面312a與第二表面312b。該第一表面312& 為平面’其與絕緣層32接觸。該第二表面3l2b亦為平面， 且與第一表面312a相交。本實施例中，板翹校正部312厚 度之連續變化可藉由對廢料區3〇2之導電層進行多次磨蝕 或拋光實現。 當然，該第二表面312b亦可為曲面，即，板翹校正部 12之厚度亦可隨耆與成品區301中心之距離之增大而連 續呈非線性關係增加，僅需板翹校正部312之厚度變化規 律與電路板預製品3G之麵曲度變化規律相對應，從而可較 好地牽制電路板預製品3〇兩端之翹曲即可。 本技術方案還提供一種電路板組裝方法，以下僅以第 一實施例之電路板預製品10為例進行說明。 首先，請再次參閱圖i，提供如第一實施 板預製品10。 Μ 其次，請一併參閱圖12及圖13，於成品區101组 子元器件40。 、电 當然，於組裝電子元器件4〇之前，還可對電路板預製 品1〇進行鐘金、塗覆防焊層、文字印刷等工序。 製 於電路板預製品1〇之成σ Ρ 1Λ1〜壯+ 7 將雷子亓哭心0壯 農電子元器件係指 α 、，裝於成品區101中與導電圖形部1η f應之位置。將電子元器件組裝於成品區1〇1之方法^為 表面貼裝、覆晶構Μ其他方法，^了為 以及組裝之要求視電子4件之類型 疋。該電子元器件為用於實 功能之器件，呈可处 ”了為積體電路晶片，亦可為電容電感元件， 1358251 ，可=他器件。電子元器件之形狀結構亦不限。 -藉^ 實施例中，電子元时為長方體形之 片40,其具有複數與導電接點⑽相對應之組 為焊錫凸塊41，藉由貼合頭（圖未 -=將積體電路晶片40之複數焊錫凸塊41 一一對庫貼人 接復點1112，再經過回焊實現焊锡凸塊Μ與㈣ 口Flm之牛固連接，從而將積體電路晶片覆晶構襄於成 得組裝有電子元器件之電路板預組裝品-， 再次’請-併參_ 13及圖14，去除廢料區搬，以 又侍組裝有電子元器件40之電路板成品10b。 以衝裁模具、銳刀、雷射或其他工具切割成品區而 二廢料區102之邊界，以使廢料區1〇2掉落去除，即可獲 4細震有積體電路晶片4〇之電路板成品⑽。當然，獲得 電路板成品l〇b後，還可進行後續檢驗、進一步組裝等工 藝。 ^， 本技術方案之電路板預製品中，首先，廢料區亦具有 導電層，從而使得廢料區亦具有與成品區相似之生產製 從而了減輕因成品區與廢料區製作工藝不同而引起之 鍾曲；其次，廢料區之導電層厚度隨著與成品區中心之距 離之増大而增加，使得廢料區中越遠離成品區中心之部分 /、有越大之重1，從而該部分之重量可牽制電路板預製品 之兩端以減輕電路板預製品之翹曲度，並使得整個電路板 預製具有較好平整度。本技術方案之電路板組裝方法 15 1358251 •t利用先於成品區組裝電子元器件再去除廢料區之工 使传組裝電子几器件時成品區處於較為平坦之狀態， :保€電子（$件與電路板之對位精度與組裝精度，使 -于電路板具有較好之組裝效果。 -^上所述，本發明確已符合發料利之要件，遂依法 出專利申請。惟，以上料者僅為本發日狀較佳實施方 =自不能以此限制本案之申請專利範圍。舉凡熟悉本案 鲁人士援依本發明之精神所作之等效修飾或變化，皆 應涵盍於以下申請專利範圍内。 【圖式簡單說明】 圖1為本技術方案第一 立體結構示意圖。 實施例提供之電路板預製品之 圖2為沿圖1中之職方向剖開之剖面示意圖。 圖3為本技術方案第—實施例提供之覆銅基板之示意 品區^^:^施例提供之於覆銅基板之成 成光^層本方案第—實施例提供之於覆銅基板上形 光之=圖為本技財提供以光阻層進行曝 影後U意為圖本技術方案第—實施例提供之對光阻層進行顯 圖8為本技術方案第一實施例提供之第-次電鍵後之 16 1358251 . 示意圖。 • 圖9為本技術方案第一實施例提供之移除光阻層後之 -示意圖。 圖10為本技術方案第二實施例提供之電路板預製品之 •示意圖。 圖11為本技術方案第三實施例提供之電路板預製品之 示意圖。 圖12為本技術方案提供之電子元器件之示意圖。 > 圖13為本技術方案提供之將電子元器件組裝於如第一 實施例所示之電路板預製品之示意圖。 圖14為本技術方案提供之去除廢料區後獲得之組装有 電子元器件之電路板成品之示意圖。 【主要元件符號說明】 電路板預製品 10 成品區 101 、 201 、 301 廢料區 102、202、302 導電層 11、21 絕緣層 12、32 導電圖形部 111 > 211 板麵权正部 112 ' 212 ' 312 導電線路 1111 導電接點 1112 第一表面 112a ' 312a 第二表面 112b 、 312b 1358251 . 第一導電材料層 1121 ‘第二導電材料層 1122 -第三導電材料層 1123 \第四導電材料層 1124 •覆銅基板 1〇〇 光阻層 13 光罩 14 開口 140 ®積體電路晶片 40 焊錫凸塊 41 電路板預組裝品 l〇a 電路板成品 l〇b 181358251 IX. Description of the invention: - [Technical field to which the invention pertains] - The present invention relates to a circuit board manufacturing technology, and more particularly to a circuit board preform having better flatness and an electric circuit capable of reducing warpage of the circuit board Board assembly method. [Prior Art] In the information, communications, and consumer electronics industries, boards are an essential component of all electronic products. With the development of electronic products in the direction of small-scale and high-speed, circuit boards have also evolved from single-sided boards to double-sided boards and multilayer boards. Multilayer boards are widely used due to their large wiring area and high assembly density. See Takahashi, A. et al., 1992, IEEE Trans, on Components, Packaging, and Manufacturing Technology, "High Density Layered Print." Circuit board for HITAC M~880”. The fabrication and assembly process of the I board usually includes the steps of blanking, forming conductive patterns and vias, gold plating, molding, and assembly. The blanking refers to cutting a raw material such as a copper clad laminate into a substrate of an appropriate size for facilitating production, the substrate including a finished product area corresponding to the circuit board product and a waste area for supporting the finished product area to facilitate placement of the substrate. Secondly, the copper layer of the waste area is removed and conductive patterns and via holes are formed in the finished area, that is, the copper layer of the finished area is formed into a pattern including conductive lines and connection terminals, and interconnection of interlayer conductive lines is realized. Again, the boarding process is performed after the forming process is performed by die cutting or stamping to remove the waste area. Finally, the electronic U58251 device is assembled on the circuit board product to realize the signal connection between the electronic component and the circuit board product, and the finished circuit board with the electronic component is obtained. However, the above process has the following disadvantages: First, since there is no copper layer in the waste area of the substrate, and the finished area has a copper layer, which causes the manufacturing process of the finished area and the waste area to be different, which is easy to cause: the finished product area and Inconsistent expansion and contraction of the scrap area causes warpage of the entire circuit board substrate, and generally, the clock on both ends of the circuit board substrate is more serious, and the central portion is relatively flat. Second, if the circuit board is warped, it is assembled. , the call can cause the board and the electronic components can not be accurately connected to the bit and the connection, resulting in assembly failure. In view of the above, it is necessary to provide a circuit board preform having a good flatness and a circuit board assembly method which can reduce the warpage of the circuit board and improve the assembly effect of the circuit board. SUMMARY OF THE INVENTION A circuit board preform and a circuit board assembly method will be described below by way of embodiments. A circuit board preform comprising a finished product area and a waste area located around the finished product area, the finished product area and the waste area each having a conductive layer, the conductive layer is formed with a conductive pattern, and the conductive layer thickness of the waste area As the distance from the center of the finished area increases, it increases. A circuit board assembly method comprising the steps of: providing a circuit board preform as described above; assembling an electronic component in a finished product area; and removing the waste area to obtain a finished circuit board assembly with the electronic component. In the pre-product of the circuit board of the technical solution, first, the scrap area also has a conductive layer', so that the scrap area also has a production process 13508251 similar to the finished area, thereby reducing the manufacturing process caused by the difference between the finished area and the waste area. The composition, secondly, the thickness of the conductive layer of the scrap area increases with the distance from the center of the finished product area, so that the farther away from the center of the finished product area, the greater the weight, so that the weight of the part can be Both ends of the board pre-product are pinned to reduce the warpage of the board pre-form and to make the entire board pre-form have a good flatness. In the circuit board assembly method of the technical solution, the process of assembling the electronic components prior to the finished product area and then removing the waste area is used, so that the finished product area is in a relatively flat state when assembling the electronic components, thereby ensuring the electronic components and the circuit board. The alignment accuracy and assembly accuracy make the board have a better assembly effect. [Embodiment] Hereinafter, a circuit board pre-product and a circuit board assembly method provided by the present technical solution will be further described in detail with reference to the accompanying drawings and the embodiments. Referring to FIG. 1 and FIG. 2 together, the circuit board preform 10 provided by the first embodiment of the present technical solution includes a finished product area 101 and a waste area 102. φ This board pre-product 10 is a circuit board that has been subjected to a conductive line process and has not yet been subjected to a molding process. The circuit board preform 10 can be a single-sided circuit board, a double-sided circuit board, or a multi-layer circuit board. In this embodiment, the circuit board preform 10 is a rectangular single-sided circuit board including a conductive layer 11 and an insulating layer 12. The conductive layer 11 can be a copper layer, a silver layer or a gold layer, and in this embodiment is a copper layer. The insulating layer 12 may be a hard resin layer such as an epoxy resin, a fiberglass cloth, or the like, or may be a flexible resin layer such as polyimide (PI) or polyethylene to ethylene glycol phthalate. (Polyethylene Terephtalate, PET), Teflon, Polyamide, Polymethylmethacrylate 1, Polymethylmethacrylate, Polycarbonate or Polyfluorene, Imine-Polymer Polyamide 'polyethylene-terephthalate copolymer, and the like. The finished product area 101 refers to the area of the circuit board preform 10 corresponding to the final formed electrical: the finished form of the road board. In this embodiment, the finished product area is rectangular and is located at a central portion of the circuit board preform 10. The waste area 102 refers to the area of the circuit board preform 10 located around the finished product area 101, which will be removed after the completion of the manufacturing process, and is used to provide support for the finished product area 101 during the manufacturing process and to facilitate the placement of the entire circuit. The role of the board preform 10 . The conductive layer 11 is included in the conductive pattern portion U1 of the finished region 101 and the plate warpage correcting portion 112 of the waste region 102. The conductive pattern portion lu is located on the same plane as the plate warpage correcting portion 112, and is attached to the surface of the insulating layer 12. The conductive pattern portion 111 refers to a conductive pattern formed by the conductive layer U and including the conductive line n and the connection terminal 1112 for signal transmission and connection with the electrical component. The thickness of the plate warpage correcting portion 112 increases as the distance from the center of the finished product area increases. The finished area 1〇1 center refers to the geometric center of the finished area 101. Generally speaking, the greater the warpage of the portion of the circuit board preform 1 that is farther from the center of the finished product area 101, the greater the thickness of the board warpage correction portion is such that the portion of the waste area 1〇2 farther from the finished area 1〇1 has The greater the weight, therefore, the variation of the weight of the scrap zone 102 corresponds to the variation of the warpage of the circuit board preform 10. The weight of the portion 112 can be used to pinch the warpage of the portion of the circuit board preform 10 that is far away from the finished product = the center of the core. Therefore, the board warpage correcting portion 112 can reduce the warpage of the printed circuit board 1358251 preforms, and correct the circuit board The warpage of the article 10, • allows the entire board preform 10 to have a good flatness. The plate warpage correction portion 112 can continuously or linearly increase the thickness as the distance from the center of the finished product region 101 by means of grinding, polishing, electropolishing, etc., or by image transfer. The process and the plating or etching process cause the thickness to increase intermittently stepwise as the distance from the center of the finished region 101 increases. In this embodiment, the thickness of the plate warpage correcting portion 112 is increased stepwise, and has a first surface 112a and a plurality of second surfaces 112b parallel to the first rub surface 112a. The first surface 112a is in contact with the insulating layer 12, The distance between the plurality of second surfaces 112b and the first surface 112a increases sequentially. The number of the second surfaces 112b is not limited, and is four in this embodiment. Specifically, the plate warpage correcting portion 112 sequentially includes a first conductive material layer 1121, a second conductive material layer 1122, a third conductive material layer 1123, and a fourth conductive material layer 1124. The four second surfaces 112b are sequentially located on the first conductive material layer 1121, the second conductive material layer 1122, the third conductive material layer 1123, and the fourth conductive material layer 1124. That is, the first conductive material layer 1121 is attached to the insulating layer 12 and spreads over the entire waste region 102. The second conductive material layer 1122 is attached to the first conductive material layer 1121 and has a distribution area between the first conductive material layer 21 and the third conductive material layer 1123, and is only distributed in the waste area 102 away from the finished area 101. region. The third conductive material layer 1123 is located between the second conductive material layer 1122 and the fourth conductive material layer 1124, and the distribution area thereof is also between the second conductive material layer 1122 and the fourth conductive material layer 1124, and is distributed in the waste material. The area of zone 102 is further away from the area of the finished 1358251 zone 101. The fourth conductive material layer 1124 has the smallest distribution area - and is distributed in the area of the waste area 102 that is farthest from the finished area 101. - the increase of the distance between the plurality of second surface 112b and the first surface 112a is not limited, that is, the first conductive material layer 1121, the second conductive material layer: 1122, the third conductive material layer 1123, and the fourth conductive material The thickness of layer 1124 is not limited. In this embodiment, the distance between the plurality of second surfaces 112b and the first surface 112a is increased, and the thickness of the first conductive material layer 1121 is the same as the thickness of the conductive pattern portion 111, that is, the minimum thickness of the plate warpage correcting portion 112. The @ degree is the same as the thickness of the conductive pattern portion 111, and the thicknesses of the first conductive material layer 1121, the second conductive material layer 1122, the third conductive material layer 1123, and the fourth conductive material layer 1124 are also the same. Of course, the thickness of the first conductive material layer 1121 may be different from the thickness of the conductive pattern portion 111 and the thickness of the second conductive material layer 1122. The second conductive material layer 1122, the third conductive material layer 1123, and the fourth conductive material layer may also be different. The thickness of 1124 can also vary. For example, the thickness of the third conductive material layer 1123 may be between the second conductive material layer 1122 and the fourth conductive material layer 1124, that is, the second conductive material layer 1122, the third conductive material layer 1123, and the fourth conductive material layer. The thickness of 1124 can be gradually increased to provide greater weight in the portion of the waste zone 102 that is further from the finished zone 101 to better pinch the warpage of the portion of the circuit board preform 10 that is distal from the center of the finished zone 101. . The circuit board preform 10 shown in the first embodiment of the present technical solution can be manufactured by the following steps: First, referring to Fig. 3, a copper clad substrate 100 having a finished product 11 1358251 region 101 and a waste positive 102 is provided. The copper clad substrate 1 is a single-sided copper clad substrate comprising a first conductive material layer 1121 and an insulating layer 12. . . Referring to FIG. 4, the first conductive material layer 1121 of the .σσ region ι〇1 is formed into a conductive pattern portion m by an image transfer process and an etching process. • Again, the tortoise correction unit 112 is formed in the scrap area 102 by the image transfer process and the electroplating process. - In the first step, please refer to FIG. 4 and FIG. 5 together on the copper-clad substrate; the surface of the L00 is formed by coating or coating the photoresist layer 13 to make the conductive pattern of the finished region ι〇ι. The first conductive material layer of the crucible 111 and the waste region 1〇2 is covered by the photoresist layer 13. In this embodiment, the photoresist layer 13 is a positive photoresist. Of course, it can also be a negative photoresist. In the second step, please refer to FIG. 1 and FIG. 1 to expose the photoresist layer 13 by the photomask 14. The portion of the reticle 14 corresponding to the scrap area 1 〇 2 has an opening 14 相对 corresponding to the second conductive material layer 1122. After the exposure, the light-resisting layer 13 corresponding to the opening 140 is decomposed and reacted. The photoresist layer 13 which is not irradiated with light does not react. In the third step, the circuit board substrate 1 is immersed in the developing solution, and the photoresist layer 13 in which the decomposition reaction occurs is dissolved to expose the underlying copper foil layer 1121, and the photoresist layer 13 which does not react is not formed. Without being dissolved, it remains attached to the surfaces of the conductive pattern portion 111 and the copper foil layer 1121 as shown in FIG. In the fourth step, the circuit board substrate 10 is immersed in a plating bath (not shown) such that the conductive material in the plating bath is deposited on the surface of the copper pig layer 1111 not covered by the photoresist layer 13, that is, in the waste area 102. A region corresponding to the opening ι4 镀 is plated with a second conductive material layer 1122 as shown in FIG. 12 1358251. In the fifth step, referring to FIG. 8 and FIG. 9, the photoresist layer 13 remaining on the first conductive material layer 1121 and the surface of the conductive pattern portion 111 is removed, thereby obtaining the first conductive material. The layer 1121 and the second conductive material layer 1122 are circuit board semi-finished products. In the sixth step, the above steps are repeated to form a third conductive material layer 1123 on the second conductive material layer 1122, and a fourth conductive material layer 1124 is deposited on the third conductive material layer 1123. Thereby, the plate warpage correcting portion 112 including the first conductive material layer 1121, the second conductive material layer 1122, the third conductive material layer 1123, and the fourth conductive material layer 1124 can be formed in the scrap region 102, and formed in the finished product region. 101 has a conductive pattern portion 111, and has a conductive layer 11 of the plate warpage correcting portion 112 in the waste region 102, thereby obtaining a circuit board preform 10 including the above-described conductive layer 11, as shown in FIG. Referring to FIG. 10, the circuit board preform 20 provided by the second embodiment of the present invention is substantially the same as the circuit board preform 10 provided by the first embodiment, except that the maximum thickness and conductivity of the board warpage correcting portion 212 are different. The thickness of the pattern portion 211 is the same, that is, the maximum thickness of the conductive layer 21 of the waste region 202 is the same as the thickness of the conductive pattern. In this embodiment, the stepwise change of the thickness of the conductive layer 21 of the scrap region 202 can be performed after the conductive layer 21 of the finished region 201 is formed into a conductive pattern by performing multiple image transfer processes on the conductive layer 21 of the scrap region 202. The secondary etching process is realized. Referring to FIG. 11, the circuit board preform 30 provided by the third embodiment of the present invention is substantially the same as the circuit board preform 20 provided by the second embodiment, except that the thickness of the board warpage correcting portion 312 is The distance from the center of the finished product zone 301 increases continuously and linearly. The plate warpage correcting portion 312 has 13 1358251 opposed to the first surface 312a and the second surface 312b. The first surface 312 & is a plane 'which is in contact with the insulating layer 32. The second surface 312b is also planar and intersects the first surface 312a. In this embodiment, the continuous change in the thickness of the plate warpage correcting portion 312 can be achieved by performing multiple abrasion or polishing of the conductive layer of the waste region 3〇2. Of course, the second surface 312b may also be a curved surface, that is, the thickness of the plate warpage correction portion 12 may continuously increase in a nonlinear relationship as the distance from the center of the finished product region 301 increases, and only the plate warpage correction portion 312 is required. The thickness variation rule corresponds to the variation law of the surface curvature of the circuit board pre-product 3G, so that the warpage of the two ends of the circuit board preform can be well pinned. The present technical solution also provides a circuit board assembly method. Hereinafter, only the circuit board preform 10 of the first embodiment will be described as an example. First, referring again to Figure i, a pre-form 10 of the first embodiment is provided. Μ Next, please refer to FIG. 12 and FIG. 13 together with the sub-component 40 in the finished product area 101. Of course, before the assembly of electronic components, the process of pre-fabrication of the board can be carried out in the form of gold, coated solder mask, and text printing. Manufactured in the pre-product of the circuit board, σ Λ 1Λ1~Zhuang + 7 will be Leizi 亓 crying heart 0 strong agricultural electronic components refer to α, installed in the finished area 101 and the position of the conductive pattern part 1η f. The method of assembling the electronic components in the finished product area 1 is a surface mount, a flip-chip structure, and other methods, and the type of assembly depends on the type of the electronic device. The electronic component is a device for real function, and can be used as an integrated circuit chip, or a capacitive inductor component, 1358251, can be used as a device. The shape and structure of the electronic component are not limited. In the embodiment, the electron element is a rectangular parallelepiped piece 40 having a plurality of solder bumps 41 corresponding to the conductive contacts (10), and the bonding heads are provided by the bonding heads (the figure is not -= the plural of the integrated circuit wafers 40) Solder bumps 41 are paired with a pair of contacts, and then soldered to achieve a solid connection between the solder bumps and the (four) mouth Flm, thereby laminating the integrated circuit wafers to form an electronic component. The circuit board pre-assembly of the device -, again 'please-and refer to _ 13 and Figure 14, remove the waste area to move, and then assemble the finished circuit board 10b with the electronic component 40. To punch the die, sharp knife, thunder The shot or other tool cuts the finished area and the boundary of the two scrap areas 102, so that the waste area 1〇2 is dropped and removed, and the finished board (10) of the fine-grained integrated circuit chip 4 is obtained. Of course, the board is obtained. After the finished product l〇b, it can also carry out subsequent inspection, further assembly and other processes. ^, In the circuit board preform of the technical solution, first, the scrap area also has a conductive layer, so that the scrap area also has a production system similar to the finished area, thereby reducing the clock caused by the different manufacturing process of the finished area and the waste area. Secondly, the thickness of the conductive layer in the scrap area increases with the distance from the center of the finished product area, so that the farther away from the center of the finished product area, the greater the weight of the waste area, so that the weight of the part can be trapped Both ends of the board preform are used to reduce the warpage of the circuit board preform, and the whole circuit board prefabrication has a good flatness. The circuit board assembly method of the technical solution 15 1358251 • Use the electronic component before the finished product area After removing the waste area, the finished product area is in a relatively flat state when the electronic components are assembled. The protection of the electronics and the precision of the assembly and the accuracy of the assembly make the board have a good assembly effect. -^ As stated above, the present invention has indeed met the requirements for the issue of the materials, and the patent application is issued according to law. However, the above materials are only preferred for the present day. This article can limit the scope of the patent application in this case. Any equivalent modifications or changes made by the person in charge of the case in accordance with the spirit of the present invention should be included in the scope of the following patent application. FIG. 2 is a cross-sectional view taken along the direction of FIG. 1. FIG. 3 is a schematic view of a copper-clad substrate provided by the first embodiment of the present technical solution. The product area ^^:^The example provided on the copper-clad substrate is formed into a photo-layer. The first embodiment provides a photo-deposit on the copper-clad substrate. The post U is intended to show the photoresist layer provided by the first embodiment of the present invention. FIG. 8 is a schematic diagram of the first-order key provided by the first embodiment of the present technical solution. Figure 9 is a schematic view of the first embodiment of the present invention after removing the photoresist layer. Figure 10 is a schematic view of a circuit board preform according to a second embodiment of the present technical solution. Figure 11 is a schematic view of a circuit board preform according to a third embodiment of the present technology. FIG. 12 is a schematic diagram of an electronic component provided by the technical solution. > Fig. 13 is a schematic view showing the assembly of an electronic component in a circuit board preform as shown in the first embodiment, provided by the present technical solution. Fig. 14 is a schematic view showing the finished circuit board assembly with electronic components obtained after removing the waste area provided by the technical solution. [Description of main component symbols] Circuit board preform 10 Finished area 101, 201, 301 Waste area 102, 202, 302 Conductive layer 11, 21 Insulation layer 12, 32 Conductive pattern portion 111 > 211 Board surface right portion 112 ' 212 ' 312 conductive line 1111 conductive contact 1112 first surface 112a ' 312a second surface 112b, 312b 1358251 . First conductive material layer 1121 'second conductive material layer 1122 - third conductive material layer 1123 \ fourth conductive material layer 1124 • Copper-clad substrate 1 〇〇 photoresist layer 13 Photomask 14 Opening 140 ® Integrated circuit wafer 40 Solder bump 41 Circuit board pre-assembly l〇a Circuit board finished product l〇b 18