WO2009116564A1 - 抵抗変化素子、半導体記憶装置、その製造方法及び駆動方法 - Google Patents
抵抗変化素子、半導体記憶装置、その製造方法及び駆動方法 Download PDFInfo
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- H—ELECTRICITY
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of switching materials after formation, e.g. doping
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/253—Multistable switching devices, e.g. memristors having three or more electrodes, e.g. transistor-like devices
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to a resistance change element, a semiconductor memory device, a manufacturing method thereof, and a driving method.
- non-volatile memories that are mainstream in the market include flash memories and memories with a SONOS (Silicon Oxide Nitride Oxide Silicon) stack structure. These memories are realized by using a technique for changing the threshold voltage of the semiconductor transistor by the electric charge stored in the insulating film disposed above the channel portion of the semiconductor transistor.
- SONOS Silicon Oxide Nitride Oxide Silicon
- phase change memory There are several existing technologies for changing electrical resistance by electrical stimulation.
- the most well-studied technology used the fact that a pulse current is passed through a chalcogenide semiconductor to switch the crystal phase (amorphized crystal), and there is a difference of 2 to 3 digits in the electrical resistance of each crystal phase. It is a storage device and is generally called a phase change memory.
- MIM type metal / metal oxide / metal (hereinafter referred to as MIM type) structure in which a metal oxide is sandwiched between electrodes is known to cause a resistance change by applying a large voltage or current.
- the present invention mainly relates to this MIM variable resistance element.
- FIG. 1 is a schematic diagram of a MIM variable resistance element.
- Reference numeral 1 shown in FIG. 1 denotes an upper first electrode in the MIM variable resistance element.
- 2 shows a resistance variable material made of a metal oxide.
- Reference numeral 3 denotes a lower second electrode in the MIM variable resistance element.
- Non-Patent Document 1 reports on a resistance change element using nickel oxide (Ni O). In the 1950s and 1960s, the phenomenon that the resistance value changes with voltage and current is various. Research has been reported.
- FIG. 2 shows the current-voltage characteristics of the MIM variable resistance element shown in FIG.
- the variable resistance element maintains the high-resistance off-state or low-resistance on-state characteristics in a nonvolatile manner even when the power is turned off, but the resistance state is applied by applying a predetermined voltage / current stimulus as necessary. Can be switched.
- FIG. 2 shows an example of current-voltage characteristics in the on state and the off state.
- the MIM resistance change element can be repeatedly switched between FIG. 2A and FIG. 2B, and this characteristic is used as a nonvolatile memory cell for circuit switching or a nonvolatile switch. be able to.
- the reference value for determining whether the resistance is high resistance or low resistance is not particularly limited, and any reference value can be used as long as it can be switched between high resistance and low resistance. It is possible to apply.
- As the reference value for example, 10 k ⁇ is preferable.
- the current path that assumes the low resistance state is not formed in the entire electrode surface, as shown schematically in FIG. Even the local current path 4 having a diameter of about several tens of nm is obtained.
- FIG. 4 shows the electrode area dependence characteristics of the resistance value in the low resistance state in the parallel plate type MIM resistance change element. 4 shows the case where Ni O is used as the variable resistance material of the current path 4 as in Non-Patent Document 1.
- the resistance value in the low resistance state hardly depends on the electrode area, and it can be seen that the low resistance state is carried by the locally formed current path 4. Therefore, when the MIM resistance change element is applied as a memory element, the electrical resistance in the high resistance state is higher with miniaturization, the electrical resistance in the low resistance state is hardly changed, and the resistance ratio in each state is higher. can do. For this reason, the MIM resistance change element can be said to be a memory element suitable for miniaturization.
- the two-terminal MIM resistance change element requires more current when switching to the high resistance state as the electrical resistance in the low resistance state decreases. There is. For this reason, in the case of realizing a fuse / antifuse type switching element capable of switching the resistance state a plurality of times, the above-mentioned problem becomes a big problem.
- a two-terminal MIM resistance change element requires a large-capacity power supply circuit (driver), which is associated with an increase in chip area from the viewpoint of power consumption. It is also a big problem in terms of increase in manufacturing cost.
- a variable resistance element having three or more terminals can be said to be a semiconductor transistor.
- a MOS transistor having a metal / oxide / semiconductor (MOS) type gate terminal is induced at the depletion layer width at the semiconductor interface under the gate by applying a voltage to the gate terminal, that is, at the insulator / semiconductor interface. It is possible to control the carrier density and adjust the conductance between the source and the drain.
- the amount of carriers induced at this time is about 10 ⁇ 18 (cm ⁇ -3) to 10 ⁇ 20 (cm ⁇ -3) in terms of volume density.
- Patent Documents 1 and 2 disclose a three-terminal element in which a metal oxide is replaced with a semiconductor material.
- Patent Documents 1 and 2 propose an element having a structure in which a semiconductor portion of a MOS semiconductor transistor is replaced with a metal oxide. Both have the same multi-terminal arrangement as the source / drain / gate semiconductor transistors.
- the resistance change element is similar to the semiconductor transistor in that charge is induced at the metal oxide / insulator interface by an electric field generated at the gate terminal. However, the resistance change element is greatly different from the semiconductor transistor in that the principle of operation is to cause the metal-insulator transition of the oxide material by the induced charge and change the conductance of the entire surface under the gate electrode. In order to cause the metal-insulator transition, the resistance change element needs to change the amount of charge more than 10 ⁇ 21-10 ⁇ 22 (cm ⁇ -3) in volume density and drives the MOS type semiconductor transistor. It will reach 100 times the charge density required.
- the resistance change element needs to generate an extremely high electric field directly under the gate, and of course, the interface state density is low, and the insulator under the gate terminal has a very high breakdown voltage. It is necessary to use materials, which is a big barrier to realization.
- a filament-shaped current path 4 having an extremely small cross-sectional area is formed between electrodes corresponding to the source and drain, and these have non-volatility that is maintained even when the power is turned off. This is very different from the first and second inventions.
- the current path 4 is caused by a structural change of a fine region accompanying a slight movement of metal or oxygen in the crystal, and is not a metal-insulator transition by so-called charge amount control in the material.
- Patent Document 3 in a nonvolatile memory device including a substrate, a switching element formed on the substrate, and a storage node coupled to the switching element, the storage node is coupled to the switching element and serves as an ion source.
- JP 2006-319342 A JP-A-9-129839 JP 2007-59914 A JFGIBBONS and WEBEADLE 'SWITCHING PROPERTIES OF THIN NiOFILMS' Solid-State Electronics, Vol.7, P.785-797, 1964.
- Patent Document 3 discloses a nonvolatile semiconductor memory device including an ion conductive layer.
- Patent Document 3 in the above-mentioned Patent Document 3, in the variable resistance element having three or more electrodes, any description and necessity of the variable resistance element in which no ion is supplied to the variable resistance material from any electrode is suggested. Not.
- the present invention has been made in view of the above circumstances, and is a variable resistance element capable of reducing current required when switching from a low resistance state to a high resistance state, a semiconductor memory device,
- An object is to provide a manufacturing method and a driving method thereof.
- the present invention has the following features.
- the variable resistance element according to the present invention is A resistance change element having three or more electrodes, and from which no ion is supplied to the resistance change material; A material that does not exhibit a resistance change is disposed between one electrode and the variable resistance material, and a current path is formed in two electrodes other than the one electrode.
- the semiconductor memory device according to the present invention is It is characterized by including the variable resistance element described above.
- the manufacturing method according to the present invention includes: A method of manufacturing a resistance change element having three or more electrodes, in which ions are not supplied from any electrode to the resistance change material, A material that does not exhibit a resistance change is disposed between one electrode and the variable resistance material, and a current path is formed in two electrodes other than the single electrode.
- the driving method according to the present invention includes: A resistance change in which three or more electrodes are provided, and no ion is supplied to the resistance change material from any electrode, and a material that does not exhibit a resistance change is disposed between one electrode and the resistance change material.
- a device driving method A current path is formed in two electrodes other than the one electrode.
- the resistance change element according to the present embodiment has three or more electrodes (204, 207, 202), and is a resistance change element in which no ion is supplied to the resistance change material (205) from any electrode. is there.
- a material (206) that does not exhibit a resistance change is disposed between one electrode (207) and a resistance change material (205), and two electrodes (204) other than the one electrode (207) are disposed.
- the current path (4) shown in FIG. 3 is formed. Thereby, it becomes possible to reduce the current required when switching from the low resistance state to the high resistance state.
- the variable resistance element according to the present embodiment will be described in detail with reference to the accompanying drawings.
- Ni O In the conduction mechanism between the high resistance state and the low resistance state, it is important that the metal oxide layer contains metal or oxygen vacancies in a density of percent order.
- Ni O will be described as an example.
- Ni O ideally forms crystals with a rock salt structure with a ratio of Ni to O of 1: 1, but in reality, Ni defects tend to occur.
- FIG. 6 schematically shows a state in which the periphery of the Ni deficiency generated in the Ni O crystal is divided by the (001) plane.
- ⁇ Ni deficiency effectively functions like a divalent negative charge (acceptor).
- acceptor divalent negative charge
- surplus charges are induced in the metal ions as shown in FIG. 6 in order to compensate for the charge imbalance caused by the introduction of defects.
- FIG. 7 shows the conceptual band structure.
- the band gap is determined by the energy required to transfer charges to the transition metal d-orbit above the oxygen 2p orbital, and the electron orbit near the top of the valence band is hybridized with the transition metal ion d-orbital. However, it is thought that the characteristics of oxygen 2p orbit are strong.
- the holes generated for the charge compensation of the metal deficiency mainly enter the 2p orbit of oxygen existing in 6-coordinates around the metal deficiency as shown in FIG. It is known that the induced holes are likely to be localized around the metal defect with lattice distortion, and this state is shown as “metal defect wearing a hole garment” as shown in FIG. Can be drawn schematically.
- Ni O which has upper and lower electrodes formed of platinum group metal electrodes, is considered to be a state in which “Ni deficient in a hole garment” is randomly dispersed at a density of percent order in Ni ⁇ ⁇ O. It is done.
- reference numerals 301 and 303 denote electrodes.
- 302 represents a transition metal oxide.
- 304 indicates electrons.
- the electric conduction near room temperature is limited to “1”: a mechanism over the potential barrier at the electrode interface as shown in FIG. 11, and “2”: a mechanism for hopping holes between Ni vacancies. Is done.
- FIG. 11 This is a state in which the mechanism “3” shown in FIGS. 11 and 12 is emphasized, and when shown in a band diagram, Ni deficiencies are arranged in a state corresponding to a one-dimensional chain as shown in FIG. It can be explained if you think.
- the formation of a one-dimensional chain by this Ni deficiency is the key to resistance change phenomenon control, and this formation mechanism will be described later.
- the resistance change element is an electrode that is a two-terminal MIM resistance change element and includes an ion source.
- description about a resistance change element is demonstrated for the comparison of this embodiment to the last.
- Numeral 101 shown in FIG. 15 is an electrode.
- the electrode 101 is made of an element that allows ions such as Cu and Ag to move in the solid electrolyte 102.
- the counter electrode 103 often uses an element that is difficult to ionize, such as Pt.
- the electrons 104 on the electrode 101 side move to the electric wire side, and the metal element of the electrode 101 is ionized at the interface between the electrode 101 and the solid electrolyte 102 to generate a positive charge.
- the charged ions 105 begin to move toward the counter electrode 103, which is the negative electrode.
- the ions 105 give and receive the electrons 104, and the electrons 104 are reduced to the ions 105.
- a metal element 106 it is precipitated. An electric field is easily concentrated between the metal element 106 and the electrode 101 from the surroundings, and the electrons 104 can freely move in the deposited metal. Therefore, as shown in FIG.
- the bridge of the metal element 106 grows so that the tip of the metal element 106 grows, and when the bridge tip of the metal element 106 reaches the electrode 101, the resistance change element Transitions to a low resistance state.
- Oxidation / reduction of the metal element 106 is an indispensable process in the process of movement of the ions 105 and metal deposition.
- the battery In order to return this state to the high resistance state again, the battery is connected in reverse and the direction of the electric field in the solid electrolyte 102 is reversed.
- This “forming” forms the one-dimensional array structure of Ni deficiency shown in FIG. 14, but the microscopic behavior of the ions 105 contained in advance in the resistance change material is important. Again, it should be noted that no ions 105 are supplied from the electrode into the variable resistance material.
- FIG. 19 shows a location where Ni deficiency exists adjacent to the position in FIG. 10 (position surrounded by a dotted line). Holes localized around isolated Ni vacancies cannot move unless they are thermally activated. However, when Ni vacancies are adjacent to each other to form a complex of vacancies, the holes move only within the interior. It is thought that it is easy to do. If Ni deficiency is connected from one electrode 301 as shown in FIG. 10, when an electric field is applied in this state, holes can easily move to the tip of the nucleus in contact with the electrode 301, and the electric field is connected to the counter electrode 303. It is applied concentrated on the tip of the nucleus. Such a location functions as a generation nucleus of the current path 4.
- Ni deficiency across the tip of the nucleus and one or several Ni ions.
- holes as charge carriers start to move from the adjacent Ni defect to the counter electrode 303 by the hopping mechanism.
- reduction electron reduction
- the hole movement is a hopping mechanism, and the electric field dependence of this conduction mechanism is proportional to the square root of the electric field strength, so the rate of increase in the hopping probability (mobility) gradually decreases.
- Ni ions are more likely to move to adjacent Ni defects rather than hole movement (hopping).
- FIG. 21 schematically shows the time change of the electric field in the region indicated by “P” in FIG.
- “1” indicates a case where a hole is supplied (low electric field) to an adjacent defect from a filament conduction path in which holes have grown.
- “2” indicates the case where Ni ions in the gap between the filament and the adjacent defect move to the adjacent defect (threshold electric field Ef or more).
- “A” and “A ′” indicate the moments when holes escaped (reduced) from adjacent defects (the periphery of the defect is effectively strongly negatively charged).
- “B” indicates the moment when the hole hops from the filament to the adjacent defect.
- “C” indicates the moment when Ni ions in the gap move to adjacent defects.
- This process is a process in which holes are first deprived (electrons are supplied) due to the original Ni deficiency, and subsequently, Ni ions move.
- the counter electrode of the resistance change element having an ion source on the electrode described above This corresponds to the metal ion reduction process.
- the resistance change element used in the present embodiment occurs at a lattice defect position in the metal oxide, so that the moving distance of real ions can be reduced. This is the reason why the resistance change speed of this resistance change element is several orders of magnitude higher.
- Ni O has a rock-salt type crystal structure, which is a nested structure in which the face-centered cubic structures of O and Ni are shifted by (1/2, 0,0). This is because the ion filling rate is high. In fact, it is believed that no interstitial defects occur in Ni O, and the only preferential and dominant destination of Ni ions at the lattice position is the Ni defect position.
- Ni deficiency newly generated (connected) at the tip of the nucleus when attention is paid to Ni deficiency.
- the electric field between the filament tip and the counter electrode becomes stronger than before the Ni ion movement, and the filament tip grows at an accelerated speed.
- the presence of Ni deficiency in the vicinity of the tip at this time is a necessary condition for growth, and in the case of a filament that is not satisfied, the growth stops halfway, but the filament that satisfies the necessary condition grows selectively.
- the counter electrode is connected to the counter electrode. In such a process, when the path where the defect is connected between the electrodes is bridged, the state transitions to a low resistance state.
- the mobility of oxygen vacancies is high, and the movement of metal defects is often not a problem.
- the bond mode between oxygen and metal is not a pure ionic bond but has a covalent element, and the reaction product energy with oxygen per single atom Is about 10 times that of S and Se compounds used in phase change memory. Therefore, if there is an adjacent defect with a high electric field applied as shown in FIG. 21, ion migration occurs sufficiently.
- the hole mobility is high, and the temperature dependence of the resistance also shows a semiconductor close to a metal, but still has a finite electrical resistance.
- the filament generates Joule heat in an amount proportional to the square of the current value and its own resistance value as shown in FIG.
- the low resistance state is stable when Ni vacancies are one-dimensionally arranged structurally, but the lattice vibration increases as the temperature rises, and the thermally adjacent Ni ions move to the Ni vacancies on the filament ( The probability of diffusion) increases.
- FIG. 22 if even a part of the Ni deficiency on the path is filled with Ni ions, hole movement on the path is limited by hopping movement at the cut position, and the resistance value becomes high. This is just a break of the path, and it has been found that the position where this path breakage is likely to occur is often near the electrode interface.
- the above mechanism may be regarded as the behavior of oxygen deficiency in an oxide that easily generates oxygen deficiency, such as Ti-Ox or W-Ox, and exhibits n-type conduction.
- an oxide that easily generates oxygen deficiency such as Ti-Ox or W-Ox
- n-type conduction in other words, in forming, a one-dimensional array of oxygen vacancies is formed, and it is thought that conduction is carried out by electrons induced in the d orbitals of surrounding Ti and W.
- a low resistance filament is formed between two electrodes by the mechanism as described above.
- an electric field can be applied in a direction not parallel to the growth direction of the filament.
- These electrodes are installed through an insulator between the variable resistance material.
- the variable resistance element according to this embodiment includes an insulator 203 on the fourth electrode 202 and a variable resistance material 205 on the insulator 203.
- the variable resistance material 205 includes first and second electrodes 204 and an insulator 206, and the insulator 206 includes a third electrode 207. Yes.
- the insulator 203, the resistance change material 205, and the first and second electrodes 204 are configured to have an interlayer insulating film 201 at both ends.
- the variable resistance element of this embodiment can reduce the current required when switching from the low resistance state to the high resistance state by configuring the structure shown in FIG.
- FIGS. 24 to 27 are diagrams for explaining the manufacturing process of the first structure of the variable resistance element according to this embodiment, and a completed schematic diagram is shown in FIG.
- FIG. 24 is a cross-sectional view in the case where the fourth electrode 202 is formed as flat as possible in the interlayer insulating film 201 on a wafer made of an Si substrate including a logic circuit, a power supply circuit, and the like.
- an insulator 203 such as Mg O (the same Na Cl type structure as Ni O and close to the lattice constant) and Al2 O3 is deposited as shown in FIG. After the first and second electrodes 204 to be formed are deposited, the upper portion of the fourth electrode 202 is opened by a method such as dry etching.
- a variable resistance material (NiO) 205 is deposited to several to 20 nm so as to fill the opening. Further thereon, a gate insulator 206 such as Mg O is deposited, and then a third electrode (platinum group such as Ru, Ta ⁇ N, Ti N, W) 207 is deposited, and as shown in FIG. Is processed using a method such as dry etching. In addition to the pure metal oxide such as Ni-O, Al, Ti, and Ta can be added to the resistance change material 205 in the range of 1 to 10%.
- contact holes are opened by dry etching, and the portion that becomes S / D is excessively oxidized by plasma oxidation or the like, or Li ion
- the resistance of the S / D part is reduced by injecting, and the contact is filled with a metal such as W or Ti N.
- FIG. 28 is a view for explaining the manufacturing process of the first structure of the variable resistance element according to this embodiment, and shows a completed schematic diagram.
- the second structure shows a case where a resistance change material 205 is embedded between two electrodes 204 as shown in FIG.
- an insulator 203 such as Mg O (the same Na Cl type structure as that of Ni) O and a lattice constant is close) or Al2 O3 is deposited on the structure shown in FIG.
- the upper portion of the fourth electrode 202 is opened by a method such as dry etching.
- a variable resistance material (NiO) 205 is deposited to several to 20 nm so as to fill the opening.
- an insulator 206 such as Mg O (the same Na Cl type structure as Ni O and close to the lattice constant) or Al2 O3 is deposited thereon.
- a third electrode (platinum group such as Ru, Ta N, Ti N, W) 207 is deposited, and the third electrode 207 is processed using a method such as dry etching as shown in FIG.
- a low resistance filament is formed between two electrodes arranged on a plane parallel to the substrate by forming in the same manner as the two-terminal element.
- V 1 is applied, and the filament is heated by passing an electric current through the filament.
- the current i flowing at this time can be made smaller than the current I necessary for filament cutting in the two-terminal element (i ⁇ I).
- V 2 is applied between the third or third and fourth electrodes after a certain time, most preferably 10 to 100 nsec, to generate an electric field at an angle not parallel to the filament.
- the lattice defects forming the filament move and the filament is cut.
- variable resistance element of the present embodiment is an additional electrode that is in contact with the variable resistance material via a highly insulating material, in addition to the two electrodes that are in direct contact with the variable resistance material.
- the device structure has the following. This realizes a mechanism that can apply an electric field at an angle that is not parallel to the current path using the third or fourth electrode without flowing a large current between two electrodes that are in direct contact with the variable resistance material. Is possible. As a result, it is possible to reduce the current required when switching from the low resistance state to the high resistance state.
- the structure is not particularly limited, and a semiconductor memory device having any structure can be configured.
- FIG. 4 is a schematic diagram of a local current path 4 that assumes an ON state in an overhead perspective view of an MIM variable resistance element. It is a figure which shows the electrode area dependence characteristic of the ON resistance of a parallel plate type MIM type resistance change element. It is a figure which shows the qualitative relationship of the resistance value ( RON ) of a low resistance state in a 2 terminal type variable resistance element, and the electric current value ( IOFF ) required when switching to a high resistance state.
- FIG. 11 is a schematic diagram (enlarged view in a dotted frame in FIG. 10) around a Ni defect adjacent to a generation nucleus of a current path 4 in a Ni O element.
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Abstract
Description
上記特許文献3では、基板と、前記基板に形成されたスイッチング素子と、スイッチング素子に連結されたストレージノードと、を備える不揮発性メモリ装置において、ストレージノードは、スイッチング素子に連結され、イオンソースとして使われる下部電極と、下部電極上に形成され、その一部は下部電極と離隔されたデータ保存層と、下部電極から離隔された前記データ保存層の部分に側面が連結され、下部電極と離隔されている側部電極と、データ保存層上に形成された上部電極と、を備えるようにしている。
本発明にかかる抵抗変化素子は、
3つ以上の電極を有し、どの電極からも抵抗変化材料へのイオン供給が行われない抵抗変化素子であって、
1つの電極と、前記抵抗変化材料と、の間に抵抗変化を示さない材料が配置され、前記1つの電極以外の2つの電極に電流経路が形成されていることを特徴とする。
また、本発明にかかる半導体記憶装置は、
上記記載の抵抗変化素子を含んで構成することを特徴とする。
また、本発明にかかる製造方法は、
3つ以上の電極を有し、どの電極からも抵抗変化材料へのイオン供給が行われない抵抗変化素子の製造方法であって、
1つの電極と、前記抵抗変化材料と、の間に抵抗変化を示さない材料を配置し、前記1つの電極以外の2つの電極に電流経路を形成することを特徴とする。
また、本発明にかかる駆動方法は、
3つ以上の電極を有し、どの電極からも抵抗変化材料へのイオン供給が行われず、1つの電極と、前記抵抗変化材料と、の間に抵抗変化を示さない材料が配置された抵抗変化素子の駆動方法であって、
前記1つの電極以外の2つの電極に電流経路を形成することを特徴とする。
まず、図23、図3を参照しながら、本実施形態の抵抗変化素子の概要について説明する。
本実施形態の抵抗変化素子は、図23に示すように、3つ以上の電極(204,207,202)を有し、どの電極からも抵抗変化材料(205)へのイオン供給が行われない抵抗変化素子である。そして、1つの電極(207)と、抵抗変化材料(205)と、の間に抵抗変化を示さない材料(206)が配置され、その1つの電極(207)以外の2つの電極(204)に、図3に示す電流経路(4)が形成されていることを特徴とする。これにより、低抵抗状態から高抵抗状態に切り替える際に必要な電流を低減することが可能となる。以下、添付図面を参照しながら、本実施形態の抵抗変化素子について詳細に説明する。
本実施形態の抵抗変化素子は、図23に示す構造を構成することで、低抵抗状態から高抵抗状態に切り替える際に必要な電流を低減することが可能となる。
次に、図24~図27を参照しながら、本実施形態の抵抗変化素子の第1の構造について説明する。なお、図24~図27は、本実施形態の抵抗変化素子の第1の構造の製造工程を説明するための図であり、完成模式図が図27となる。
次に、図28を参照しながら、本実施形態の抵抗変化素子の第2の構造について説明する。なお、図28は、本実施形態の抵抗変化素子の第1の構造の製造工程を説明するための図であり、完成模式図を示している。第2の構造は、図28に示すように、抵抗変化材料205を2つの電極204間に埋め込んだ場合を示している。
次に、図29を参照しながら、本実施形態の抵抗変化素子の駆動方法について説明する。
基板に平行な面に配置された2つの電極間に、2端子型素子と同様にフォーミングにて低抵抗フィラメントを形成する。このフィラメントを切断する操作において、まずV1を印加し、フィラメントに電流を流すことでフィラメント周囲を加熱する。このとき流す電流iは、2端子型素子でフィラメント切断に必要な電流Iより小さくすることができる(i<I)。その後、ある一定時間、最も好ましくは10nsecから100nsec後にV2を第3、あるいは第3と第4の電極間に印加し、フィラメントと平行でない角度の電界を発生させる。これにより、フィラメントを形成していた格子欠陥が移動し、フィラメントが切断される。
以上の説明より明らかなように、本実施形態の抵抗変化素子は、抵抗変化材料に直接接する2つの電極以外に、抵抗変化材料との間に絶縁性が高い材料を介して接する付加的な電極を有する素子構造にしている。これにより、抵抗変化材料に直接接する2つの電極間に大電流を流すことなく、第3、もしくは第4の電極を利用して電流経路に平行にならない角度で電界を印加できる機構を実現することが可能となる。その結果、低抵抗状態から高抵抗状態に切り替える際に必要な電流を低減することが可能となる。
2 金属酸化物からなる抵抗変化材料
3 第2の電極
4 電流経路
101 電極
102 固体電解質
103 対向電極
104 電子
105 イオン化した電極構成元素(イオン)
106 対向電極界面で還元された電極構成元素(金属元素)
201 層間絶縁膜
202 第4の電極
203 絶縁体
204 第1、第2の電極
205 抵抗変化材料
206 絶縁体
207 第3の電極
301 電極
302 遷移金属酸化物
303 対向電極
304 電子
Claims (6)
- 3つ以上の電極を有し、どの電極からも抵抗変化材料へのイオン供給が行われない抵抗変化素子であって、
1つの電極と、前記抵抗変化材料と、の間に抵抗変化を示さない材料が配置され、前記1つの電極以外の2つの電極に電流経路が形成されていることを特徴とする抵抗変化素子。 - 請求項1記載の抵抗変化素子を含んで構成することを特徴とする半導体記憶装置。
- 3つ以上の電極を有し、どの電極からも抵抗変化材料へのイオン供給が行われない抵抗変化素子の製造方法であって、
1つの電極と、前記抵抗変化材料と、の間に抵抗変化を示さない材料を配置し、前記1つの電極以外の2つの電極に電流経路を形成することを特徴とする抵抗変化素子の製造方法。 - 3つ以上の電極を有し、どの電極からも抵抗変化材料へのイオン供給が行われず、1つの電極と、前記抵抗変化材料と、の間に抵抗変化を示さない材料が配置された抵抗変化素子の駆動方法であって、
前記1つの電極以外の2つの電極に電流経路を形成することを特徴とする駆動方法。 - 前記電流経路に電流を流しながら、前記1つの電極に電圧を印加し、前記電流経路を切断することを特徴とする請求項4記載の駆動方法。
- 前記2つの電極に電界を印加しつつ、前記電流経路を切断した時と逆向きの電圧を前記1つの電極に印加し、前記電流経路を形成することを特徴とする請求項5記載の駆動方法。
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