WO2009078242A1 - 不揮発性ラッチ回路及びそれを用いた論理回路 - Google Patents

不揮発性ラッチ回路及びそれを用いた論理回路 Download PDF

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Publication number
WO2009078242A1
WO2009078242A1 PCT/JP2008/070986 JP2008070986W WO2009078242A1 WO 2009078242 A1 WO2009078242 A1 WO 2009078242A1 JP 2008070986 W JP2008070986 W JP 2008070986W WO 2009078242 A1 WO2009078242 A1 WO 2009078242A1
Authority
WO
WIPO (PCT)
Prior art keywords
latch circuit
magnetoresistive elements
same
circuit
volatile latch
Prior art date
Application number
PCT/JP2008/070986
Other languages
English (en)
French (fr)
Inventor
Noboru Sakimura
Tadahiko Sugibayashi
Ryusuke Nebashi
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009546191A priority Critical patent/JP5392568B2/ja
Priority to US12/747,951 priority patent/US8243502B2/en
Publication of WO2009078242A1 publication Critical patent/WO2009078242A1/ja

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/18Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1659Cell access
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1673Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1675Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165Auxiliary circuits
    • G11C11/1693Timing circuits or methods
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/45Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of non-linear magnetic or dielectric devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B61/00Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00Galvanomagnetic devices
    • H10N50/10Magnetoresistive devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Static Random-Access Memory (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)

Abstract

不揮発性ラッチ回路は、ラッチ回路11と、第1磁気抵抗素子13-1及び第2磁気抵抗素子13-2と、電流供給部12とを具備する。ラッチ回路11は、データを一時的に保持する。第1磁気抵抗素子13-1及び第2磁気抵抗素子13-2は、絶縁膜を挟んで積層される第1磁性層と第2磁性層とを含む。電流供給部12は、ラッチ回路11の状態に応じて、第1磁気抵抗素子13-1及び第2磁気抵抗素子13-2の磁化状態を相補に変化させる。第1磁気抵抗素子13-1の第1磁性層と第2磁気抵抗素子13-2の第1磁性層とは直列接続されている。ラッチ回路11は、磁化状態に対応するデータを、ラッチ回路11が保持するデータとする機能を有する。
PCT/JP2008/070986 2007-12-14 2008-11-19 不揮発性ラッチ回路及びそれを用いた論理回路 WO2009078242A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009546191A JP5392568B2 (ja) 2007-12-14 2008-11-19 不揮発性ラッチ回路及びそれを用いた論理回路
US12/747,951 US8243502B2 (en) 2007-12-14 2008-11-19 Nonvolatile latch circuit and logic circuit using the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-324046 2007-12-14
JP2007324046 2007-12-14

Publications (1)

Publication Number Publication Date
WO2009078242A1 true WO2009078242A1 (ja) 2009-06-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/070986 WO2009078242A1 (ja) 2007-12-14 2008-11-19 不揮発性ラッチ回路及びそれを用いた論理回路

Country Status (3)

Country Link
US (1) US8243502B2 (ja)
JP (1) JP5392568B2 (ja)
WO (1) WO2009078242A1 (ja)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011129980A (ja) * 2009-12-15 2011-06-30 Mitsubishi Electric Corp 半導体集積回路
JP5365813B2 (ja) * 2009-01-28 2013-12-11 日本電気株式会社 不揮発ロジック回路
JP2015515750A (ja) * 2012-03-29 2015-05-28 インテル コーポレイション 磁気状態素子及び回路
US9135988B2 (en) 2011-09-09 2015-09-15 Nec Corporation Semiconductor device and control method of the same
JP2018019397A (ja) * 2016-07-19 2018-02-01 株式会社半導体エネルギー研究所 半導体装置
JP2018107626A (ja) * 2016-12-26 2018-07-05 国立大学法人東北大学 不揮発性ラッチ装置及び不揮発性フリップフロップ装置
JP2019033166A (ja) * 2017-08-08 2019-02-28 株式会社東芝 磁気メモリ
JPWO2021176646A1 (ja) * 2020-03-05 2021-09-10

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US8670266B2 (en) * 2012-01-30 2014-03-11 Qualcomm Incorporated Non-volatile flip-flop
US9196337B2 (en) 2012-04-25 2015-11-24 Qualcomm Incorporated Low sensing current non-volatile flip-flop
US8773896B2 (en) 2012-05-18 2014-07-08 Alexander Mikhailovich Shukh Nonvolatile latch circuit
US9147454B2 (en) * 2013-01-14 2015-09-29 Qualcomm Incorporated Magnetic tunneling junction non-volatile register with feedback for robust read and write operations
US9251883B2 (en) 2014-01-28 2016-02-02 Qualcomm Incorporated Single phase GSHE-MTJ non-volatile flip-flop
US9384812B2 (en) * 2014-01-28 2016-07-05 Qualcomm Incorporated Three-phase GSHE-MTJ non-volatile flip-flop
US9257970B1 (en) 2014-12-19 2016-02-09 Honeywell International Inc. Magnetic latch
US9729128B2 (en) * 2015-04-09 2017-08-08 Synopsys, Inc. Area-delay-power efficient multibit flip-flop
JP6724459B2 (ja) * 2016-03-23 2020-07-15 Tdk株式会社 磁気センサ
CN109643690B (zh) * 2017-04-14 2023-08-29 Tdk株式会社 磁壁利用型模拟存储元件、磁壁利用型模拟存储器、非易失性逻辑电路及磁神经元件
JP2019008859A (ja) 2017-06-28 2019-01-17 東芝メモリ株式会社 半導体装置
JP2022080162A (ja) * 2020-11-17 2022-05-27 ソニーセミコンダクタソリューションズ株式会社 半導体回路

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JP2004088469A (ja) * 2002-08-27 2004-03-18 Fujitsu Ltd 不揮発性データ記憶回路を有する集積回路装置
JP2007258460A (ja) * 2006-03-23 2007-10-04 Nec Corp 磁気メモリセル、磁気ランダムアクセスメモリ、半導体装置及び半導体装置の製造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5365813B2 (ja) * 2009-01-28 2013-12-11 日本電気株式会社 不揮発ロジック回路
JP2011129980A (ja) * 2009-12-15 2011-06-30 Mitsubishi Electric Corp 半導体集積回路
US9135988B2 (en) 2011-09-09 2015-09-15 Nec Corporation Semiconductor device and control method of the same
JP2015515750A (ja) * 2012-03-29 2015-05-28 インテル コーポレイション 磁気状態素子及び回路
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JP2018019397A (ja) * 2016-07-19 2018-02-01 株式会社半導体エネルギー研究所 半導体装置
JP2018107626A (ja) * 2016-12-26 2018-07-05 国立大学法人東北大学 不揮発性ラッチ装置及び不揮発性フリップフロップ装置
JP2019033166A (ja) * 2017-08-08 2019-02-28 株式会社東芝 磁気メモリ
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Also Published As

Publication number Publication date
JP5392568B2 (ja) 2014-01-22
JPWO2009078242A1 (ja) 2011-04-28
US8243502B2 (en) 2012-08-14
US20100265760A1 (en) 2010-10-21

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