WO2009063591A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
WO2009063591A1
WO2009063591A1 PCT/JP2008/002979 JP2008002979W WO2009063591A1 WO 2009063591 A1 WO2009063591 A1 WO 2009063591A1 JP 2008002979 W JP2008002979 W JP 2008002979W WO 2009063591 A1 WO2009063591 A1 WO 2009063591A1
Authority
WO
WIPO (PCT)
Prior art keywords
forming
wirings
insulating film
semiconductor device
resist mask
Prior art date
Application number
PCT/JP2008/002979
Other languages
English (en)
French (fr)
Inventor
Junichi Shibata
Takeshi Harada
Akira Ueki
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Publication of WO2009063591A1 publication Critical patent/WO2009063591A1/ja
Priority to US12/493,673 priority Critical patent/US8034693B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　半導体装置の製造方法は、基板上に絶縁膜を形成する工程と、絶縁膜の内部に複数の配線溝を形成する工程と、複数の配線溝の内部に複数の配線を形成する工程と、絶縁膜及び複数の配線の上に、複数の配線間の領域のうち選択的に領域を露出する開口部を有するレジストマスクを形成する工程と、レジストマスクを用いたエッチングにより、複数の配線間の領域のうち選択的に露出した領域の絶縁膜を除去してエアギャップ溝を形成する工程と、レジストマスクを除去した後に、複数の配線上を覆うように層間絶縁膜を堆積することによってエアギャップを形成する工程とを含む。
PCT/JP2008/002979 2007-11-12 2008-10-21 半導体装置の製造方法 WO2009063591A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/493,673 US8034693B2 (en) 2007-11-12 2009-06-29 Method for fabricating semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-293136 2007-11-12
JP2007293136A JP2009123743A (ja) 2007-11-12 2007-11-12 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/493,673 Continuation US8034693B2 (en) 2007-11-12 2009-06-29 Method for fabricating semiconductor device

Publications (1)

Publication Number Publication Date
WO2009063591A1 true WO2009063591A1 (ja) 2009-05-22

Family

ID=40638447

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/002979 WO2009063591A1 (ja) 2007-11-12 2008-10-21 半導体装置の製造方法

Country Status (3)

Country Link
US (1) US8034693B2 (ja)
JP (1) JP2009123743A (ja)
WO (1) WO2009063591A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018125396A (ja) * 2017-01-31 2018-08-09 東芝メモリ株式会社 半導体装置およびその製造方法
US10396116B2 (en) 2015-03-31 2019-08-27 Sony Semiconductor Solutions Corporation Solid-state image-capturing element and electronic device
US11929380B2 (en) 2015-03-31 2024-03-12 Sony Semiconductor Solutions Corporation Solid-state image-capturing element having floation diffusion and hollow regions
JP7471305B2 (ja) 2019-04-12 2024-04-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 積層された導体ライン及び空隙を有する半導体チップ

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4307664B2 (ja) 1999-12-03 2009-08-05 株式会社ルネサステクノロジ 半導体装置
JP2008205165A (ja) * 2007-02-20 2008-09-04 Toshiba Corp 半導体集積回路装置
US8198174B2 (en) * 2009-08-05 2012-06-12 International Business Machines Corporation Air channel interconnects for 3-D integration
JP2011066126A (ja) * 2009-09-16 2011-03-31 Elpida Memory Inc 半導体記憶装置およびその製造方法
US8456009B2 (en) 2010-02-18 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having an air-gap region and a method of manufacturing the same
US8569891B1 (en) * 2010-03-16 2013-10-29 Micron Technology, Inc. Forming array contacts in semiconductor memories
US8203212B2 (en) * 2010-04-01 2012-06-19 International Business Machines Corporation Air gaps in a multilayer integrated circuit and method of making same
US8288268B2 (en) 2010-04-29 2012-10-16 International Business Machines Corporation Microelectronic structure including air gap
CN101982879A (zh) * 2010-10-15 2011-03-02 复旦大学 一种低介电常数介质与铜互连的结构及其集成方法
US8754338B2 (en) * 2011-05-28 2014-06-17 Banpil Photonics, Inc. On-chip interconnects with reduced capacitance and method of afbrication
US9136128B2 (en) * 2011-08-31 2015-09-15 Micron Technology, Inc. Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials
CN103021929A (zh) * 2011-09-22 2013-04-03 中芯国际集成电路制造(北京)有限公司 半导体器件制造方法
KR101978969B1 (ko) * 2013-06-17 2019-05-17 삼성전자주식회사 반도체 소자
KR102154112B1 (ko) 2013-08-01 2020-09-09 삼성전자주식회사 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법
US9230911B2 (en) 2013-12-30 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming the same
KR102092863B1 (ko) 2013-12-30 2020-03-24 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102229206B1 (ko) * 2014-04-07 2021-03-18 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102247918B1 (ko) 2014-04-07 2021-05-06 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9583434B2 (en) * 2014-07-18 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Metal line structure and method
US10163792B2 (en) 2014-07-28 2018-12-25 Qualcomm Incorporated Semiconductor device having an airgap defined at least partially by a protective structure
US9847249B2 (en) * 2014-11-05 2017-12-19 Sandisk Technologies Llc Buried etch stop layer for damascene bit line formation
US10319701B2 (en) * 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
US9449871B1 (en) * 2015-11-18 2016-09-20 International Business Machines Corporation Hybrid airgap structure with oxide liner
KR102471641B1 (ko) * 2016-02-04 2022-11-29 에스케이하이닉스 주식회사 퓨즈구조 및 그를 포함하는 반도체장치
US9666528B1 (en) * 2016-02-23 2017-05-30 International Business Machines Corporation BEOL vertical fuse formed over air gap
KR102645957B1 (ko) 2016-03-22 2024-03-08 삼성전자주식회사 반도체 장치 및 그의 제조 방법
JP2017228599A (ja) * 2016-06-21 2017-12-28 ソニー株式会社 半導体装置、及び半導体装置の製造方法
US9892961B1 (en) * 2016-08-09 2018-02-13 International Business Machines Corporation Air gap spacer formation for nano-scale semiconductor devices
KR102655189B1 (ko) 2016-09-30 2024-04-04 삼성전자주식회사 반도체 장치 및 이의 제조 방법
WO2018125063A1 (en) * 2016-12-27 2018-07-05 Intel Corporation Encapsulation of air gaps in interconnects
WO2018125124A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Creating dielectric helmet films using pulsed gas deposition
US10164009B1 (en) 2017-08-11 2018-12-25 Micron Technology, Inc. Memory device including voids between control gates
US10453855B2 (en) 2017-08-11 2019-10-22 Micron Technology, Inc. Void formation in charge trap structures
US10446572B2 (en) 2017-08-11 2019-10-15 Micron Technology, Inc. Void formation for charge trap structures
US10680006B2 (en) 2017-08-11 2020-06-09 Micron Technology, Inc. Charge trap structure with barrier to blocking region
JP2019054199A (ja) * 2017-09-19 2019-04-04 東芝メモリ株式会社 半導体装置
US11264272B2 (en) 2018-01-11 2022-03-01 Sony Semiconductor Solutions Corporation Semiconductor device and method for manufacturing the same, and electronic apparatus
US10896888B2 (en) * 2018-03-15 2021-01-19 Microchip Technology Incorporated Integrated circuit (IC) device including a force mitigation system for reducing under-pad damage caused by wire bond
US11309266B2 (en) * 2020-05-28 2022-04-19 Nanya Technology Corporation Semiconductor device structure with air gap and method for forming the same
CN115513171A (zh) * 2022-10-25 2022-12-23 长鑫存储技术有限公司 半导体结构及其制造方法、存储系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1012730A (ja) * 1996-06-27 1998-01-16 Nec Corp 半導体集積回路装置及びその製造方法
JP2004241635A (ja) * 2003-02-06 2004-08-26 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2006120988A (ja) * 2004-10-25 2006-05-11 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
JP2007188919A (ja) * 2006-01-11 2007-07-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242336B1 (en) * 1997-11-06 2001-06-05 Matsushita Electronics Corporation Semiconductor device having multilevel interconnection structure and method for fabricating the same
US6524948B2 (en) * 2000-10-13 2003-02-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US7138329B2 (en) * 2002-11-15 2006-11-21 United Microelectronics Corporation Air gap for tungsten/aluminum plug applications
JP4956919B2 (ja) * 2005-06-08 2012-06-20 株式会社日立製作所 半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1012730A (ja) * 1996-06-27 1998-01-16 Nec Corp 半導体集積回路装置及びその製造方法
JP2004241635A (ja) * 2003-02-06 2004-08-26 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2006120988A (ja) * 2004-10-25 2006-05-11 Matsushita Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
JP2007188919A (ja) * 2006-01-11 2007-07-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10396116B2 (en) 2015-03-31 2019-08-27 Sony Semiconductor Solutions Corporation Solid-state image-capturing element and electronic device
US10797097B2 (en) 2015-03-31 2020-10-06 Sony Semiconductor Solutions Corporation Solid-state image-capturing element and electronic device
US11183528B2 (en) 2015-03-31 2021-11-23 Sony Semiconductor Solutions Corporation Solid-state image-capturing element and having floating diffusion and hollow regions
US11929380B2 (en) 2015-03-31 2024-03-12 Sony Semiconductor Solutions Corporation Solid-state image-capturing element having floation diffusion and hollow regions
JP2018125396A (ja) * 2017-01-31 2018-08-09 東芝メモリ株式会社 半導体装置およびその製造方法
JP7471305B2 (ja) 2019-04-12 2024-04-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 積層された導体ライン及び空隙を有する半導体チップ

Also Published As

Publication number Publication date
JP2009123743A (ja) 2009-06-04
US20090263951A1 (en) 2009-10-22
US8034693B2 (en) 2011-10-11

Similar Documents

Publication Publication Date Title
WO2009063591A1 (ja) 半導体装置の製造方法
TW200802536A (en) Method of manufacturing semiconductor device
TW200834245A (en) Method for manufacturing semiconductor device with four-layered laminate
WO2008042732A3 (en) Recessed sti for wide transistors
WO2011059961A3 (en) Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations
TW200707757A (en) Method for forming contact hole and method for fabricating thin film transistor plate using the same
TW200737357A (en) Semiconductor structure and method of fabricating thereof
TW200603248A (en) Method for forming a resist protect layer
TW200731470A (en) Method for fabricating semiconductor device
WO2009054413A1 (ja) 半導体装置の作製方法
TW200737344A (en) Method for manufacturing semiconductor device
TWI257177B (en) Manufacturing processes for a thin film transistor and a pixel structure
TW200724709A (en) A method for forming a mask pattern for ion-implantation
WO2011010889A3 (en) Flexible printed circuit board and method for manufacturing the same
JP2008513999A5 (ja)
TW200634932A (en) Method for fabricating semiconductor device
WO2008117426A1 (ja) 半導体装置、および製造方法
TW200507173A (en) Method for manufacturing semiconductor device
WO2005057681A8 (en) Process for removing an organic layer during fabrication of an organic electronic device and the organic electronic device formed by the process
TW200733189A (en) Method for manufacturing semiconductor device
TW200644068A (en) Manufacturing method for gate dielectric layer
WO2009075052A1 (ja) 半導体装置及びその製造方法
JP2011192846A5 (ja)
US8785115B2 (en) Photoresist removal method and patterning process utilizing the same
TW200701365A (en) Method for forming contact hole in semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08849509

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08849509

Country of ref document: EP

Kind code of ref document: A1