WO2009014195A1 - 半導体装置、半導体装置の製造方法、高キャリア移動度トランジスタおよび発光装置 - Google Patents
半導体装置、半導体装置の製造方法、高キャリア移動度トランジスタおよび発光装置 Download PDFInfo
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- WO2009014195A1 WO2009014195A1 PCT/JP2008/063335 JP2008063335W WO2009014195A1 WO 2009014195 A1 WO2009014195 A1 WO 2009014195A1 JP 2008063335 W JP2008063335 W JP 2008063335W WO 2009014195 A1 WO2009014195 A1 WO 2009014195A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 252
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0891—Source or drain regions of field-effect devices of field-effect transistors with Schottky gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
Definitions
- the present invention relates to a semiconductor device, a semiconductor device manufacturing method, a high carrier mobility transistor, and a light emitting device.
- the present invention relates to a semiconductor device that reduces the contact resistance of an electrode that is ohmic-connected to a semiconductor layer, a method for manufacturing the semiconductor device, a high carrier mobility, and a light emitting device.
- the contact resistance can be reduced by optimizing the structure of the metal contact and the processing conditions of R TA.
- the contact resistance increases significantly when deviating from the optimum condition.
- This document merely discloses optimization conditions under specific conditions for metal contacts with a focus on reducing contact resistance. It is desirable to provide technology for reducing the contact resistance of metal contacts that are not sensitive to manufacturing conditions.
- a semiconductor layer containing N and Ga, a conductive layer ohmic-connected to the semiconductor layer, and a metal at the interface between the semiconductor layer and the conductive layer there is provided a semiconductor device comprising: a metal distribution region in which is distributed and a metal intrusion region in which a metal atom enters the semiconductor layer.
- FIG. 1 shows a partial cross section of a semiconductor device 100 according to the present embodiment.
- FIG. 2 shows an example of a cross section in the manufacturing process of the semiconductor device 100.
- FIG. 3 shows an example of a cross section in the manufacturing process of the semiconductor device 100.
- FIG. 4 shows an example of a cross section in the manufacturing process of the semiconductor device 100.
- FIG. 5 shows an example of a cross section in the manufacturing process of the semiconductor device 100.
- FIG. 6 shows an example of a cross section in the manufacturing process of the semiconductor device 100.
- Figure 7 shows the characteristic contact resistance and Ti penetration depth shown in Table 1 as a function of the Au film thickness.
- FIG. 8 shows the characteristic contact resistance of Example 2 and Examples 5-7 as a function of heat treatment temperature.
- FIG. 9 shows an EM image obtained by observing the contact portion of the semiconductor device 100 under the manufacturing conditions of the second embodiment.
- Figure 1 shows a Ti matting image by EDX in the same field of view as the TEM image in Figure 9.
- Fig. 1 shows a Ga mapping image by EDX in the same field of view as the TEM image in Fig. 9.
- Fig. 1 shows the A 1 matbing image by EDX in the same field of view as the TEM image in Fig. 9.
- Figure 1 also shows the TEM image in Comparative Example 1.
- Fig. 1 shows the Ti mapping image by EDX in the same field of view as the TEM image in Fig. 13
- Fig. 1 shows a Ga mapping image by EDX in the same field of view as the TEM image in Fig. 1 3
- Figure 1 shows the A1 mapping image by EDX in the same field of view as the TEM image in Figure 13.
- FIG. 1 shows a light emitting device 300 as an example of the semiconductor device 100 of the present embodiment.
- FIG. 1 shows a high carrier mobility transistor 400 as an example of the semiconductor device 100 of this embodiment. Explanation of symbols
- Second semiconductor layer 108 Conductive layer, 1 1 0 Metal distribution region
- 300 light emitting device 302 first semiconductor layer, 304 second semiconductor layer
- FIG. 1 shows a partial cross section of a semiconductor device 100 of the present embodiment.
- the semiconductor device 100 of the present embodiment may be, for example, an FET (Fi ld E ffe c t T r a n s i s tor), and the cross section shown in FIG. 1 shows, for example, the contact portion of the source or drain of FET.
- the semiconductor device 100 includes a substrate 102, a first semiconductor layer 104, a second semiconductor layer 106, a conductive layer 108, a metal distribution region 110, and a metal intrusion region 112.
- Substrate 102 for example, single crystal A 1 2 ⁇ 3 (sapphire), S i C, may be S i, etc., of the single crystal A 1 2 ⁇ 3 isosurface of G a N single crystal Epitakisharu A growth layer may be included.
- epitaxy growth methods include metal organic vapor phase epitaxy and molecular beam epitaxy.
- the first semiconductor layer 104 and the second semiconductor layer 106 are examples of semiconductor layers containing N and Ga.
- the interface between the first semiconductor layer 104 and the second semiconductor layer 106 is an example of a semiconductor heterojunction interface containing N and Ga.
- the first semiconductor layer 104 and the second semiconductor layer 106 may contain a Group 3 element that forms a mixed crystal by substituting Ga, for example, A1.
- a second semiconductor layer 1 06, for example A 1 X G a! _ X N (0 ⁇ ⁇ 1) layer can be exemplified.
- the GaN layer and the A 1 GaN layer can be formed by an epitaxy method such as metal organic chemical vapor deposition or molecular beam epitaxy.
- the GaN layer and the AlGaN layer may be intrinsic semiconductor layers into which no impurity is introduced, and may be introduced with an impurity of P-type or N-type conductivity.
- the conductive layer 108 is ohmically connected to the second semiconductor layer 106.
- the conductive layer 10 8 functions as an ohmic contact electrode of the semiconductor device 100.
- the conductive layer 108 may be ohmic connected to the first semiconductor layer 104 through the metal intrusion region 112.
- a 1 can be exemplified as the main component of the conductive layer 108.
- the conductive layer 108 can be formed by, for example, film formation by metal sputtering or vapor deposition and patterning using a photolithography method.
- the conductive layer 108 may be, for example, a single layer of A1, or may have a multilayer laminated structure in which a plurality of materials are laminated.
- a conductive intermediate layer and a cap layer may be formed on the conductive layer 108.
- the intermediate layer is used as an adhesive layer or compatibility prevention layer between the conductive layer 1 08 and the cap layer, and the cap layer is the conductive layer 1 08. It can function as an antioxidant layer or a ball-up prevention layer.
- Examples of the intermediate layer include Ni, Ta, Nb, W, Pt, Mo, and Au.
- the cap layer include Ni, Ta, Nb, W, Pt :, Mo, and Au.
- the metal distribution region 110 exists at the interface between the second semiconductor layer 106 and the conductive layer 108, and the metal distribution region 110 exists by uniformly distributing metal.
- An example of the metal distributed in the metal distribution region 110 is Ti. Note that the metal distributed in the metal distribution region 110 does not exist only in the metal distribution region 110, but may exist in the conductive layer 108.
- the metal intrusion region 1 1 2 exists at least in the second semiconductor layer 1 0 6, and atoms of the same type of metal as the metal distributed in the metal distribution region 1 1 0 intrude into the metal intrusion region 1 1 2. Exist.
- the metal intrusion region 1 1 2 may also exist in the first semiconductor layer 10 4 through the second semiconductor layer 10 6.
- the cross-sectional shape of the metal intrusion region 1 1 2 is displayed in a pseudo circle, but is not limited to a circle.
- the metal intrusion region 112 is formed in the second semiconductor layer 106, which is a semiconductor layer, so that the conductive layer 108, which functions as an ohmic contact electrode, is formed.
- Contact resistance can be reduced. The effect of reducing the contact resistance is obtained by the physical property of forming the metal intrusion region 1 1 2 and exceeds the effect obtained by optimizing the manufacturing process conditions.
- Ti can be exemplified as the metal that enters the metal intrusion region 1 1 2.
- Ti may combine with N contained in the first semiconductor layer 104 or the second semiconductor layer 106 to form TiN. Since T i N has a small work function, T i in the metal intrusion region 1 1 2 constitutes T i N, thereby reducing the barrier between the metal and the semiconductor and further reducing the contact resistance.
- the metal intrusion region 1 1 2 is an interface between the second semiconductor layer 1 0 6 and the semiconductor layer. It is formed unevenly in parallel planes. Thereby, the contact area between the metal intrusion region 112 and the first semiconductor layer 104 or the second semiconductor layer 106 is increased, and the contact resistance can be reduced.
- the metal intrusion region 1 1 2 is formed so as to reach a region where the intrusion depth in the second semiconductor layer 10 6 is 6 nm or more. As a result, the contact area of the metal intrusion region 1 1 2 in the semiconductor layer can be increased, and the contact resistance can be reduced.
- the metal intrusion region 1 1 2 may be formed to reach the junction interface between the first semiconductor layer 10 4 and the second semiconductor layer 10 6, that is, the hetero junction interface.
- a device such as a high electron mobility transistor that forms a channel by forming a two-dimensional electron gas at the heterojunction interface
- a low resistance metal intrusion region is formed between the conductive layer 108 and the channel region. 1 1 2 can be connected. As a result, the resistance of the path from the conductive layer 108 to the channel region can be reduced.
- the metal intrusion region 1 12 may be formed in the second semiconductor layer 106, that is, a region of the semiconductor layer that does not reach the heterojunction interface. For example, when a quantum well is formed by a plurality of heterojunctions, it is possible to suppress scattering of carriers due to intruding metal in the quantum well.
- More metal may enter the metal intrusion region 1 1 2 than in the conductive layer 1 0 8. Further, the concentration of the metal in the metal intrusion region 1 1 2 may be in a range of a molar fraction of 1% or more and less than 100%. The Ga concentration in the metal intrusion region 1 1 2 may be lower than the Ga concentration in the first semiconductor layer 1 0 4 and the second semiconductor layer 1 0 6 other than the metal intrusion region 1 1 2, for example, 50% It may be formed lower. Metal intrusion area 1 1 2 is surrounded by a group 3 element such as A
- a group 3 element such as A 1 may be present surrounding the metal intrusion region 1 1 2.
- the characteristic properties of these metal intrusion regions 1 1 2 are the metal distribution region 1 1 0 and gold It is obtained by forming the genus invasion region 1 1 2 by the following method. That is, a metal layer mainly composed of metal (for example, T i) is formed on the first semiconductor layer 104 and the second semiconductor layer 106. A diffusion prevention layer for preventing diffusion of a metal (for example, ⁇ ⁇ ) constituting the metal layer is formed. Further, a conductive layer 10 8 is formed, and the metal layer, the diffusion prevention layer, and the conductive layer 10 8 are heat-treated. As a result, the metal distribution region 110 and the metal intrusion region 112 are formed. The material constituting the diffusion prevention layer may have a melting point higher than that of the material constituting the conductive layer 108, for example, A1. it can.
- the second semiconductor layer 106 is formed.
- the first semiconductor layer 104 and the second semiconductor layer 106 can be formed by an epitaxy method such as a metal organic chemical vapor deposition method or a molecular beam epitaxy method.
- An example of the film thickness of the first semiconductor layer 104 is 2 m, and an example of the film thickness of the second semiconductor layer 106 is 30 nm.
- the first semiconductor layer 104 and the second semiconductor layer 106 can be appropriately doped with impurities serving as donors or acceptors depending on the device configuration of the semiconductor device 100, as shown in FIG. 2
- a patterned resist film 120 is formed on the upper surface of the semiconductor layer 106.
- the resist film 120 is coated with resist on the entire surface of the second semiconductor layer 106 and patterned by photolithography so that an opening is formed in a region where the conductive layer 108 is formed.
- a process corresponding to the device configuration of the semiconductor device 100 can be completed before the formation of the resist film 120 for forming the conductive layer 108. For example, processes such as ion implantation and annealing of impurities into the source and drain regions of the FET and formation of the gate electrode are completed. You can end.
- a metal layer 130, a diffusion prevention layer 1 32, a conductive layer 1 34, an intermediate layer 1 36, and a cap layer 1 38 are sequentially formed.
- the metal layer 130, the diffusion preventing layer 1 32, the conductive layer 1 34, the intermediate layer 1 36, and the cap layer 1 38 can be formed by, for example, vapor deposition, sputtering, or other metal thin film deposition methods.
- the metal layer 130 includes a metal that forms the metal distribution region 1 1 0 and the metal intrusion region 1 1 2.
- the diffusion prevention layer 1 3 2 prevents diffusion of the metal constituting the metal layer 1 30.
- the conductive layer 1 34 is processed into the conductive layer 108.
- Ti can be exemplified as a metal mainly constituting the metal layer 130, and a film thickness of the Ti layer can be exemplified as 20 nm.
- a 1 can be exemplified as a material mainly constituting the conductive layer 134, and a film thickness of the A 1 layer can be exemplified as 180 nm.
- Ni can be exemplified as a metal mainly constituting the intermediate layer 136, and 25 nm can be exemplified as the film thickness of the Ni layer.
- Au can be exemplified as a metal mainly constituting the cap layer 138, and the film thickness of the Au film can be exemplified as 30 nm.
- Ta, Nb, W, Pt, or Mo can be applied as a material for forming the intermediate layer 136 and the cap layer 138.
- the material constituting the diffusion prevention layer 1 32 has a melting point higher than that of the material constituting the conductive layer 1 34. Since the diffusion preventing layer 1 32 has a higher melting point than the conductive layer 1 34, diffusion of the metal constituting the metal layer 130 into the conductive layer 1 34 can be prevented even when the conductive layer 1 34 is melted.
- the material mainly constituting the diffusion preventing layer 1 32 include Au, Ag, Cu, W, Mo, Cr, Nb, Pt, Pd, and Si. Of the metals exemplified above, Au Ag, Cu, Pt, Pd, and Si are preferred. Further, Au, Ag, Cu, and Si are more preferable as a material mainly constituting the diffusion prevention layer 132, and Au is particularly preferable.
- Anti-diffusion layer 1 32 is composed of A u, Ag, Cu, W, Mo, Cr, N It may be any material selected from b, Pt, Pd and S i, or their alloys, or their nitrides or oxides. Among these, any metal or an alloy thereof is preferable.
- the diffusion prevention layer 1 32 can be formed with a film thickness of 10 nm to 500 nm, preferably 15 nm to 200 nm, more preferably 25 nm to 80 nm.
- the resist film 120 is peeled off to form a patterned metal layer 140, a diffusion prevention layer 142, a conductive layer 144, an intermediate layer 146, and a cap layer 148.
- a patterned metal layer 140 As shown in FIG. 5, for example, the resist film 120 is peeled off to form a patterned metal layer 140, a diffusion prevention layer 142, a conductive layer 144, an intermediate layer 146, and a cap layer 148.
- the patterning by the lift-off method by peeling the resist film 120 is illustrated, but patterning may be performed by dry etching or the like.
- the diffusion preventing layer 142, the conductive layer 144, the intermediate layer 146, and the cap layer 148 for example, heat treatment by RTA is performed.
- the metal layer 140 is melted or softened, and the metal constituting the metal layer 140 is diffused into the first semiconductor layer 104 and the second semiconductor layer 106.
- the diffusion preventing layer 142 exists above the metal layer 140, diffusion of the metal constituting the metal layer 140 in the direction of the conductive layer 144 is suppressed. Therefore, the metal composing the metal layer 140 is diffused in the direction of the first semiconductor layer 104 and the second semiconductor layer 106 under a stronger concentration gradient. As a result, a metal distribution region 110 and a metal intrusion region 112 are formed.
- the conductive layer 144 is also melted or softened by the heat treatment, and the diffusion preventing layer 14
- the intermediate layer 146 and the cap layer 148 may be fused so as not to stop the original shape.
- the conductive layer 108 formed as a result of the heat treatment includes the elements constituting the diffusion prevention layer 142, the intermediate layer 146, and the cap layer 148 in addition to the elements constituting the conductive layer 144. Will be. Even when the intermediate layer 146 and the cap layer 148 are not formed, the semiconductor of this embodiment It is possible to constitute the device 100. In such a case, it goes without saying that the elements constituting the intermediate layer 146 and the cap layer 148 are not included in the conductive layer 108 formed as a result of the heat treatment.
- the heat treatment can be performed in a temperature range of 65 Ot: or more and 900 or less, preferably a temperature range of 750 or more and 900 or less, and more preferably a temperature range of 790 or more and 870 or less.
- Examples of the heat treatment conditions in this embodiment include a nitrogen atmosphere, a heat treatment temperature of 800 t: and a treatment time of 30 seconds.
- Table 1 shows the evaluation results of the contact resistance of the contact portion in the semiconductor device 100 manufactured as described above.
- the contact resistance was evaluated by changing the film thickness of the Au layer which is the diffusion prevention layer 142 (diffusion prevention layer 1 32).
- the cross section of the contact portion in each example is observed with TEM (Transmission Electron Microscope) and EDX (Energy Dispersive X-rayspectrometer), and the size of the metal intrusion region 1 12 is determined as T i. The depth of penetration was evaluated.
- Table 1 Metal film thickness (nm) Characteristic contact resistance Ti penetration depth
- Example 1 Ti Au Al Ni Au ( ⁇ / cm 2 ) (rm) Example 1 20 60 180 25 30 6.9X 10— 6 240 Example 2 20 30 180 25 30 7.4X 10— 6 222 Example 3 20 20 180 25 30 1 ⁇ 2 ⁇ 10- 5 93 example 4 20 10 180 25 30 2.9X 10- 5 unevaluated Comparative example 1 20 one 180 25 30 5.9X 10- 5 5 or less
- the thickness of the Ti layer which is the metal layer 140 (metal layer 130)
- the thickness of the A1 layer which was the conductive layer 144 (conductive layer 134) was 180 nm.
- the thickness of the Ni layer as the intermediate layer 146 was 25 nm
- the thickness of the Au layer as the cap layer 148 was 30 nm
- the thickness of the Au layer which is the diffusion prevention layer 142 is 60 nm in Example 1, 30 nm in Example 2, and 2 in Example 3.
- Example 4 it was 10 nm.
- the heat treatment was an RTA treatment in a nitrogen atmosphere, 800T: 30 seconds.
- the contact resistance was evaluated by two-terminal probing using the TLM (T ran sm s s i o n L ine Mode 1) method.
- the Ti intrusion depth is determined by identifying a region with a high Ti concentration as a metal intrusion region 1 12 from cross-sectional observation by TEM and observation of a Ti profile by EDX in the same field of view. It was evaluated as the reach distance in the depth direction. Further, as Comparative Example 1, a layer without the diffusion prevention layer 142 (diffusion prevention layer 1 32) was prepared and evaluated in the same manner as in the example.
- Figure 7 shows the characteristic contact resistance and Ti penetration depth shown in Table 1 as a function of the Au film thickness. Characteristic contact resistance is expressed logarithmically. In Fig. 7, the black square plot shows the measured value of the logarithmic characteristic contact resistance, and the black circle plot shows the measured value of the Ti penetration depth. X represents the characteristic contact resistance value of Comparative Example 1.
- the solid line 202 and the solid line 204 indicate the logarithmic characteristic contact resistance experimental line, and the broken line 206 indicates the Ti penetration depth experimental curve.
- the characteristic contact resistance decreases as the thickness of the Au layer which is the diffusion prevention layer 142 (diffusion prevention layer 1 32) increases. It can also be seen that the Ti penetration depth increases as the A u film thickness increases. This result directly shows the effect of diffusion prevention layer 1 42 (diffusion prevention layer 1 32) on the reduction of contact resistance. i It shows that the characteristic contact resistance decreases as the penetration depth increases.
- Fig. 7 show that the contact resistance can be reduced to about half that of Comparative Example 1 with an Au film thickness of about 10 nm. A large contact resistance reduction effect is obtained when the Au film thickness is 10 nm or more. It is shown that.
- the experimental straight lines 202 and 204 indicate that there is an inflection point of the logarithmic characteristic contact resistance when the Au film thickness is in the range of 20 to 30 nm. This seems to suggest that the mechanism of contact resistance reduction is changing.
- the same suggestion can be seen from the fact that the experimental curve indicated by the broken line 206 is inflected around the Au film thickness of 30 nm. In other words, even if the Au film thickness is increased far beyond 60 nm, a large reduction in contact resistance is difficult to expect.
- the film thickness of the Au layer which is the diffusion prevention layer 142 (diffusion prevention layer 1 32) should be 10 nm or more, preferably 25 nm or more.
- the upper limit of the thickness is preferably 500 nm or less in consideration of ease of processing. Considering that the effect of reducing contact resistance is reduced when the Au film thickness is 30 nm or more, and further considering the ease of processing, the upper limit value of the Au film thickness is more preferably 200 nm or less or 80 nm or less. .
- Table 2 shows the evaluation results of the contact resistance of the contact portion in the semiconductor device 100 in which the manufacturing conditions of the semiconductor device 100 other than the heat treatment temperature are the same as in Example 2.
- the heat treatment temperatures of Example 5, Example 6, and Example 7 were set to 750, 850 :, and 900T :, respectively.
- FIG. 8 shows the characteristic contact resistance of Example 2 and Examples 5-7 as a function of heat treatment temperature.
- the black circle plot shows the measured value, and the solid line shows the experimental curve.
- Figure 8 shows that there is an optimum heat treatment temperature that reduces the characteristic contact resistance.
- the heat treatment temperature is preferably in the range of 75 0 to 90 0 ⁇ , more preferably in the range of 7 90 to 8 70. Table 3
- Example 8 is a semiconductor manufactured under the same manufacturing conditions as in Example 1 using a substrate (Epitaxial substrate for HEMT) on which an A 1 GaN layer having a composition of 0.465 is formed. This is an example of the device 100.
- the epitaxy substrate for HEM T can be obtained, for example, as an A 1 G aNZG aN epoxy wafer (product name) from NTT Advanced Technology Corporation.
- Example 9 is an example of a semiconductor device 100 fabricated using a substrate (HEMT epitaxial substrate) on which an A 1 GaN layer having a composition of 0.24 is formed under the same manufacturing conditions as in Example 1. It is.
- Example 10 is an example of a semiconductor device 100 that is manufactured under the same manufacturing conditions as Example 1 using an epitaxial substrate with zero A 1 composition.
- the epitaxial substrate of Example 10 was n-type conductivity type.
- the concentration of Si giving n-type was controlled to 2.0 X 10 18 cm- 3 . —
- the characteristic contact resistance according to the TLM (Tran Sm i ss i o n Line Model 1) method was evaluated by 4-terminal probing.
- the Ti intrusion depth is determined by identifying a region with a high Ti concentration as a metal intrusion region 1 12 from cross-sectional observation by TEM and observation of a Ti profile by EDX in the same field of view. The reach distance in the depth direction was evaluated.
- Comparative Example 2 a semiconductor device was fabricated under the same manufacturing conditions as in Comparative Example 1 in Table 1 using a substrate with an A 1 GaN layer with an A 1 composition of 0.465 (epitaxial substrate for HE MT) did.
- Comparative Example 3 a semiconductor device was fabricated under the same manufacturing conditions as Comparative Example 1 in Table 1 using an epitaxial substrate having a zero A1 composition.
- the epitaxy substrate of Comparative Example 3 was of n-type conductivity as in Example 10. Comparative Example 2 and Comparative Example 3 were evaluated in the same manner as in Examples 8-10.
- a 1 G a N layer substrate with an A 1 composition of 0.35 or more (EPMT for HEMT) (Chiral substrate) is expected to be a practically advantageous substrate because of its wide-band gap, but it is expected that the contact resistance will increase.
- the technology of this embodiment as shown in Example 8 of Table 3, even if a substrate (an HEMT epitaxial substrate) on which an A 1 GaN layer having an A 1 composition of 0.35 or more is used, The resistance value can be reduced to the same level as that of the conventional semiconductor device 100 having the A 1 composition of about 0.24 shown in the ninth embodiment.
- the resistance value is about the same as the conventional semiconductor device 100 with an A 1 composition of about 0.24. It can be expected that it can be reduced. That is, the technique of the present embodiment can realize both a wide band gap and an ohmic connection with a low contact resistance.
- Example 1 and Comparative Example 1 Example 10 and Comparative Example 3 with 8 1 compositions of 0.465, 0.24, and 0, respectively.
- the following matters can be considered. That is, the comparison of eight 1 composition and actual ⁇ 8 of 0.465 and Comparative Example 2, 2 times 10 than the contact resistance of the contact resistance Comparative Example 2 Example 8 small, A 1 composition
- the contact resistance of Example 1 is about 10 to 1 times smaller than the contact resistance of Comparative Example 1.
- Comparative Example 3 is about 0.8 times smaller than the contact resistance.
- FIG. 9 shows a TEM image of the contact portion of the semiconductor device 100 observed under the manufacturing conditions of Example 2. Since the boundary between the first semiconductor layer 104 and the second semiconductor layer 106 is difficult to read, it is labeled as the same region, but the second semiconductor layer 106 is formed above the first semiconductor layer 104. . A conductive layer 108 is formed on the second semiconductor layer 106. An interface IF is formed at the boundary between the second semiconductor layer 106 and the conductive layer 108.
- Figure 10 shows a Ti matting image by EDX in the same field of view as the TEM image in Figure 9. The higher the Ti density, the more white it is displayed. From FIG. 9, it can be seen that the white area at the interface IF between the second semiconductor layer 106 and the conductive layer 108, that is, the metal distribution region 1
- the metal intrusion region 112 is unevenly formed on the plane to which the interface IF belongs.
- Figure 11 shows a Ga mapping image by EDX in the same field of view as the TEM image in Figure 9. The higher the Ga concentration, the more white it is displayed. From Figure 1 1, the metal intrusion area 1 1
- the Ga concentration in the region where 2 is formed decreases.
- the decrease in the Ga concentration in the metal intrusion region 1 12 in Example 2 is measured to be reduced to 10 to 43% compared to the region that is not the metal intrusion region 1 12.
- Figure 12 shows an A1 matbing image by EDX in the same field of view as the TEM image in Figure 9. The higher the A 1 density is, the more white it is displayed. From Fig. 12, the metal intrusion area 1 1
- FIG. 13 shows a TEM image in Comparative Example 1.
- the symbols are displayed separately.
- a conductive layer 108 is formed on the second semiconductor layer 106, and an interface IF is formed at the boundary between the second semiconductor layer 106 and the conductive layer 108.
- Figure 14 shows a Ti mapping image by EDX in the same field of view as the TEM image of Figure 13. The higher the Ti density, the more white it is displayed. In Comparative Example 1, it can be seen that the metal intrusion region 112 as shown in FIG. 10 is not formed. This also strongly supports that the reduction in contact resistance is due to the formation of the metal intrusion region 112. Note that the penetration depth of Ti in Comparative Example 1 is observed to be 5 nm or less.
- Example 2 in Comparative Example 1, a region with a high Ti concentration is formed in the conductive layer 108.
- the region having a high Ti concentration is formed not in the conductive layer 108 but in the first semiconductor layer 104 and the second semiconductor layer 106. That is, in Example 2, more Ti exists in the first semiconductor layer 104 and the second semiconductor layer 106 than in the conductive layer 108. 14 and 10 are compared, the presence of the Au layer as the diffusion prevention layer 142 (diffusion prevention layer 1 32) suppresses the diffusion of Ti into the conductive layer 108, while the first Ti It can be seen that implantation into the semiconductor layer 104 and the second semiconductor layer 106 occurs.
- Figure 15 shows an EDX Ga mapping image in the same field of view as the TEM image in Figure 13.
- the higher the Ga concentration the more white the image is displayed.
- Figure 16 shows an A1 mapping image by EDX in the same field of view as the TEM image of Figure 13.
- FIG. 15 and FIG. 16 it can be seen that no elemental profile characteristic to the metal intrusion region 1 1 2 as shown in FIG. 1 1 and FIG. 1 2 is displayed.
- the metal distribution region 1 1 0 and the metal intrusion region 1 1 are formed in the contact portion with the semiconductor layer below the conductive layer 1 08. 2 is formed.
- the contact resistance of the contact portion is significantly reduced.
- This effect is obtained by forming a characteristic conductive region called the metal intrusion region 1 1 2 at the interface between the semiconductor and the conductive layer (electrode). By optimizing the heat treatment conditions, etc. Needless to say, it also includes the possibility of reducing contact resistance.
- FIG. 17 shows a light emitting device 300 as an example of the semiconductor device 100 of the present embodiment.
- the light emitting device 300 includes a first semiconductor layer 3 0 2, a second semiconductor layer 3 0 4, a third semiconductor layer 3 0 6, an electrode 3 0 8, a metal distribution region 3 1 0, and a metal intrusion region 3 1 2 Transparent electrode 3 1 4 and contact pad 3 1 6 are provided.
- the first semiconductor layer 30 2 may be an n-type semiconductor layer including N and Ga, for example, as the first conductivity type
- the second semiconductor layer 3 0 4 may be the first semiconductor layer 3 0 It may be, for example, an n-type semiconductor layer containing N and Ga that forms a heterojunction.
- the second semiconductor layer 30 4 generates radiated light due to carrier recombination.
- the third semiconductor layer 30 06 may be, for example, a p-type semiconductor layer that includes N and Ga and forms a second heterojunction with the second semiconductor layer 30 04, for example, as a second conductivity type.
- the electrode 3 0 8 is in ohmic connection with the first semiconductor layer 3 0 2.
- the metal distribution region 3 10 is present by distributing metal, for example, Ti, at the interface between the first semiconductor layer 30 2 and the electrode 3 08.
- the metal intrusion region 3 1 2 exists when a metal, for example, Ti enters the first semiconductor layer 3 0 2.
- the transparent electrode 3 1 4 is formed in contact with the third semiconductor layer 3 0 6, and the contact pad 3 1 6 is in contact with the transparent electrode 3 1 4.
- the light emitting device 30 0 causes recombination of carriers in the second semiconductor layer 30 4 by flowing a current between the electrode 3 0 8 and the transparent electrode 3 1 4, thereby emitting light.
- a metal distribution region 3 10 and a metal intrusion region 3 12 are formed between the electrode 3 0 8 and the first semiconductor layer 3 0 2. For this reason, the contact resistance of the ohmic contact can be reduced.
- consumption Reduction of electric power, reduction of heat generation, and improvement of luminous efficiency are required, and the effect of satisfying these requirements can be expected by reducing the contact resistance.
- an electrode similar to the electrode 3 0 8 can be configured.
- the electrode replacing the transparent electrode 3 14 may be in ohmic contact with the third semiconductor layer 30 6, and at the interface between the electrode replacing the transparent electrode 3 14 and the third semiconductor layer 3 06.
- a metal distribution region may be formed.
- Ti may enter the third semiconductor layer 3 06 to form a metal intrusion region.
- the metal intrusion region 3 1 2 may be formed to reach the interface of the first heterojunction or the second heterojunction.
- FIG. 18 shows a high carrier mobility transistor 400 as an example of the semiconductor device 100 according to this embodiment.
- the high carrier mobility transistor 400 includes a substrate 40 2, a buffer layer 4 0 4, a non-doped semiconductor layer 4 0 6 formed on an upper layer of the substrate 4 0 2 and containing N and Ga, and a non-doped semiconductor layer
- the band gap is larger than that of 40 6, and the doped semiconductor layer 4 0 8 is doped with an impurity that forms a heterojunction with the non-doped semiconductor layer 4 0 6, and the non-doped semiconductor layer 4 0 6 and the doped half
- Source electrode 4 1 2 that is in an ohmic connection with the drain electrode
- a drain electrode 4 1 8 that is in an ohmic connection
- the metal distribution region 4 1 4 and the metal intrusion region 4 1 6 are formed at the interface between the source electrode 4 1 2 and the doped semiconductor layer 4 0 8. It is formed.
- a metal distribution region 4 20 and a metal intrusion region 4 2 2 are formed at the interface between the drain electrode 4 1 8 and the doped semiconductor layer 4 0 8.
- the on-resistance between the source and drain can be reduced.
- the reduction of the on-resistance is particularly effective in ensuring high frequency operation.
- the metal intrusion region 4 16 and the metal intrusion region 4 2 2 may be formed to reach the channel region 4 10.
- the semiconductor device which reduces the contact resistance of the electrode ohmic-connected to a semiconductor layer, the manufacturing method of a semiconductor device, a high carrier mobility transistor, and a light-emitting device are provided.
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Abstract
Description
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US12/669,164 US20100207137A1 (en) | 2007-07-24 | 2008-07-17 | Semiconductor device, semiconductor device manufacturing method, high carrier mobility transistor and light emitting device |
CN200880025590.6A CN101779273B (zh) | 2007-07-24 | 2008-07-17 | 半导体器件,半导体器件制造方法,高载流子迁移率晶体管和发光器件 |
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US8563372B2 (en) * | 2010-02-11 | 2013-10-22 | Cree, Inc. | Methods of forming contact structures including alternating metal and silicon layers and related devices |
US8844793B2 (en) | 2010-11-05 | 2014-09-30 | Raytheon Company | Reducing formation of oxide on solder |
US9525054B2 (en) * | 2013-01-04 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | High electron mobility transistor and method of forming the same |
JP6658300B2 (ja) * | 2016-05-20 | 2020-03-04 | 株式会社デンソー | 有機トランジスタ |
IT201900019980A1 (it) * | 2019-10-29 | 2021-04-29 | St Microelectronics Srl | Metodo di fabbricazione di un terminale di porta di un dispositivo hemt, e dispositivo hemt |
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- 2008-07-17 KR KR1020107002446A patent/KR20100051647A/ko not_active Application Discontinuation
- 2008-07-17 CN CN200880025590.6A patent/CN101779273B/zh not_active Expired - Fee Related
- 2008-07-17 WO PCT/JP2008/063335 patent/WO2009014195A1/ja active Application Filing
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TW200913024A (en) | 2009-03-16 |
KR20100051647A (ko) | 2010-05-17 |
CN101779273A (zh) | 2010-07-14 |
US20100207137A1 (en) | 2010-08-19 |
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