WO2008126447A1 - 電子機器の配線構造及び電子機器パッケージの製造方法 - Google Patents

電子機器の配線構造及び電子機器パッケージの製造方法 Download PDF

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Publication number
WO2008126447A1
WO2008126447A1 PCT/JP2008/051181 JP2008051181W WO2008126447A1 WO 2008126447 A1 WO2008126447 A1 WO 2008126447A1 JP 2008051181 W JP2008051181 W JP 2008051181W WO 2008126447 A1 WO2008126447 A1 WO 2008126447A1
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WO
WIPO (PCT)
Prior art keywords
wiring
electronic apparatus
stage
printing
level difference
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PCT/JP2008/051181
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English (en)
French (fr)
Inventor
Yuuki Momokawa
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Nec Corporation
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Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/593,524 priority Critical patent/US8253250B2/en
Priority to JP2009508938A priority patent/JP5354380B2/ja
Publication of WO2008126447A1 publication Critical patent/WO2008126447A1/ja

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/245—Reinforcing conductive patterns made by printing techniques or by other techniques for applying conductive pastes, inks or powders; Reinforcing other conductive patterns by such techniques
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    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
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    • H01—ELECTRIC ELEMENTS
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

　スクリーン印刷によって段差のある対象に配線を形成する。下段と上段の２段を有する基材に対して印刷により配線が施される。その際、まず下段に配線パターンを印刷し乾燥する工程が繰り返されることにより、複数の層が重なった積層配線が形成される。そして積層配線の高さが上段の高さに近づいたとき、最上段の配線が積層配線の上に印刷される。この最上段の配線は、上段の表面にまで延設される。最上段の配線は段差が少ないため、印刷の特性が良い。こうした方法により、配線幅が狭く、しかも配線幅よりも大きな段差の上下を確実に接続する配線構造が印刷により形成される。
PCT/JP2008/051181 2007-03-30 2008-01-28 電子機器の配線構造及び電子機器パッケージの製造方法 WO2008126447A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/593,524 US8253250B2 (en) 2007-03-30 2008-01-28 Interconnection structure of electronic device having multilayer interconnections structure with electrically conductive layers
JP2009508938A JP5354380B2 (ja) 2007-03-30 2008-01-28 電子機器の配線構造及び電子機器パッケージの製造方法

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Application Number Priority Date Filing Date Title
JP2007-091490 2007-03-30
JP2007091490 2007-03-30

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Publication number Priority date Publication date Assignee Title
US9496171B2 (en) * 2014-09-26 2016-11-15 Texas Instruments Incorporated Printed interconnects for semiconductor packages

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JPH0613490A (ja) * 1992-03-26 1994-01-21 Sumitomo Electric Ind Ltd 半導体装置
JP2004247668A (ja) * 2003-02-17 2004-09-02 Hitachi Chem Co Ltd 積層用中間配線部材、配線板及びそれらの製造方法
JP2006019441A (ja) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd 電子部品内蔵基板の製造方法

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JP4738895B2 (ja) * 2005-05-31 2011-08-03 日本メクトロン株式会社 ビルドアップ型多層フレキシブル回路基板の製造方法
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JP4849926B2 (ja) * 2006-03-27 2012-01-11 富士通株式会社 半導体装置及び半導体装置の製造方法

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Publication number Priority date Publication date Assignee Title
JPH0613490A (ja) * 1992-03-26 1994-01-21 Sumitomo Electric Ind Ltd 半導体装置
JP2004247668A (ja) * 2003-02-17 2004-09-02 Hitachi Chem Co Ltd 積層用中間配線部材、配線板及びそれらの製造方法
JP2006019441A (ja) * 2004-06-30 2006-01-19 Shinko Electric Ind Co Ltd 電子部品内蔵基板の製造方法

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JP5354380B2 (ja) 2013-11-27
JPWO2008126447A1 (ja) 2010-07-22
US20100117239A1 (en) 2010-05-13
US8253250B2 (en) 2012-08-28

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