Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
  • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
  • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
  • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
  • H05K3/341—Surface mounted components
  • H05K3/3431—Leadless components
  • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
• • H—ELECTRICITY
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
• • H—ELECTRICITY
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  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/0198—Manufacture or treatment batch processes
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/03—Conductive materials
  • H05K2201/0332—Structure of the conductor
  • H05K2201/0364—Conductor shape
  • H05K2201/0379—Stacked conductors
• • H—ELECTRICITY
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09372—Pads and lands
  • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10234—Metallic balls
• • H—ELECTRICITY
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10227—Other objects, e.g. metallic pieces
  • H05K2201/10242—Metallic cylinders
• • H—ELECTRICITY
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  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
  • H05K2201/10954—Other details of electrical connections
  • H05K2201/10977—Encapsulated connections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
  • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
  • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
  • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01215—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps forming coatings
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
  • H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
  • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01251—Changing the shapes of bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/013—Manufacture or treatment of die-attach connectors
  • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07231—Techniques
  • H10W72/07234—Using a reflow oven
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07231—Techniques
  • H10W72/07236—Soldering or alloying
• • H—ELECTRICITY
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
  • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
  • H10W72/07255—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in materials
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/221—Structures or relative sizes
  • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
• • H—ELECTRICITY
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/221—Structures or relative sizes
  • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
  • H10W72/223—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core characterised by the structure of the outermost layers, e.g. multilayered coatings
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/231—Shapes
  • H10W72/237—Multiple bump connectors having different shapes
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
• • H—ELECTRICITY
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/255—Materials of outermost layers of multilayered bumps, e.g. material of a coating
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  • H10W72/00—Interconnections or connectors in packages
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  • H10W72/251—Materials
  • H10W72/257—Multiple bump connectors having different materials
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/321—Structures or relative sizes of die-attach connectors
  • H10W72/322—Multilayered die-attach connectors, e.g. a coating on a top surface of a core
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  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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  • H10W72/30—Die-attach connectors
  • H10W72/321—Structures or relative sizes of die-attach connectors
  • H10W72/325—Die-attach connectors having a filler embedded in a matrix
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  • H10W72/351—Materials of die-attach connectors
  • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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  • H10W72/351—Materials of die-attach connectors
  • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
  • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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  • H10W72/00—Interconnections or connectors in packages
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  • H10W72/853—On the same surface
  • H10W72/856—Bump connectors and die-attach connectors
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  • H10W72/941—Dispositions of bond pads
  • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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  • H10W72/941—Dispositions of bond pads
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  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base
  • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

• the present invention relates to an electrical interconnect structure and associated method for forming an electrical interconnect structure.
• the present invention provides an electrical structure comprising: a first substrate comprising a first electrically conductive pad; a second substrate comprising a second electrically conductive pad; and an interconnect structure electrically and mechanically connecting said first electrically conductive pad to said second electrically conductive pad, wherein said interconnect structure comprises a non- solder metallic core structure, a first solder structure in direct mechanical contact with a first portion of said non- solder metallic core structure, and a second solder structure in direct mechanical contact with a second portion of said non- solder metallic core structure, wherein said first solder structure electrically and mechanically connects said first portion of said non- solder metallic core structure to said first electrically conductive pad, and wherein said second solder structure electrically and mechanically connects said second portion of said non- solder metallic core structure to said second electrically conductive pad.
• the present invention provides an electrical structure comprising: a first substrate comprising a first electrically conductive pad; a second substrate comprising a second electrically conductive pad; and an interconnect structure electrically and mechanically connecting said first electrically conductive pad to said second electrically conductive pad, wherein said interconnect structure comprises a non- solder metallic core structure and a layer of solder covering an entire exterior surface of said non- solder metallic core structure, wherein said entire exterior surface completely surrounds said first metallic structure, wherein said layer of solder is in direct electrical and mechanical contact with said entire surface of said non- solder metallic core structure, and wherein said layer of solder electrically and mechanically connects said non-solder metallic core structure to said first electrically conductive pad and said second electrically conductive pad.
• the present invention provides a method for forming an electrical structure comprising: providing a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, and a transfer film comprising a non-solder metallic core structure, wherein said non-solder metallic core structure comprises a cylindrical shape; forming a first solder structure on said first electrically conductive pad; first positioning after said forming said first solder structure, said transfer film such that a first side of said non-solder metallic core structure is in contact with said first solder structure; first heating after said first positioning, said non- solder metallic core structure to a temperature sufficient to cause said first solder structure to melt and form an electrical and mechanical connection between said first side of said non- solder metallic core structure and said first electrically conductive pad; removing after said first heating, said transfer film from said non- solder metallic core structure; forming a second solder structure on said second electrically conductive pad; second positioning, after said forming said second solder structure, said first substrate comprising said non- sold
• the present invention provides a method for forming an electrical structure comprising: providing a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, a first transfer substrate comprising a first cavity, and a non- solder metallic core structure comprising a spherical shape, wherein said non- solder metallic core structure comprises a diameter that is less than a diameter of said first cavity; forming a first solder structure on said first electrically conductive pad; dispensing said non- solder metallic core structure into said first cavity within said first transfer substrate; first positioning after said dispensing, said first transfer substrate such that a first section of a surface of said non-solder metallic core structure is in contact with said first solder structure; first heating after said first positioning, said non- solder metallic core structure to a temperature sufficient to cause said first solder structure to melt and form an electrical and mechanical connection between said first section of said surface of said non- solder metallic core structure and said first electrically conductive pad; removing after said first heating, said
• the present invention provides a method for forming an electrical structure comprising: providing a first substrate comprising a first electrically conductive pad, a second substrate comprising a second electrically conductive pad, a first transfer substrate comprising a first cavity, a first non-solder metallic core structure comprising a spherical shape, and a second non-solder metallic core structure comprising a spherical shape, wherein said first non-solder metallic core structure comprises a diameter that is less than a diameter of said first cavity, and wherein said second non-solder metallic core structure comprises a diameter that is less than a diameter of said first cavity; forming a first solder structure on said first electrically conductive pad; first dispensing said first non- solder metallic core structure into said first cavity within said first transfer substrate; first positioning after said first dispensing, said first transfer substrate such that a first section of a surface of said first non-solder metallic core structure is in contact with said first solder structure; first heating after said first positioning, said first non-solder metallic
• the present invention provides a method for forming an electrical structure comprising: providing a first substrate comprising a first electrically conductive pad and a second electrically conductive pad, a second substrate comprising third electrically conductive pad and a fourth electrically conductive pad, a first transfer substrate comprising a first cavity and a second cavity, and a non- solder metallic core structure comprising a spherical shape, wherein said non- solder metallic core structure comprises a diameter that is less than a diameter of said first cavity; forming a first solder structure on said first electrically conductive pad; forming a second solder structure on said second electrically conductive pad; covering said second cavity with a film having an opening corresponding to said first cavity; dispensing said non-solder metallic core structure into said first cavity within said first transfer substrate; first positioning said first transfer substrate such that a first section of a surface of said non- solder metallic core structure is in contact with said first solder structure and said second cavity is aligned with said second solder structure; first heating said non-
• FIG. 1 illustrates a cross sectional view of a first electrical structure, in accordance with embodiments of the present invention
• FIG. 2 depicts a first alternative to FIG. 1 illustrating a cross sectional view of a second electrical structure, in accordance with embodiments of the present invention.
• FIG. 3 depicts a first alternative to FIG. 2 illustrating a cross sectional view of a third electrical structure, in accordance with embodiments of the present invention.
• FIG. 4 depicts a first alternative to FIG. 3 illustrating a cross sectional view of a fourth electrical structure, in accordance with embodiments of the present invention.
• FIG. 5 illustrates a cross sectional view of a fifth electrical structure, in accordance with embodiments of the present invention.
• FIG. 6 depicts a second alternative to FIG. 2 illustrating a cross sectional view of a sixth electrical structure, in accordance with embodiments of the present invention.
• FIG. 7 depicts a second alternative to FIG. 1 illustrating a cross sectional view of an seventh electrical structure, in accordance with embodiments of the present invention.
• FIG. 8 depicts a second alternative to FIG. 3 illustrating a cross sectional view of a eighth electrical structure, in accordance with embodiments of the present invention.
• FIGS. 9A-9G illustrate a process for generating the electrical structure of FIG. 1, in accordance with embodiments of the present invention.
• FIGS. 10A-10I illustrate a process for generating the electrical structures of FIG. 2, FIG. 3, and FIG. 5, in accordance with embodiments of the present invention.
• FIGS. 1 IA-I IF illustrate a process for generating the electrical structure of FIG. 4, in accordance with embodiments of the present invention.
• FIG. 1 illustrates a cross sectional view of an electrical structure 2a, in accordance with embodiments of the present invention.
• Electrical structure 2a comprises a substrate 1, a substrate 4, and a plurality of interconnect structures 5a.
• Substrate 1 comprises a plurality of electrically conductive pads 10. Each pad of electrically conductive pads 10 may be connected to wires or electrical components within substrate 1.
• Substrate 4 comprises a plurality of electrically conductive pads 12. Each pad of electrically conductive pads 12 may be connected to wires or electrical components within substrate 4.
• Substrate 1 may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc.
• Substrate 4 may comprise, inter alia, a semiconductor device (e.g., an integrated circuit chip, a semiconductor wafer, etc), a chip carrier (organic or inorganic), a printed circuit board, etc.
• Each interconnect structure 5a comprises a non-solder metallic (i.e., does not comprise any solder material) core structure 14 and a solder structure 6a.
• Solder structure 6a comprises solder.
• Solder is defined herein as a metal alloy comprising a low melting point (i.e., about 100 degrees Celsius to about 340 degrees Celsius) that is used to join metallic surfaces together without melting the metallic surfaces.
• Solder structure 6a comprises a layer of solder that completely surrounds non-solder metallic core structure 14.
• solder structure 6a could comprise a first portion of solder 9a attached to a top side 14a of non- solder metallic core structure 14 and a second portion of solder 9b attached to a bottom side 14b of non-solder metallic core structure 14.
• Each non-solder metallic core structure 14 may comprise any conductive metallic material that does not comprise solder including, inter alia, copper, gold, nickel, etc.
• Each interconnect structure 5a electrically and mechanically connects an electrically conductive pad 10 to an electrically conductive pad 12.
• Non-solder metallic core structure 14 comprises a cylindrical shape.
• Solder structure 6a may comprise any solder material suitable for flip chip interconnections including, inter alia, an alloy of tin such as SnCu, SnAgCu, SnPb, etc.
• FIG. 2 depicts a first alternative to FIG. 1 illustrating a cross-sectional view of an electrical structure 2b, in accordance with embodiments of the present invention.
• Electrical structure 2b comprises substrate 1, substrate 4, and a plurality of interconnect structures 5b.
• electrical structure 2b of FIG. 2 comprises a plurality of interconnect structures 5b.
• Each of interconnect structures 5b comprises a spherical non-solder (i.e., does not comprise any solder material) metallic core structure 17 and a solder structure 6b.
• Each solder structure 6b comprises a layer of solder that completely surrounds an associated non-solder metallic core structure 17.
• each of interconnect structures 5b may comprise an additional solder structure 6d.
• Each solder structure 6b electrically and mechanically connects the associated non- solder metallic core structure 17 to an associated electrically conductive pad 10.
• Each solder structure 6d electrically and mechanically connects the associated non- solder metallic core structure 17 (i.e., thru solder structure 6b) to an associated electrically conductive pad 12.
• the aforementioned connections result in each interconnect structure 5b electrically and mechanically connecting an electrically conductive pad 10 to an associated electrically conductive pad 12.
• two different types of solder materials may be used for solder structure 6b and solder structure 6d.
• solder structure 6b may comprise an AuSn solder material and solder structure 6d may comprise a solder material such as, inter alia, SnAg, SnCu, SnAgCu, SnBi, etc.
• each non- solder metallic core structure 17 may comprise a diameter of about 25 microns to about 150 microns.
• second level area array interconnects e.g., a ball grid array (BGA)
• each non-solder metallic core structure 17 may comprise a diameter of about 0.2 mm to about 1.5 mm.
• Each non- solder metallic core structure 17 may comprise a core of any conductive metallic material that does not comprise solder including, inter alia, copper, gold, nickel, etc.
• each non- solder metallic core structure 17 may comprise an additional layer(s) of non-solder metallic materials (i.e., different from a material comprised by non-solder metallic core structure 17) surrounding (e.g., see layer 19 in FIG. 3, infra) non-solder metallic core structure 17.
• the additional layer(s) may comprise any conductive metallic material including, inter alia, nickel, gold, tin, etc.
• FIG. 3 depicts a first alternative to FIG. 2 illustrating a cross sectional view of an electrical structure 2c, in accordance with embodiments of the present invention.
• Electrical structure 2c comprises substrate 1, substrate 4, and a plurality of interconnect structures 5c.
• electrical structure 2c of FIG. 3 comprises a plurality of interconnect structures 5c.
• Each of interconnect structures 5c comprises a non- solder metallic core structure 17, a solder structure 6c, and a solder structure 6d.
• Each solder structure 6c electrically and mechanically connects an associated non-solder metallic core structure 17 to an associated electrically conductive pad 10.
• Each solder structure 6d electrically and mechanically connects an associated non- solder metallic core structure 17 to an associated electrically conductive pad 12.
• solder structure 6c may comprise an AuSn solder material and solder structure 6d may comprise a solder material such as, inter alia, SnAg, SnCu, SnAgCu, SnBi, etc.
• solder structure 6d may comprise a solder material such as, inter alia, SnAg, SnCu, SnAgCu, SnBi, etc.
• Each non- solder metallic core structure 17 may comprise a core of any conductive metallic material that does not comprise solder including, inter alia, copper, gold, nickel, etc.
• each non-solder metallic core structure 17 may comprise an additional layer(s) 19 of non- solder metallic materials (i.e., different from a material comprised by non-solder metallic core structure 17) surrounding non-solder metallic core structure 17.
• Additional layer(s) 19 may comprise any conductive metallic material including, inter alia, nickel, gold, tin, etc.
• FIG. 4 depicts a first alternative to FIG. 3 illustrating a cross sectional view of an electrical structure 2d, in accordance with embodiments of the present invention.
• Electrical structure 2d comprises substrate 1, substrate 4, and a plurality of interconnect structures 5d.
• electrical structure 2d of FIG. 4 comprises a plurality of interconnect structures 5d.
• Each of interconnect structures 5d comprises a non- solder metallic core structure 17a, a non-solder metallic core structure 17b, a solder structure 6c, a solder structure 6d, a solder structure 6e.
• electrical structure 2d comprises an underfill encapsulant layer 25 a and an underfill encapsulant layer 25b.
• Each solder structure 6e electrically and mechanically connects a non- solder metallic core structure 17a to an associated a non-solder metallic core structure 17b.
• Each solder structure 6c electrically and mechanically connects a non-solder metallic core structure 17a to an associated electrically conductive pad 10.
• Each solder structure 6d electrically and mechanically connects a non-solder metallic core structure 17b to an associated electrically conductive pad 12.
• the aforementioned connections result in each interconnect structure 5d electrically and mechanically connecting an electrically conductive pad 10 to an associated electrically conductive pad 12.
• three different types of solder materials may be used for solder structure 6c, solder structure 6d, and solder structure 6e.
• solder structure 6c may comprise an AuSn solder material
• solder structure 6d may comprise a solder material such as, inter alia, SnAg, SnCu, etc
• solder structure 6e may comprise a solder material such as, inter alia, SnAgCu, SnBi, etc.
• Each non-solder metallic core structure 17a and 17b may comprise a core of any conductive metallic material that does not comprise solder including, inter alia, copper, gold, nickel, etc.
• Non-solder metallic core structure 17a may comprise a first material (e.g., copper) and non-solder metallic core structure 17b may comprise a second material (e.g., gold).
• each non-solder metallic core structure 17a and 17b may comprise an additional layer(s) 19 of metallic materials (i.e., different from a material comprised by non-solder metallic core structure 17a and 17b) surrounding non-solder metallic core structure 17a and 17b.
• Additional layer(s) 19 may comprise any conductive metallic material including, inter alia, nickel, gold, tin, etc.
• non- solder metallic core structure 17a may comprise a layer(s) 19 comprising a different material from a layer(s) 19 on non-solder metallic core structure 17b.
• Underfill encapsulant layer 25a surrounds non- solder metallic core structures 17a and is in contact with substrate 1.
• Underfill encapsulant layer 25b surrounds non-solder metallic core structures 17b and is in contact with substrate 4.
• Underfill encapsulant layer 25 a is in contact with underfill encapsulant layer 25b.
• Underfill encapsulant layer 25a may comprise a first material (e.g., a highly filled silica-epoxy composite adhesive) and underfill encapsulant layer 25b may comprise a second and different material (e.g., a lightly filled silica-epoxy composite adhesive).
• Underfill encapsulant layer 25a may comprise a first coefficient of thermal expansion (e.g., comprising a range of about 5-15 ppm/C) that is different (e.g., lower) from a second coefficient of thermal expansion (e.g., comprising a range of about 15.1-40 ppm/C) comprised by encapsulant layer 25b.
• Underfill encapsulent layer 25a may additionally comprise a filler 25c dispersed throughout.
• FIG. 5 illustrates a cross sectional view of an electrical structure 2e, in accordance with embodiments of the present invention.
• Electrical structure 2e in FIG. 5 is a combination of electrical structures 2b and 2c, of FIGS. 2-3.
• electrical structure 2e in FIG. 5 comprises interconnection structures 29 (i.e., comprising solder) electrically and mechanically connecting some of electrically conductive pads 10 to associated electrically conductive pads
• electrical structure 2e uses a combination of interconnect structures 5b, 5c, and 29 to electrically and mechanically connect electrically conductive pads 10 to associated electrically conductive pads 12.
• interconnect structures 5b, 5 c, and 29 may be used to electrically and mechanically connect electrically conductive pads 10 to associated electrically conductive pads 12.
• electrical structure 2e may comprise only interconnect structures 5 c and 29 to electrically and mechanically connect electrically conductive pads 10 to associated electrically conductive pads 12.
• interconnect structures 5b, 5c, and 29 may be any number or ratio of interconnect structures 5b, 5c, and 29 arranged in any pattern (e.g., interconnect structures 5b and 29: may be placed such that they are in alternating positions, may be placed in random positions, may be placed such that there is one interconnect structure 5b for every three interconnect structures 29, may be placed such that interconnect structures 5b provide power and ground connections only and interconnect structures 29 are placed for signal interconnects only, etc).
• electrical structure 2e may comprise an underfill encapsulant layer 31 between substrate 1 and substrate 4.
• FIG. 6 depicts a second alternative to FIG. 2 illustrating a cross sectional view of an electrical structure 2f, in accordance with embodiments of the present invention.
• electrical structure 2f of FIG. 6 comprises an underfill encapsulant layer 32a between substrate 1 and substrate 4.
• underfill encapsulant layer 32a may alternately comprise an underfill layer applied prior to chip joining or applied on the silicon wafer over the interconnect structures 5b.
• Such an underfill layer is defined as a wafer-level underfill.
• FIG. 7 depicts a second alternative to FIG. 1 illustrating a cross sectional view of an electrical structure 2g, in accordance with embodiments of the present invention.
• electrical structure 2g of FIG. 7 comprises an underfill encapsulant layer 32b between substrate 1 and substrate 4.
• underfill encapsulant layer 32b may alternately comprise an underfill layer applied prior to chip joining or applied on the silicon wafer over the interconnect structures 5a.
• Such an underfill layer is defined as a wafer-level underfill
• FIG. 8 depicts a second alternative to FIG. 3 illustrating a cross sectional view of an electrical structure 2h, in accordance with embodiments of the present invention.
• electrical structure 2h of FIG. 8 comprises an underfill encapsulant layer 32c between substrate 1 and substrate 4.
• underfill encapsulant layer 32c may alternately comprise an underfill layer applied prior to chip joining or applied on the silicon wafer over the interconnect structures 5c.
• Such an underfill layer is defined as a wafer- level underfill.
• FIGS. 9A-9G illustrate a process for generating electrical structure 2a of FIG. 1, in accordance with embodiments of the present invention.
• FIG. 9A illustrates a cross sectional view of a non-solder metallic layer 37 formed over an insulator layer 35, in accordance with embodiments of the present invention.
• Non- solder metallic layer 37 may comprise any non-solder metallic material such as, inter alia, copper, gold, nickel, etc.
• Insulator layer 35 may comprise any insulator material such as, inter alia, a polymer film (e.g., polyimide), etc.
• FIG. 9B illustrates a cross sectional view of the structure of FIG. 9A after non-solder metallic interconnect structures 14 have been formed in order to form structure 35 a, in accordance with embodiments of the present invention.
• Non-solder metallic interconnect structures 14 may be formed by subtractively etching portions of non- solder metallic layer 37 (i.e., of FIG. 1) in order to form non-solder metallic interconnect structures 14.
• Non- solder metallic interconnect structures 14 may comprise various widths, heights, and height- to-width aspect ratios.
• a subtractive etching process comprises:
• Each of non- solder metallic interconnect structures 14 may comprise a width of about 10 microns to about 100 microns and comprise a height-to -width aspect ratio of about 1 :1 to about 5:1.
• FIG. 9C illustrates a cross sectional view of substrate 1 of FIG. 1 after first portions of solder 9a (i.e., solder structures) have been formed thereby forming a structure 35b, in accordance with embodiments of the present invention.
• substrate 1 may comprise a silicon device wafer that is prepared with electrically conductive interconnect pads (e.g., see pads 10 of FIG. 1). Solder is applied to the pads in order to form first portions of solder 9a. Any method may be used to apply the solder to the electrically conductive interconnect pads, including, inter alia, applying solder as an injection molded solder.
• FIG. 9D illustrates a cross sectional view of structure 35a of FIG. 9B of FIG. 1 aligned with structure 35b of FIG. 9C, in accordance with embodiments of the present invention.
• Non-solder metallic interconnect structures 14 are aligned to associated first portions of solder 9a.
• the alignment process may comprise using commercially available bonding tools that use optical sensing of fiducials on substrate 1 and insulator layer 35.
• FIG. 9E illustrates a cross sectional view of structure 35c formed after the alignment process described with respect to FIG. 9D, in accordance with embodiments of the present invention.
• a transfer process has been performed by heating the aligned assembly of FIG. 9D to a temperature above a melting point (i.e., with assistance of a fluxing agent or a fluxing atmosphere) of the solder used to form first portions of solder 9a.
• the transfer process may be assisted by a laser release process applied through a backside 21 of insulator layer 35.
• Non-solder metallic interconnect structures 14 Light energy generated by a laser is absorbed by insulator layer 35 at an interface 23 to non-solder metallic interconnect structures 14 causes adhesion (i.e., at interface 23) to be degraded hereby releasing non-solder metallic interconnect structures 14 from insulator layer 35.
• an adhesive i.e., at interface 23
• FIG. 9F illustrates a cross sectional view of a process for aligning structure 35c of FIG. 9E with a structure 35d, in accordance with embodiments of the present invention.
• Structure 35d comprises a substrate 4 comprising formed solder structures 9b (i.e., formed by a similar process to the process performed with respect to FIG. 9C).
• FIGS. 9G illustrates a completed electrical structure 35e similar to electrical structure 2a of FIG. 1, in accordance with embodiments of the present invention.
• non-solder metallic interconnect structures 14, solder structures 9a, and solder structures 9b An assembly of substrate 1 to substrate 4 through non-solder metallic interconnect structures 14, solder structures 9a, and solder structures 9b is carried out by raising a temperature of non-solder metallic interconnect structures 14 above a melting temperature of solder structures 9b with the assistance of a fluxing agent or fluxing atmosphere.
• non-solder metallic interconnect structures 14, solder structures 9a, and solder structures 9b may be encapsulated with polymeric material by capillary underfill following the joining of substrate 1 to substrate 4.
• an underfill encapsulant may be applied at wafer-level or on singulated devices prior to the joining of substrate 1 to substrate 4.
• FIGS. 10A- 101 illustrate a process for generating electrical structure 2b of FIG. 2, electrical structure 2c of FIG. 3, and electrical structure 2e of FIG. 5, in accordance with embodiments of the present invention. Note that although FIGS. 10A- 101 illustrate a process for applying solder as an injection molded solder, any solder applying process may be used.
• FIG. 1OA illustrates a cross sectional view of a structure 39a comprising a filled glass or silicon mold 40 positioned over substrate 1 (i.e., from FIGS. 2 and 3), in accordance with embodiments of the present invention.
• Glass or silicon mold 40 is filled with solder that when released from glass mold will become solder structures 6b of FIG. 2, 6c of FIG. 3, and
• the solder may comprise any solder suitable for flip chip interconnects including, inter alia, an alloy of tin such as, inter alia, AuSn, SnCu, SnAgCu, etc.
• the solder may comprise a high melting point so that solder structures 6b, 6c will not melt during a subsequent step.
• FIG. 1OB illustrates a cross sectional view of a structure of 39b formed from structure 39a of FIG. 1OA, in accordance with embodiments of the present invention.
• the solder has been released from glass or silicon mold 40 to form solder structures 6c attached to electrically conductive pads 10 on substrate 1.
• FIG. 1OC illustrates a cross sectional view of a transfer substrate 43 comprising a plurality of non-solder metallic core structures 17, in accordance with embodiments of the present invention.
• Non-solder metallic core structures 17 are positioned in cavities 43 a within transfer substrate 43.
• Each of cavities 43 a comprises similar dimensions as non- solder metallic core structures 17 with cavity positions corresponding to positions of associated solder structures 6c on electrically conductive pads 10.
• Transfer substrate 43 may comprise, inter alia, glass, silicon, or any material used for injection molded solder molds, etc.
• Non-solder metallic core structures 17 may be dispensed into cavities 43a as a slurry in a solvent such as, inter alia, water alcohol (e.g., isopropanol), etc.
• the solvent may comprise an appropriate amount of flux to assist in the wetting of solder structures 6c to non- solder metallic core structures 17. In a case in which non- solder metallic core structures 17are coated with gold, flux is not necessary.
• the solvent may additionally comprise a small amount of thermally degradable polymeric adhesive to aid in retaining non- solder metallic core structures 17in cavities 43 a. Cavities 43 a are fabricated to a size that will only cause one non- solder metallic core structure 17 to fall into it during a dispensing of non- solder metallic core structures 17.
• FIG. 1OD illustrates a cross sectional view of transfer substrate 43 of FIG. 1OC comprising a selected plurality of non- solder metallic core structures 17, in accordance with embodiments of the present invention.
• transfer substrate 43 may be covered with a polymeric film (i.e., not shown) with through-holes matching some pre-determined fraction of cavities 43 a.
• the pre-determined fraction of cavities 43a covered by the polymeric film will be prevented from receiving non- solder metallic core structures 17.
• the pre-determined fraction of cavities 43a allows a packaging design engineer to selectively place non-solder metallic core structures 17.
• solder interconnects 29 may be selectively placed in some of cavities 43a (i.e., instead of select non-solder metallic core structures 17) for placement on substrate 1.
• transfer substrate 43 may be couvered with a second polymeric film (i.e., not shown) with through-holes matching the remaining cavities 43 a.
• the cavities 43 a covered by the polymeric film will be prevented from receiving solder interconnects 29.
• FIG. 1OE illustrates a cross sectional view of substrate 1 of FIG. 1OB positioned over transfer substrate 43 comprising non-solder metallic core structures 17, in accordance with embodiments of the present invention.
• Substrate 1 of FIG. 1OB is positioned over transfer substrate 43 comprising non- solder metallic core structures 17 in order to transfer non- solder metallic core structures 17 to substrate 1.
• FIG. 1OF illustrates a cross sectional view of substrate 1 after non-solder metallic core structures 17 have been released from transfer substrate 43 and connected to solder structures 6b, in accordance with embodiments of the present invention.
• solder structures 6b completely surround non- solder metallic core structures 17.
• FIG. 1OG depicts an alternative to FIG. 1OF illustrating a cross sectional view of a structure 39c comprising substrate 1 after non- solder metallic core structures 17 have been released from transfer substrate 43 and connected to solder structures 6c, in accordance with embodiments of the present invention.
• solder structures 6c partially surround non- solder metallic core structures 17.
• FIG. 1OH illustrates a cross sectional view of substrate 1 positioned over substrate 4, in accordance with embodiments of the present invention.
• Substrate 1 is connected to substrate 4 in order to form electrical structure 2b of FIG. 2.
• FIG. 101 illustrates an alternative cross sectional view of substrate 1 positioned over substrate 4, in accordance with embodiments of the present invention.
• the option of FIG. 1OD is used (i.e., comprising solder interconnect structures 29)
• the positioning is done similarly as in FIG 101.
• Substrate 1 is connected to substrate 4 in order to form electrical structure 2c of FIG. 3.
• FIGS. 1 IA-I IF illustrate a process for generating electrical structure 2d of FIG. 4, in accordance with embodiments of the present invention.
• FIG. 1 IA illustrates structure 39c of FIG. 1OG comprising an underfill layer 25a, in accordance with embodiments of the present invention.
• Structure 39c in FIG. 1 IA has been formed by the process steps described with reference to FIGS. 10A- 1OE.
• Underfill layer 25a may comprise a filler 25c to create a low coefficient of thermal expansion (CTE).
• Underfill layer 25a may comprise a coefficient of thermal expansion (CTE) similar to that of substrate 1.
• FIG. 1 IB illustrates structure 39c comprising a glass or silicon mold 40b positioned over non-solder metallic core structures 17a, in accordance with embodiments of the present invention.
• Glass or silicon mold 40b is filled with solder that when released from mold 40b will become solder structures 6e of FIG. 4.
• the solder may comprise any solder suitable for flip chip interconnects including, inter alia, an alloy of tin such as, inter alia, AuSn, SnCu, SnAgCu, etc.
• the solder may comprise a high melting point so that solder structures 6e will not melt during a subsequent step.
• FIG. 11C illustrates a cross sectional view of structure of 39c comprising solder structures 6e attached to non-solder metallic core structures 17a, in accordance with embodiments of the present invention.
• the solder has been released from glass or silicon mold 40b to form solder structures 6e attached to non-solder metallic core structures 17a.
• FIG. 1 ID illustrates a cross sectional view of structure 39c of FIG. 11C positioned over a transfer substrate 43 comprising non- solder metallic core structures 17b, in accordance with embodiments of the present invention.
• Structure 39c of FIG. 11C is positioned over transfer substrate 43 comprising non-solder metallic core structures 17b in order to transfer and connect non-solder metallic core structures 17b to non-solder metallic core structures 17a.
• FIG. 1 IE illustrates a cross sectional view of structure 39c of FIG. 1 ID after non- solder metallic core structures 17b have been connected to non-solder metallic core structures 17a, in accordance with embodiments of the present invention.
• FIG. 1 IF illustrates a cross sectional view of structure 39c of FIG. 1 IE comprising an underfill layer 25b applied over underfill layer 25 a, in accordance with embodiments of the present invention.
• substrate 1 is connected to substrate 4 in order to form electrical structure 2d of FIG. 4.

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• 2007
  • 2007-04-11 US US11/733,840 patent/US7786001B2/en not_active Expired - Fee Related
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