WO2008084525A1 - バラツキ補正方法、ｐｌｌ回路及び半導体集積回路 - Google Patents

バラツキ補正方法、ｐｌｌ回路及び半導体集積回路 Download PDF

Info

Publication number
WO2008084525A1
WO2008084525A1 PCT/JP2007/050097 JP2007050097W WO2008084525A1 WO 2008084525 A1 WO2008084525 A1 WO 2008084525A1 JP 2007050097 W JP2007050097 W JP 2007050097W WO 2008084525 A1 WO2008084525 A1 WO 2008084525A1
Authority
WO
WIPO (PCT)
Prior art keywords
controlled oscillator
voltage controlled
low
semiconductor integrated
correcting variation
Prior art date
Application number
PCT/JP2007/050097
Other languages
English (en)
French (fr)
Inventor
Toshihiko Mori
Masafumi Kondo
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to EP07706444.2A priority Critical patent/EP2120344B1/en
Priority to PCT/JP2007/050097 priority patent/WO2008084525A1/ja
Priority to KR1020097014329A priority patent/KR101065818B1/ko
Priority to JP2008552969A priority patent/JP4593669B2/ja
Publication of WO2008084525A1 publication Critical patent/WO2008084525A1/ja
Priority to US12/499,849 priority patent/US7872536B2/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/04—Modifications for maintaining constant the phase-locked loop damping factor when other loop parameters change
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

　位相周波数検出部、チャージポンプ、ローパスフィルタ、電圧制御発振器が直列接続され、電圧制御発振器の出力クロックが分周器を介して入力クロックが入力される位相周波数検出部にフィードバックされる構成のＰＬＬ回路の特性のバラツキを補正するバラツキ補正方法では、ローパスフィルタ内の抵抗値に応じた基準電流を生成し、基準電流が電圧制御発振器に出力され、ローパスフィルタの特性と電圧制御発振器の利得とが、電圧制御発振器の出力クロックに基づいて補正される。
PCT/JP2007/050097 2007-01-09 2007-01-09 バラツキ補正方法、ｐｌｌ回路及び半導体集積回路 WO2008084525A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP07706444.2A EP2120344B1 (en) 2007-01-09 2007-01-09 Method for correcting variation, pll circuit and semiconductor integrated circuit
PCT/JP2007/050097 WO2008084525A1 (ja) 2007-01-09 2007-01-09 バラツキ補正方法、ｐｌｌ回路及び半導体集積回路
KR1020097014329A KR101065818B1 (ko) 2007-01-09 2007-01-09 변동 보정 방법, ｐｌｌ 회로 및 반도체 집적 회로
JP2008552969A JP4593669B2 (ja) 2007-01-09 2007-01-09 バラツキ補正方法、ｐｌｌ回路及び半導体集積回路
US12/499,849 US7872536B2 (en) 2007-01-09 2009-07-09 Variance correction method, PLL circuit and semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/050097 WO2008084525A1 (ja) 2007-01-09 2007-01-09 バラツキ補正方法、ｐｌｌ回路及び半導体集積回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/499,849 Continuation US7872536B2 (en) 2007-01-09 2009-07-09 Variance correction method, PLL circuit and semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
WO2008084525A1 true WO2008084525A1 (ja) 2008-07-17

Family

ID=39608430

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/050097 WO2008084525A1 (ja) 2007-01-09 2007-01-09 バラツキ補正方法、ｐｌｌ回路及び半導体集積回路

Country Status (5)

Country Link
US (1) US7872536B2 (ja)
EP (1) EP2120344B1 (ja)
JP (1) JP4593669B2 (ja)
KR (1) KR101065818B1 (ja)
WO (1) WO2008084525A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101572545A (zh) * 2009-06-12 2009-11-04 上海集成电路研发中心有限公司 锁相环电路及其控制方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011001497A1 (ja) * 2009-06-29 2011-01-06 富士通株式会社 発振回路および電流補正方法
DE102017130390A1 (de) * 2017-12-18 2019-06-19 Infineon Technologies Ag Testen von Eigenschaften eines spannungsgesteuerten Oszillators
TWI668965B (zh) * 2018-06-05 2019-08-11 円星科技股份有限公司 時脈產生電路及時脈產生方法
JP2022144311A (ja) 2021-03-18 2022-10-03 キオクシア株式会社 受信装置、受信装置の制御方法及びメモリコントローラ
KR20220130504A (ko) 2021-03-18 2022-09-27 에스케이하이닉스 주식회사 비휘발성 메모리 장치의 데이터 입출력 속도를 개선하기 위한 장치 및 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001016102A (ja) * 1999-06-29 2001-01-19 Nec Corp Ｐｌｌ回路方式
JP2003078410A (ja) * 2001-08-30 2003-03-14 Hitachi Ltd 位相同期回路
JP2006033108A (ja) 2004-07-13 2006-02-02 Renesas Technology Corp Ｐｌｌ回路を内蔵する半導体集積回路
JP2006262348A (ja) 2005-03-18 2006-09-28 Fujitsu Ltd 半導体回路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345698A (ja) * 2000-03-27 2001-12-14 Toshiba Corp 補償機能付アナログ回路
US7352249B2 (en) 2003-10-03 2008-04-01 Analog Devices, Inc. Phase-locked loop bandwidth calibration circuit and method thereof
JP4421467B2 (ja) * 2004-12-24 2010-02-24 パナソニック株式会社 位相同期回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001016102A (ja) * 1999-06-29 2001-01-19 Nec Corp Ｐｌｌ回路方式
JP2003078410A (ja) * 2001-08-30 2003-03-14 Hitachi Ltd 位相同期回路
JP2006033108A (ja) 2004-07-13 2006-02-02 Renesas Technology Corp Ｐｌｌ回路を内蔵する半導体集積回路
JP2006262348A (ja) 2005-03-18 2006-09-28 Fujitsu Ltd 半導体回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2120344A4

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101572545A (zh) * 2009-06-12 2009-11-04 上海集成电路研发中心有限公司 锁相环电路及其控制方法

Also Published As

Publication number Publication date
JP4593669B2 (ja) 2010-12-08
US7872536B2 (en) 2011-01-18
EP2120344A1 (en) 2009-11-18
US20090315628A1 (en) 2009-12-24
EP2120344A4 (en) 2012-09-19
KR101065818B1 (ko) 2011-09-20
EP2120344B1 (en) 2013-11-06
JPWO2008084525A1 (ja) 2010-04-30
KR20090089460A (ko) 2009-08-21

Similar Documents

Publication Publication Date Title
TWI358205B (en) Frequency synthesizer and calibration device there
WO2008146433A1 (ja) スペクトラム拡散制御ｐｌｌ回路及びそのスタートアップ方法
WO2008084525A1 (ja) バラツキ補正方法、ｐｌｌ回路及び半導体集積回路
CN102361456B (zh) 一种时钟相位对齐调整电路
US9225345B2 (en) Charge pump calibration for dual-path phase-locked loop
JP6044269B2 (ja) 自励発振型ｄ級アンプおよび自励発振型ｄ級アンプの自励発振周波数制御方法
US20120319734A1 (en) System and method for reducing power consumption in a phased-locked loop circuit
JP4638806B2 (ja) 位相同期ループ回路、オフセットｐｌｌ送信機、通信用高周波集積回路及び無線通信システム
TW200735537A (en) Phase-locked loop circuit, delay-locked loop circuit and method of tuning output frequencies of the same
US9240879B2 (en) Signal generator, electronic system comprising the signal generator and method of generating signals
US8786329B1 (en) Method for doubling the frequency of a reference clock
US20100067636A1 (en) Baseband Phase-Locked Loop
JP2009296571A (ja) 発振器および位相同期回路のループ帯域補正方法
EP2312756A3 (en) A dual reference oscillator phase-lock loop
US8686768B2 (en) Phase locked loop
EP2426821A3 (en) Systems and methods for calibrating the loop bandwidth of a phase-locked loop (PLL)
TW201240353A (en) Device and method for a feedback control of switch capacitive regulator
US8760201B1 (en) Digitally programmed capacitance multiplication with one charge pump
WO2009090448A2 (en) Proportional phase comparator and method for phase-aligning digital signals
JP2008035451A (ja) 周波数シンセサイザおよびこれに用いるループフィルタ
TW201304422A (zh) 鎖相迴路裝置以及其調整電壓提供電路
US7408418B2 (en) Phase locked loop circuit having reduced lock time
US7786780B2 (en) Clock doubler circuit and method
Jovanovic et al. Delay locked loop with linear delay element
TW200731676A (en) Phase-locked loop circuit and mixed mode loop filter

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07706444

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2008552969

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2007706444

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1020097014329

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE