WO2008075480A1 - Commande d'affichage, unité de commande d'affichage et dispositif d'affichage - Google Patents

Commande d'affichage, unité de commande d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2008075480A1
WO2008075480A1 PCT/JP2007/066089 JP2007066089W WO2008075480A1 WO 2008075480 A1 WO2008075480 A1 WO 2008075480A1 JP 2007066089 W JP2007066089 W JP 2007066089W WO 2008075480 A1 WO2008075480 A1 WO 2008075480A1
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WO
WIPO (PCT)
Prior art keywords
display driver
display
output amplifier
wiring
output
Prior art date
Application number
PCT/JP2007/066089
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English (en)
Japanese (ja)
Inventor
Motomitsu Itoh
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2008075480A1 publication Critical patent/WO2008075480A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • Display driver display driver unit, and display device
  • the present invention relates to a display driver that enables driving using a spare wiring for a wiring defect of a display device.
  • a liquid crystal display device in which a source line disconnected in a manufacturing process is repaired using a spare wiring before shipment of the product and can be driven.
  • FIG. 7 is a block diagram showing the configuration of such a liquid crystal panel described in Patent Document 1.
  • the source line 110 extends from the source driver IC 131 of the source driver (source TAB) 102 into the display area 120 and from the gate driver IC 132 of the gate driver (gate TAB) 103.
  • a gate line 111 extends into the display area 120, and thereby the pixel portion 113 is driven.
  • the display area is displayed from the source driver IC 131 via the compensation output buffer 136 in the source driver 102, the source substrate 104, the connection cable 125, and the gate substrate 105.
  • a connection wiring 124 as a spare wiring arranged so as to extend to the opposite side of the source driver 102 with respect to 120 is welded by laser irradiation at the source line 110 and the connection point 152.
  • the output from the normal output buffer 134 is not included in the portion from the normal output part 135 of the normal output buffer 134 of the source driver IC1 31 to the disconnection point 151.
  • the signal is supplied from the connection point 152 to the disconnection point 151 by the output from the compensation output buffer 136 of the source driver IC 131.
  • Reference numeral 106 denotes a control board
  • reference numeral 126 denotes a flexible wiring board.
  • Patent Document 1 in this way, the disconnected source line 110 is repaired so that it can be driven.
  • Patent Documents 2 and 3 describe a configuration in which a source line is repaired using a spare wiring.
  • Patent Document 1 Japanese Published Patent Publication “JP 2003-202846 Publication (Publication Date: July 18, 2003)”
  • Patent Document 2 Japanese Patent Publication “JP-A-8-185144 (Publication Date: July 16, 1996)”
  • Patent Document 3 Japanese Patent Publication “JP-A-8-171081 (Publication Date: July 2, 1996)”
  • FIG. 8 shows a signal waveform A at the normal output unit 135 of the normal output buffer 134 and a signal waveform B at the connection point 152.
  • the signal waveform A is a voltage rising waveform corresponding to the slew rate of the operational amplifier because the normal output buffer 134 is usually an output voltage waveform of a buffer composed of a voltage follower using an operational amplifier.
  • the signal waveform at the compensation output section 137 of the compensation output buffer 136 is the same as the signal waveform A, but the signal waveform B depends on the resistance and parasitic capacitance components of the connection wiring 124 from the compensation output section 137 to the connection point 152.
  • a signal delay occurs, resulting in a delayed voltage waveform.
  • the voltage waveform further includes a delay due to the source line 110 itself rather than the signal waveform.
  • each point of the portion from the normal output unit 135 to the disconnection point 151 of the normal output buffer 134 is shown in the signal waveform A and from the normal output unit 135.
  • a voltage with a delay due to the source line 110 itself up to the point is supplied.
  • 151 stepped line In the generated source line 110, a voltage obtained by further adding a delay due to the source line 110 itself from the connection point 152 to the point is supplied to the signal waveform B at each point from the connection point 152 to the disconnection point 151. The This is a very slow voltage waveform.
  • the signal supply period tl for each source line 110 in one horizontal period is determined, and this is a sufficient time for charging the source line 110 to the target voltage V0 for the signal supply by the normal output. is there.
  • the signal supply period tl ends before the voltage rises to the target voltage V0, the charging voltage becomes VI, and the source line 110 of that portion is There is a risk of insufficient charging.
  • display deterioration such as black lines on the display area occurs.
  • the present invention has been made in view of the above problems, and an object thereof is to realize a display driver capable of setting a load driving capability of a spare output amplifier to a desired one. .
  • a display driver unit and a display device including the display driver are realized.
  • a display driver includes an output amplifier that outputs a signal to a data signal line of a display panel, and a preliminary output amplifier that is provided for the output amplifier.
  • a display driver circuit comprising: a display driver circuit comprising: a display driver circuit having at least one of a positive-phase input circuit, a negative-phase input circuit, and a feedback circuit from an output to a negative-phase input; It is characterized by having a connection part for connecting the external part for constituting at least a part of the external part using the external part.
  • At least a part of at least one of the positive-phase input circuit, the negative-phase input circuit, and the feedback circuit from the output to the negative-phase input of the operational amplifier is externally connected.
  • the spare wiring is passed through the spare wiring.
  • the power S is used to charge the data signal line to which the signal is supplied to the same voltage as the charging by the output amplifier.
  • the display driver of the present invention comprises a chip that incorporates the display driver circuit and is mounted on the display panel by COG (Chip On Glass). And a terminal connected to a wiring formed on the display panel as the connection portion.
  • COG Chip On Glass
  • the load drive capability of the auxiliary output amplifier can be set to a desired value for the display driver in the form of COG.
  • a wiring for connecting the external component is connected to the film from a chip incorporating the display driver circuit as the connection portion. It is characterized by being made up of extracted COF (Chip On Film).
  • the load driving capability of the auxiliary output amplifier can be set to a desired value for the display driver in the form of COF.
  • a wiring for connecting the external component is connected to the tape from the chip incorporating the display driver circuit as the connection portion. It is characterized by being composed of the extracted TCP (Tape Carrier Package).
  • TCP Transmission Carrier Package
  • the display driver and wiring for supplying a display drive signal to the display driver are formed, and the connection of the display driver is performed.
  • a mounting portion for the external component connected to the section is provided! /, And a printed wiring board is provided! /.
  • the display driver unit of the present invention includes the display driver and wiring for supplying a display drive signal to the display driver, and the connection of the display driver. And a printed wiring board on which the external component is mounted in a state of being connected to the unit! /.
  • a display driver that can avoid the occurrence of insufficient charging of the data signal line even when a signal is supplied to the data signal line that has been disconnected using the spare wiring. There is an effect that it can be realized.
  • the external component causes the spare output amplifier to output the output voltage of the spare output amplifier within the period of supplying the signal to the data signal line. It is characterized by a voltage that is greater than the input voltage of the output amplifier.
  • the charging voltage of the data signal line using the auxiliary output amplifier can be made substantially equal to the charging voltage of the data signal line using the output amplifier.
  • the external component causes the output voltage of the auxiliary output amplifier to be temporally changed with respect to a steady value of the output voltage of the auxiliary output amplifier. It is characterized by a vibrating waveform.
  • the output voltage of the auxiliary output amplifier is supplied to the data signal line.
  • the load drive capability of the standby output amplifier can be easily increased.
  • the external component includes a component having a variable element constant, and the length of a period during which the signal is supplied to the data signal line And an element constant control means for changing the element constant in response to the above.
  • the element constant control means by changing the element constant of the external component by the element constant control means, the optimum output voltage of the standby output amplifier in accordance with the period for supplying the signal to the data signal line is obtained. There is an effect that it can be set.
  • the display device of the present invention includes the display driver unit, and a signal output to the selected data signal line is input to the input of the auxiliary output amplifier.
  • the wiring connected to the output of the auxiliary output amplifier is formed so as to be connectable to one end of the data signal line on the side opposite to the display driver side.
  • a display device capable of avoiding the occurrence of insufficient charging of the data signal line even if the signal supply is performed using the spare wiring for the data signal line in which the disconnection has occurred. If it can be realized, it will produce an effect.
  • the display device of the present invention is a liquid crystal display device.
  • the liquid crystal display device using the spare wiring has an effect of avoiding insufficient charging of the data signal line.
  • FIG. 1, showing an embodiment of the present invention is a block diagram showing a configuration of a display device
  • FIG. 2 is a diagram showing a specific example of a spare output amplifier.
  • A shows a spare output amplifier connected with an external circuit.
  • B is a graph showing the gain characteristics of the auxiliary output amplifier in (a).
  • FIG. 5 A waveform diagram showing the waveform of the signal used in the configuration of FIG. 4, where (a) shows the case where the horizontal sync signal is used, and (b) shows the case where the vertical sync signal and the data enable signal are used. is doing.
  • FIG. 7 is a block diagram showing a conventional technique and showing a configuration of a display device.
  • FIG. 1 shows a configuration of a liquid crystal display device (display device) 1 according to the present embodiment.
  • the liquid crystal display device 1 includes a display panel 2, a plurality of source drivers 3, ..., a source substrate 4, a controller A roll board 5, a flexible wiring board 6, and a plurality of gate drivers 7 are provided.
  • the display panel 2 is provided with a plurality of gate lines (scanning signal lines) GL... And a plurality of source lines (data signal lines) SL-- '!
  • a pixel PIX is formed corresponding to each intersection of the gate line GL and the source line SL.
  • Pixel PIX has TFT15 and liquid crystal capacitor 16.
  • the gate of TFT15 is connected to gate line GL
  • the source of TFT15 is connected to source line SL
  • the drain of TFT15 is connected to the pixel electrode which is one end of liquid crystal capacitor 16.
  • the other end of the liquid crystal capacitor 16 is connected to a common electrode.
  • the source driver 3 outputs a signal for charging the liquid crystal capacitor 16 to the source line SL, and includes an output amplifier 11 corresponding to each source line SL.
  • the source driver 3 is provided in the form of COF (Chip On Film) or TCP (Tape Carrier Package), and is a display driver that generates a signal to be output to the source line SL ... on the film or tape.
  • a source driver IC3a with a built-in circuit is mounted.
  • the output amplifier 11 is formed in the source driver IC 3a, and comprises a voltage follower using an operational amplifier.
  • a source such as a shift register, a level shifter, and a DA converter circuit is provided in the source dry IC 3a.
  • a spare output amplifier 12 is further provided as described later. .
  • the source drivers 3... are supplied with various control signals and display data for deriving an output to the output amplifier 11. These control signals and display drive signals such as display data are supplied as a signal group sO from the controller 5a mounted on the control board 5.
  • the signal group sO output from the controller 5a is supplied to the source board 4 via the flexible wiring board 6.
  • the source substrate 4 supplies these signal groups sO to each source driver 3 through wiring provided on the source substrate 4 itself.
  • the gate drivers 7 supply a scanning signal to be applied to the gate of the TFT 15 of the pixel PIX to the gate lines GL ....
  • the gate driver 7 is provided in the form of COF or TCP, and the gate driver IC 7a for generating the scanning signal is mounted on the film or tape, and the source driver 3 of the display panel 2 is provided. On two sides orthogonal to the side It is attached. The left area of the display panel 2 is driven using the left gate driver 7... And the right area of the display panel 2 is driven using the right gate driver 7.
  • the supply signal to the gate driver 7 may be supplied from the control board 5 or may be supplied from the controller power provided in the middle.
  • the spare output amplifier 12 provided in the source driver IC 3a is a redundant amplifier provided preliminary to the output amplifier 11.
  • the spare output amplifier 12 is configured using an operational amplifier, and its positive phase input terminal is connected to the first spare wiring 27.
  • the first auxiliary wiring 27 is provided in the vicinity of the edge of the display panel 2 on the source drain 3 side, in parallel with the edge. In this case, one combination of the spare output amplifier 12 and the first spare wiring 27 is provided for each source driver 3! /, And any number of pairs of source drivers 3 may be provided.
  • the reverse-phase input circuit of the auxiliary output amplifier 12 and the feedback circuit from the output to the reverse-phase input are provided as an external circuit 12 a on the source substrate 4.
  • the external circuit 12a will be described later.
  • the output of the auxiliary output amplifier 12 is drawn out on the film or tape of the source driver 3 as a connection part for connecting the external circuit 12a, and further connected to the wiring on the source board 4 to be connected to the source board 4 Connected to external circuit 12a at point Q above
  • the output of the auxiliary output amplifier 12 drawn out on the source substrate 4 is connected to the second auxiliary wiring 21 at the point Q described above.
  • the second spare wiring 21 is provided for each source driver 3 and crosses over the source driver 3 located at both ends of the source driver group from the source board 4 to the vicinity of the gate driver 7 side edge of the display panel 2. Further, the vicinity of the end side opposite to the source driver 3 side of the display panel 2 is provided in parallel to the end side.
  • the second auxiliary wiring 21 connected to the auxiliary output amplifier 12 of the source driver 3 may Provided in the left area of the display panel 2 bypasses the display area 2 by bypassing the left end side of the display panel 2.
  • the second spare wiring 2 1 connected to the spare output amplifier 12 of the source driver 3 ⁇ which is routed to a position opposite to the source driver 3 ⁇ and to the right side area of the display panel 2 is Then, bypass the right edge side of the display panel 2 and be routed to the position facing the source driver 3 • ⁇ across the display area 2!
  • the first spare wiring 27 and the second spare wiring 21 are wirings used to repair the disconnected source line SL when the source line SL is disconnected in the manufacturing stage of the liquid crystal display device 1.
  • the output of the output amplifier 11 of the source driver 3 connected to the source line SL is represented by a corresponding P as shown by a point P.
  • the portion of the disconnected source line SL from the output amplifier 11 to the disconnected portion 25 and the selected pixel connected thereto are charged by the output of the output amplifier 11, and the portion from the point R to the stepped portion is charged.
  • the portion up to 25 and the selected pixel connected to the portion are charged by the output of the auxiliary output amplifier 12.
  • FIG. 2 (a) shows an example of a configuration in which the external circuit 12 a is connected to the auxiliary output amplifier 12.
  • the positive phase input terminal of the auxiliary output amplifier 12 is connected to the point P in FIG. 1, and the output voltage Vin of the output amplifier 11 is inputted.
  • a parallel circuit of a resistor R1 and a capacitor C is connected between the negative-phase input terminal of the auxiliary output amplifier 12 and GND, and this parallel circuit constitutes a negative-phase input circuit.
  • a resistor R2 is inserted between the output terminal of the auxiliary output amplifier 12 and the negative phase input terminal, and this resistor R2 forms a feedback circuit from the output of the auxiliary output amplifier 12 to the negative phase input. ing.
  • the output terminal of auxiliary output amplifier 12 is connected to point Q in Fig.1.
  • the source driver IC 3a Since the external circuit 12a is not monolithically formed with the spare output amplifier 12 in the source driver IC 3a, the source driver IC 3a has a reverse-phase input terminal of the spare output amplifier 12 and an output terminal. Each drawing wiring force of the source driver 3 is drawn to the source substrate 4 across the film or tape. Then, it is connected to an external circuit 12a composed of a resistor Rl, a resistor R2, and a capacitor C mounted at a mounting location of an external component provided on the source substrate 4.
  • FIG. 2 (b) shows a spare output amplifier 12 in a state where the external circuit 12a having the above configuration is connected. Shows the frequency characteristics of the gain of the output voltage Vout with respect to the input voltage Vin. Curve E shows the characteristics without capacitance C, curve F shows the characteristics when capacitance C is small, and curve G shows the characteristics when capacitance C is large.
  • the curve E corresponds to a configuration in which the capacitor C is not provided in FIG. 2A, and the time change of the output voltage Vout after the input voltage Vin is input is shown in FIG.
  • the voltage at point P rises to V0 and stabilizes, while the voltage at point Q becomes higher than V0 within the signal supply period tl and then rises to VI and stabilizes. To do. This indicates that the load driving capability of the auxiliary output amplifier 12 has increased.
  • the voltage waveform at point R where the voltage waveform at point Q appears delayed by the resistance and parasitic capacitance of the second auxiliary wiring 21, is as shown by the curve R in FIG. 3 (a). . Accordingly, if the resistance values (element constants) of the resistors R1 and R2 are appropriately selected, the voltage at the point R is set at the end of the signal supply period tl to the source line SL as shown in FIG. The power can be almost equal to the voltage at point P, and the source line SL can be charged to approximately the same voltage at the point P side from the disconnection point 25 to the point P side at the disconnection point 25. be able to.
  • the voltage waveform at point R where the voltage waveform at point Q appears delayed by the resistance and parasitic capacitance of the second auxiliary wiring 21, is as shown by curve R in Fig. 3 (b). Become. Therefore, resistor R1 If the resistance value (element constant) of resistor R2 is selected appropriately, as shown in Fig. 3 (b), at the end of signal supply period tl to source line SL, The voltage at point R can be made approximately equal to the voltage at point P, and the source line SL is charged at the same voltage from the disconnection point 25 to the point P side and from the disconnection point 25 to the point R side. The power S to do.
  • the source driver 3 can connect the external components constituting the external circuit 12a.
  • the display driver can set the load driving capability of the auxiliary output amplifier 12 to a desired one.
  • the external circuit 12a is a circuit that constitutes a reverse-phase input circuit of the auxiliary output amplifier 12 and a feedback circuit from the output to the negative-phase input, but is not limited thereto, and is not limited to this. Any circuit that constitutes at least a part of at least one of the 12 positive-phase input circuits, the negative-phase input circuit, and the feedback circuit may be used. That is, by connecting the external circuit 12a to the auxiliary output amplifier 12, at least a part of at least one of the positive phase input circuit, the negative phase input circuit, and the feedback circuit of the auxiliary output amplifier 12 is connected. What is necessary is just to comprise using external parts.
  • the resistor R2 is a spare output amplifier in the source driver IC3a.
  • the resistor R1 and the capacitor C can be used as external parts constituting the external circuit 12a. Also, only the resistor R1, only the resistor R2, and only the resistor C can be used as external parts constituting the circuit 12a. Furthermore, the non-inverting amplifier having the positive phase input circuit may be configured such that the positive phase input circuit, the negative phase input circuit, and the feedback circuit are all external circuits 12a. [0067] Although the above voltage has been described by taking a positive polarity as an example, the negative voltage also has a rising edge in the description of positive polarity and an overshoot undershoot. The same effect can be obtained.
  • the resistor R2 is configured with a variable resistor, for example, an electronic volume, as shown in FIG. 3A
  • the resistance of the resistor R2 is controlled by the control signal si input to the resistor R2.
  • the gain of the auxiliary output amplifier 12 can be changed. In this way, the rising speed of the curve Q in (a) and (b) of FIG. 3 can be changed, so that the optimum curve Q is adapted to the length of the signal supply period tl to the source line SL. Can be set.
  • an ASI C (element constant control means) 31 for resistance value control on the source substrate 4.
  • the resistance value control ASIC 31 receives information on the signal supply period tl from the signal group sO output from the control board 5, generates a control signal si according to the length of the signal supply period tl, and outputs it to the resistor R2. To do.
  • the horizontal synchronization signal HSYNC is used as information regarding the signal supply period tl.
  • Figure 4 shows the configuration of the ASIC 31 for resistance control in this case.
  • the resistance value control ASIC 31 of FIG. 4 includes a counter unit 31a, a period calculation unit 31b, a lookup table 31c, and a control signal generation unit 31d.
  • the horizontal synchronizing signal HSYNC included in the signal group sO output from the controller board 5 and the clock signal CK generated from the crystal oscillation circuit 30 are input to the counter unit 31a.
  • the counter unit 31a has one cycle of the horizontal synchronization signal HSYNC.
  • the number of clock signals CK corresponding to a much smaller period is counted, and the count result N is input to the period calculation unit 31b.
  • the period calculation unit 31b calculates the length of one horizontal period (signal supply period tl) based on the input count result, and stores the calculation result (length of the signal supply period tl) in the lookup table 31c. Enter in. [0075]
  • the lookup table 31c is stored in the memory of the resistance value control ASIC 31 in advance, and describes the correspondence between the length of one horizontal period and the resistance value to be set in the resistor R2. .
  • the lookup table 31c inputs a signal k related to resistance value information corresponding to the input calculation result of the length of one horizontal period to the control signal generation unit 31d.
  • the control signal generation unit 31d generates a control signal si corresponding to the input signal k and inputs the control signal si to the resistor R2.
  • the length of one horizontal period is calculated from the period of the horizontal synchronization signal HSYNC.
  • the present invention is not limited to this, and the vertical synchronization signal VSYNC as shown in (b) of FIG. It may be calculated from the cycle or the cycle of the data DATA enable signal ENA.
  • the resistance value control ASIC 31 is provided not only on the source board 4 but also on the control board 5! /, May! /.
  • the resistance value of the resistor R2 is variable.
  • the element constant of any element constituting 12a can be made variable.
  • the source driver 3 is configured by COF or TCP.
  • the source driver IC3a chip is mounted on the film 41 as shown in FIG. 6 (b), and the spare output amplifier 12 of the source driver 3 is directed from the source driver IC3a to the film 41.
  • Wiring 35 is drawn out as a connection part for connecting external parts constituting the external circuit 12a.
  • the source driver IC3a chip is mounted on the tape 42 as shown in FIG. 6 (c), and the spare output amplifier 12 is directed from the source driver IC3a to the tape 42.
  • Wiring 35 is drawn out as a connecting portion for connecting external parts constituting the external circuit 12a.
  • the source driver IC3a chip can be mounted on the display panel 2 in the form of COG (Chip On Glass).
  • the source driver IC 3a has a terminal as a connection portion connected to the wiring 35 formed on the display panel 2 for connecting an external component constituting the external circuit 12a.
  • the external circuit 12a may be connected on the source substrate 4 directly connected to the display panel 2.
  • the number of wirings 35 is the same as that of the external circuit 12a, the positive-phase input circuit, the negative-phase input circuit, and the feedback circuit of the auxiliary output amplifier 12. Because it depends on which part of the circuit it is, it is not limited to the two shown!
  • the configuration composed of the source drivers 3... And the source substrate 4 can be handled as one display driver unit.
  • the display driver unit further includes other components such as a control board 5 and a flexible wiring board 6! /.
  • the display driver unit is provided with a place where the external circuit 12a is mounted, and may exist in a state before the external circuit 12a is mounted. In this case, a person who intends to manufacture a display device using this display driver unit selects and mounts external components appropriately, and adjusts the data signal line according to the display device to be manufactured. It is possible to avoid the occurrence of insufficient charging.
  • the display panel and display device in addition to the liquid crystal, for example, an organic EL element, a dielectric liquid, an electrochromic device, or the like may be used as the display element.
  • the display driver of the present invention includes at least one of the positive-phase input circuit, the negative-phase input circuit, and the feedback circuit from the output to the negative-phase input of the operational amplifier. Both of them have a connection part for connecting the external parts for constituting a part using the external parts.
  • the present invention relates to a high-definition, large-screen liquid crystal display device in which the occurrence probability of disconnection is high, It can be preferably used.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention porte sur des circuits de rétroaction et d'entrée à phase de polarité inverse d'un amplificateur (12) de sortie préliminaire disposé dans un circuit intégré de commande source (3a) pouvant être connectés sous forme de circuit externe (12a) sur une carte source (4). Une constante d'élément du circuit externe (12a) est réglée de telle sorte que la valeur de la tension de sortie de l'amplificateur (12) de sortie de rechange devient supérieure à celle de la sortie d'entrée. Ceci fournit une commande d'affichage dans laquelle l'aptitude à commander une charge de l'amplificateur de sortie préliminaire peut être réglée à une commande désirée.
PCT/JP2007/066089 2006-12-20 2007-08-20 Commande d'affichage, unité de commande d'affichage et dispositif d'affichage WO2008075480A1 (fr)

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Cited By (7)

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Publication number Priority date Publication date Assignee Title
WO2010052971A1 (fr) 2008-11-10 2010-05-14 シャープ株式会社 Appareil d’affichage
JP2011133896A (ja) * 2009-12-24 2011-07-07 Silicon Works Co Ltd 液晶表示装置のソースドライバー回路
WO2012137817A1 (fr) * 2011-04-08 2012-10-11 シャープ株式会社 Dispositif d'affichage et procédé de commande d'un dispositif d'affichage
WO2016103370A1 (fr) * 2014-12-24 2016-06-30 堺ディスプレイプロダクト株式会社 Dispositif d'affichage et procédé de fabrication de dispositif d'affichage
WO2016132435A1 (fr) * 2015-02-16 2016-08-25 堺ディスプレイプロダクト株式会社 Dispositif de circuit et dispositif d'affichage
WO2017069193A1 (fr) * 2015-10-22 2017-04-27 シャープ株式会社 Panneau d'affichage à cristaux liquides et procédé de correction associé
CN110956917A (zh) * 2019-12-05 2020-04-03 南京中电熊猫平板显示科技有限公司 一种面板显示模组的修复补偿方法

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CN102203849A (zh) * 2008-11-10 2011-09-28 夏普株式会社 显示装置
JP5096591B2 (ja) * 2008-11-10 2012-12-12 シャープ株式会社 表示装置
WO2010052971A1 (fr) 2008-11-10 2010-05-14 シャープ株式会社 Appareil d’affichage
JP2011133896A (ja) * 2009-12-24 2011-07-07 Silicon Works Co Ltd 液晶表示装置のソースドライバー回路
CN106205519A (zh) * 2011-04-08 2016-12-07 夏普株式会社 显示装置和显示装置的驱动方法
WO2012137817A1 (fr) * 2011-04-08 2012-10-11 シャープ株式会社 Dispositif d'affichage et procédé de commande d'un dispositif d'affichage
CN103477384A (zh) * 2011-04-08 2013-12-25 夏普株式会社 显示装置和显示装置的驱动方法
JP5399586B2 (ja) * 2011-04-08 2014-01-29 シャープ株式会社 表示装置
US9129544B2 (en) 2011-04-08 2015-09-08 Sharp Kabushiki Kaisha Display device, and method for driving display device
WO2016103370A1 (fr) * 2014-12-24 2016-06-30 堺ディスプレイプロダクト株式会社 Dispositif d'affichage et procédé de fabrication de dispositif d'affichage
CN107111971A (zh) * 2014-12-24 2017-08-29 堺显示器制品株式会社 显示装置和显示装置的制造方法
JPWO2016103370A1 (ja) * 2014-12-24 2017-11-02 堺ディスプレイプロダクト株式会社 表示装置及び表示装置の製造方法
CN107111971B (zh) * 2014-12-24 2020-01-17 堺显示器制品株式会社 显示装置和显示装置的制造方法
WO2016132435A1 (fr) * 2015-02-16 2016-08-25 堺ディスプレイプロダクト株式会社 Dispositif de circuit et dispositif d'affichage
JPWO2016132435A1 (ja) * 2015-02-16 2018-01-18 堺ディスプレイプロダクト株式会社 回路装置及び表示装置
US10159145B2 (en) 2015-02-16 2018-12-18 Sakai Display Products Corporation Circuit device and display apparatus
WO2017069193A1 (fr) * 2015-10-22 2017-04-27 シャープ株式会社 Panneau d'affichage à cristaux liquides et procédé de correction associé
JPWO2017069193A1 (ja) * 2015-10-22 2018-08-09 シャープ株式会社 液晶表示パネルおよびその修正方法
CN110956917A (zh) * 2019-12-05 2020-04-03 南京中电熊猫平板显示科技有限公司 一种面板显示模组的修复补偿方法

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