US20100265229A1 - Level regulation circuit of common signal of lcd - Google Patents
Level regulation circuit of common signal of lcd Download PDFInfo
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- US20100265229A1 US20100265229A1 US12/536,468 US53646809A US2010265229A1 US 20100265229 A1 US20100265229 A1 US 20100265229A1 US 53646809 A US53646809 A US 53646809A US 2010265229 A1 US2010265229 A1 US 2010265229A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
Definitions
- the storage capacitor CcsO of the first sub-pixel is electrically connected to a first common signal line 24 O.
- the storage capacitor CcsE of the second sub-pixel is electrically connected to a second common signal line 24 E.
- the voltage drops across the storage capacitors CcsO and CcsE can be different.
- FIG. 2 is a waveform diagram illustrating voltage level of control signals of the pixel shown in FIG. 1 .
- Vs(m) represents the voltage signal of the data line 14 ( m ).
- Vcom represents the common voltage.
- Vg(n) represents the voltage signal of the scan line 12 ( n ).
- VgH represents the high-level voltage of Vg(n), and
- VgL represents the low-level voltage of Vg(n).
- VcsO represents the voltage signal of the first common signal line 24 O.
- VcsE represents the voltage signal of the second common signal line 24 E.
- VcsH represents the high-level voltage of VcsO and VcsE.
- VcsL represents the low-level voltage of VcsO and VcsE.
- the common voltage Vcom of display panels of LCDs are different, the common voltage Vcom is required to be adjusted for reducing the flicker of the LCD.
- the high-level voltage VcsH and the low-level voltage VcsL of the voltage signals VcsO and VcsE can not be adjusted when adjusting the common voltage Vcom. In this way, the flicker of the LCD can not be effectively reduced.
- An objective of the present invention is to provide a level regulation circuit of a common signal of a Liquid Crystal Display (LCD).
- LCD Liquid Crystal Display
- the present invention provides a level regulation circuit of a common signal of an LCD.
- the level regulation circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a Zener diode.
- the operational amplifier comprises a positive input end, a negative input end, and an output end.
- the first resistor comprises a first end and a second end. The first end of the first resistor is electrically connected to the negative input end of the operational amplifier.
- the second end of the first resistor is electrically connected to a ground end.
- the second resistor comprises a first end and a second end. The first end of the second resistor is electrically connected to the positive input end of the operational amplifier.
- the second end of the second resistor is utilized for receiving a common voltage.
- the third resistor comprises a first end and a second end.
- the first end of the third resistor is electrically connected to the positive input end of the operational amplifier.
- the second end of the third resistor is utilized for receiving a reference voltage.
- the fourth resistor comprises a first end and a second end.
- the first end of the fourth resistor is electrically connected to the negative input end of the operational amplifier.
- the second end of the fourth resistor is electrically connected to the output end of the operational amplifier.
- the Zener diode comprises a first end and a second end.
- the first end of the Zener diode is electrically connected to the output end of the operational amplifier and is utilized for outputting a first level voltage of the common signal.
- the second end of the Zener diode is electrically connected to the ground end through an output resistor and is utilized for outputting a second level voltage of the common signal.
- the present invention further provides a level regulation circuit of a common signal of an LCD.
- the level regulation circuit comprises an operational amplifier, a resistor, a first Zener diode, and a second Zener diode.
- the operational amplifier comprises a positive input end, a negative input end, and an output end. The output end of the operational amplifier is electrically connected to the negative input end of the operational amplifier.
- the resistor comprises a first end and a second end. The first end of the resistor is electrically connected to the positive input end of the operational amplifier. The second end of the resistor is utilized for receiving a reference voltage.
- the first Zener diode comprises a first end and a second end. The first end of the first Zener diode is electrically connected to the positive input end of the operational amplifier.
- the second of the first Zener diode is utilized for receiving a common voltage.
- the second Zener diode comprises a first end and a second end.
- the first end of the second Zener diode is electrically connected to the output end of the operational amplifier and is utilized for outputting a first level voltage of the common signal.
- the second end of the second Zener diode is electrically connected to a ground end and is utilized for outputting a second level voltage of the common signal.
- FIG. 1 is a diagram illustrating a pixel of a conventional TFT LCD.
- FIG. 2 is a waveform diagram illustrating voltage level of control signals of the pixel shown in FIG. 1 .
- FIG. 3 is a waveform diagram illustrating common signals of an LCD.
- FIG. 4 is a block diagram illustrating a generating circuit of the common signals.
- FIG. 5 is a diagram illustrating a level regulation circuit of the common signals.
- FIG. 6 is a circuit diagram illustrating a level regulation circuit of the common signals according to the first embodiment of the present invention.
- FIG. 7 is a circuit diagram illustrating a level regulation circuit of the common signals according to the second embodiment of the present invention.
- FIG. 8 is a circuit diagram illustrating a current amplifier.
- FIG. 9 is a circuit diagram illustrating a signal-generating circuit.
- FIG. 3 is a waveform diagram illustrating common signals of an LCD.
- the common signals are swing signals comprising a first common signal CSO and a second common signal CSE.
- the first common signal CSO and the second common signal CSE are complementary.
- the high-level voltage VCSH and the low-level voltage VCSL are symmetrical to each other and the voltage level of the common voltage VCOM is in the middle of the high-level voltage VCSH and the low-level voltage VCSL.
- the voltage difference between the high-level voltage VCSH and the common voltage VCOM is ⁇ V
- the voltage difference between the common voltage VCOM and the low-level voltage VCSL is ⁇ V as well. Therefore, the high-level voltage VCSH and the low-level voltage VCSL can be represented as the following formulas:
- the common electrode end of the first storage capacitor of the pixel receives the first common signal CSO and the common electrode end of the second storage capacitor of the pixel receives the second common signal CSE.
- the high-level voltage VCSH and the low-level voltage VCSL of the common signals are required to be varied with the common voltage VCOM for avoiding the flicker of the LCD caused by the voltage asymmetry of the storage capacitors during the inversion of the liquid crystal.
- FIG. 4 is a block diagram illustrating a generating circuit of the common signals.
- the generating circuit of the common signals comprises a level regulation circuit 500 , a current amplifier 600 , and a signal-outputting circuit 700 .
- the level regulation circuit 500 generates the high-level voltage VCSH and the low-level voltage VCSL of the common signals according to the common voltage.
- the current amplifier 600 increases the driving ability of the high-level voltage VCSH and the low-level voltage VCSL of the common signals.
- the signal-outputting circuit 700 is utilized for pulling the voltage level of the clock signal up between the high-level voltage VCSH and the low-level voltage VCSL of the common signals.
- the signal-outputting circuit 700 can generate the first common signal CSO and the second common signal CSE according to the high-level voltage VCSH and the low-level voltage VCSL of the common signals.
- FIG. 5 is a diagram illustrating a level regulation circuit of the common signals.
- the level regulation circuit of the common signals can be embodied by means of an adder 551 and a subtractor 552 generating the high-level voltage VCSH and the low-level voltage VCSL of the common signals according to the formulas (1) and (2).
- the high-level voltage VCSH can be generated by the adder 551 adding the common voltage VCOM and the voltage difference
- the low-level voltage VCSL can be generated by the subtractor 552 subtracting the voltage difference from the common voltage VCOM.
- the adder 551 and the subtrator 552 require an operational amplifier, respectively.
- the high-level voltage VCSH and the low-level voltage VCSL of the common signals can be generated by means of only one operational amplifier.
- FIG. 6 is a circuit diagram illustrating the first embodiment of a level regulation circuit of the common signals according to the present invention.
- the level regulation circuit comprises an operational amplifier 511 , five resistors 512 , 513 , 514 , 515 , and 517 , and a Zener diode 516 .
- Both of the resistances of the resistors 512 and 514 are R 1 .
- Both of the resistances of the resistors 513 and 515 are R 2 .
- the resistance of the resistor 517 is R.
- the breakdown voltage of the Zener diode 516 is 2 ⁇ V.
- the resistor 512 is electrically connected between a negative input end of the operational amplifier 511 and a ground end.
- the resistor 513 is electrically connected between a positive input end of the operational amplifier 511 and the common voltage source VCOM (providing the reference voltage VCOM).
- the resistor 514 is electrically connected between the positive input end of the operation amplifier 511 and a reference voltage source V 1 (providing the reference voltage V 1 ).
- the resistor 515 is electrically connected between the negative input end of the operation amplifier 511 and an output end of the operation amplifier 511 .
- the Zener diode 516 is electrically connected to the output end of the operational amplifier 511 .
- the resistor 517 is electrically connected between the Zener diode 516 and the ground end.
- the high-level voltage VCSH of the common signals can be generated from the output end of the operational amplifier 511 .
- the relationship between the common voltage VCOM and the high-level voltage VCSH can be represented as the following formula:
- V 1 ⁇ (R 2 /R 1 ) can be equal to ⁇ V by means of adjusting the resistance R 1 and R 2 .
- the high-level voltage VCSH can be equal to (VCOM+ ⁇ V).
- the Zener diode 516 is operated at the breakdown voltage 2 ⁇ V.
- the level regulation circuit of the present invention can generate the high-level voltage VCSH and the low-level voltage VCSL of the common signals by means of only one operational amplifier.
- FIG. 7 is a circuit diagram illustrating the second embodiment of a level regulation circuit of the common signals according to the present invention.
- the level regulation circuit can stably generate the high-level voltage VCSH equal to (VCOM+ ⁇ V).
- the level regulation circuit comprises an operational amplifier 531 , two resistors 533 and 535 , and two Zener diodes 532 and 534 .
- the resistance of the resistor 533 is R 3 .
- the resistance of the resistor 535 is R.
- the breakdown voltage of the Zener diode 532 is ⁇ V.
- the breakdown voltage of the Zener diode 534 is 2 ⁇ V.
- the resistor 533 is electrically connected between a positive input end of the operational amplifier 531 and the reference voltage source V 1 .
- the Zener diode 532 is electrically connected between the positive input end of the operational amplifier 531 and the common voltage source VCOM.
- a negative input end of the operational amplifier 531 is electrically connected to an output end of the operational amplifier 531 .
- the Zener diode 534 is electrically connected to the output end of the operational amplifier 531 .
- the resistor 535 is electrically connected between the Zener diode 534 and the ground end.
- the voltage level of the reference voltage V 1 must be higher than VCOM. In this way, even if the common voltage VCOM is varied, the Zener diode 532 still can be operated at the breakdown voltage ⁇ V.
- the high-level voltage VCSH of the common signals can be generated from the output end of the operational amplifier 531 .
- the relationship between the common voltage VCOM and the high-level voltage VCSH can be represented as the following formula:
- the low-level voltage VCSL is generated to be equal to (VCOM ⁇ V) by means of the high-level voltage VCSH passing by the Zener diode 534 .
- the operational amplifier 531 forms a voltage follower. As a result, as long as the voltage on the positive input end of the operational amplifier 531 is equal to (VCOM+ ⁇ V), the voltage on the output end of the operational amplifier 531 is equal to (VCOM+ ⁇ V).
- FIG. 8 is a circuit diagram illustrating a current amplifier.
- the current amplifier comprises an NPN transistor 611 , a PNP transistor 612 , and an operational amplifier 613 .
- the NPN transistor 611 is electrically connected to the reference voltage source V 1 .
- the PNP transistor 612 is electrically connected to the ground end.
- the NPN transistor 611 and the PNP transistor 612 form an inverter.
- An output end of the operational amplifier 613 is electrically connected to an input end of the inverter.
- a negative input end of the operational amplifier 613 is electrically connected to an output end of the inverter.
- the high-level voltage VCSH and the low-level voltage VCSL generated by the level regulation circuit is inputted to a positive input end of the operational amplifier 613 .
- the current amplifier can increase the driving ability of the high-level voltage VCSH and the low-level voltage VCSL.
- FIG. 9 is a circuit diagram illustrating a signal-outputting circuit.
- the signal-generating circuit comprises two PMOS transistor 711 and 713 , and two NMOS transistor 712 and 714 .
- the PMOS transistors 711 and 713 are electrically connected to the high-level voltage VCSH of the common signals.
- the NMOS transistors 712 and 714 are electrically connected to the low-level voltage of the common signals.
- the PMOS transistor 711 and the NMOS transistor 712 form a first inverter.
- the PMOS transistor 713 and the NMOS transistor 714 form a second inverter.
- the voltage level of the clock signal can be pulled up between the high-level voltage VCSH and the low-level voltage VCSL.
- the first common signal CSO is outputted from the node B
- the second common signal CSE is outputted from the node C.
- the present invention provides a level regulation circuit of a common signal of an LCD generates a first level voltage and a second level voltage according to a common voltage so as to generate a first common signal and a second common signal.
- Each pixel of the LCD includes two storage capacitors receiving the first common signal and the second common signal respectively.
- the level regulation circuit of the common signal uses an operational amplifier and one or two Zener diodes to generate the first level voltage and the second level voltage.
- the first level voltage and the second level voltage have the same voltage difference to the common voltage, so the flicker of the LCD can be reduced.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to a level regulation circuit of a common signal, and more particularly, to a level regulation circuit of common signals of a Liquid Crystal Display (LCD).
- 2. Description of the Prior Art
- Please refer to
FIG. 1 .FIG. 1 is a diagram illustrating a pixel of a conventional Thin Film Transistor (TFT) LCD. Each pixel of the LCD includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes aTFT 16 a, a liquid capacitor ClcO, and a storage capacitor CcsO. The second sub-pixel includes aTFT 16 b, a liquid capacitor ClcE, and a storage capacitor CcsE. The TFT 16 a of the first sub-pixel and theTFT 16 b of the second sub-pixel are electrically connected to the same data line 14(m) and the same scan line 12(n). The storage capacitor CcsO of the first sub-pixel is electrically connected to a first common signal line 24O. The storage capacitor CcsE of the second sub-pixel is electrically connected to a secondcommon signal line 24E. Thus, the voltage drops across the storage capacitors CcsO and CcsE can be different. - Please refer to
FIG. 2 .FIG. 2 is a waveform diagram illustrating voltage level of control signals of the pixel shown inFIG. 1 . Vs(m) represents the voltage signal of the data line 14(m). Vcom represents the common voltage. Vg(n) represents the voltage signal of the scan line 12(n). VgH represents the high-level voltage of Vg(n), and VgL represents the low-level voltage of Vg(n). VcsO represents the voltage signal of the first common signal line 24O. VcsE represents the voltage signal of the secondcommon signal line 24E. VcsH represents the high-level voltage of VcsO and VcsE. VcsL represents the low-level voltage of VcsO and VcsE. VlcO represents the voltage signal of the liquid capacitor ClcO of the first sub-pixel. VlcE represents the voltage signal of the liquid capacitor ClcE of the second sub-pixel. Vlc(c) represents the central voltage of the liquid capacitor. The voltage signal VcsO of the first common signal line 24O is complementary to the voltage signal VcsE of the firstcommon signal line 24E. The voltage level of common voltage Vcom is in the middle of the high-level voltage VcsH and the low-level voltage VcsL and serves as the bias voltage of the voltage signals VcsO and VcsE. The voltage signals VcsO and VcsE are square waves. - Since the common voltages Vcom of display panels of LCDs are different, the common voltage Vcom is required to be adjusted for reducing the flicker of the LCD. However, in the above-mentioned LCD, wherein each pixel includes two sub-pixels, the high-level voltage VcsH and the low-level voltage VcsL of the voltage signals VcsO and VcsE can not be adjusted when adjusting the common voltage Vcom. In this way, the flicker of the LCD can not be effectively reduced.
- An objective of the present invention is to provide a level regulation circuit of a common signal of a Liquid Crystal Display (LCD).
- The present invention provides a level regulation circuit of a common signal of an LCD. The level regulation circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a Zener diode. The operational amplifier comprises a positive input end, a negative input end, and an output end. The first resistor comprises a first end and a second end. The first end of the first resistor is electrically connected to the negative input end of the operational amplifier. The second end of the first resistor is electrically connected to a ground end. The second resistor comprises a first end and a second end. The first end of the second resistor is electrically connected to the positive input end of the operational amplifier. The second end of the second resistor is utilized for receiving a common voltage. The third resistor comprises a first end and a second end. The first end of the third resistor is electrically connected to the positive input end of the operational amplifier. The second end of the third resistor is utilized for receiving a reference voltage. The fourth resistor comprises a first end and a second end. The first end of the fourth resistor is electrically connected to the negative input end of the operational amplifier. The second end of the fourth resistor is electrically connected to the output end of the operational amplifier. The Zener diode comprises a first end and a second end. The first end of the Zener diode is electrically connected to the output end of the operational amplifier and is utilized for outputting a first level voltage of the common signal. The second end of the Zener diode is electrically connected to the ground end through an output resistor and is utilized for outputting a second level voltage of the common signal.
- The present invention further provides a level regulation circuit of a common signal of an LCD. The level regulation circuit comprises an operational amplifier, a resistor, a first Zener diode, and a second Zener diode. The operational amplifier comprises a positive input end, a negative input end, and an output end. The output end of the operational amplifier is electrically connected to the negative input end of the operational amplifier. The resistor comprises a first end and a second end. The first end of the resistor is electrically connected to the positive input end of the operational amplifier. The second end of the resistor is utilized for receiving a reference voltage. The first Zener diode comprises a first end and a second end. The first end of the first Zener diode is electrically connected to the positive input end of the operational amplifier. The second of the first Zener diode is utilized for receiving a common voltage. The second Zener diode comprises a first end and a second end. The first end of the second Zener diode is electrically connected to the output end of the operational amplifier and is utilized for outputting a first level voltage of the common signal. The second end of the second Zener diode is electrically connected to a ground end and is utilized for outputting a second level voltage of the common signal.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 is a diagram illustrating a pixel of a conventional TFT LCD. -
FIG. 2 is a waveform diagram illustrating voltage level of control signals of the pixel shown inFIG. 1 . -
FIG. 3 is a waveform diagram illustrating common signals of an LCD. -
FIG. 4 is a block diagram illustrating a generating circuit of the common signals. -
FIG. 5 is a diagram illustrating a level regulation circuit of the common signals. -
FIG. 6 is a circuit diagram illustrating a level regulation circuit of the common signals according to the first embodiment of the present invention. -
FIG. 7 is a circuit diagram illustrating a level regulation circuit of the common signals according to the second embodiment of the present invention. -
FIG. 8 is a circuit diagram illustrating a current amplifier. -
FIG. 9 is a circuit diagram illustrating a signal-generating circuit. - Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . .” Also, the term “electrically connect” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
- Please refer to
FIG. 3 .FIG. 3 is a waveform diagram illustrating common signals of an LCD. In the embodiment of the present invention, the common signals are swing signals comprising a first common signal CSO and a second common signal CSE. The first common signal CSO and the second common signal CSE are complementary. The high-level voltage VCSH and the low-level voltage VCSL are symmetrical to each other and the voltage level of the common voltage VCOM is in the middle of the high-level voltage VCSH and the low-level voltage VCSL. Furthermore, the voltage difference between the high-level voltage VCSH and the common voltage VCOM is ΔV, and the voltage difference between the common voltage VCOM and the low-level voltage VCSL is ΔV as well. Therefore, the high-level voltage VCSH and the low-level voltage VCSL can be represented as the following formulas: -
VCSH=VCOM+ΔV (1); -
VCSL=VCOM−ΔV (2); - the common electrode end of the first storage capacitor of the pixel receives the first common signal CSO and the common electrode end of the second storage capacitor of the pixel receives the second common signal CSE. Hence, the high-level voltage VCSH and the low-level voltage VCSL of the common signals are required to be varied with the common voltage VCOM for avoiding the flicker of the LCD caused by the voltage asymmetry of the storage capacitors during the inversion of the liquid crystal.
- Please refer to
FIG. 4 .FIG. 4 is a block diagram illustrating a generating circuit of the common signals. The generating circuit of the common signals comprises alevel regulation circuit 500, acurrent amplifier 600, and a signal-outputtingcircuit 700. Thelevel regulation circuit 500 generates the high-level voltage VCSH and the low-level voltage VCSL of the common signals according to the common voltage. Thecurrent amplifier 600 increases the driving ability of the high-level voltage VCSH and the low-level voltage VCSL of the common signals. The signal-outputtingcircuit 700 is utilized for pulling the voltage level of the clock signal up between the high-level voltage VCSH and the low-level voltage VCSL of the common signals. Thus, the signal-outputtingcircuit 700 can generate the first common signal CSO and the second common signal CSE according to the high-level voltage VCSH and the low-level voltage VCSL of the common signals. - Please refer to
FIG. 5 .FIG. 5 is a diagram illustrating a level regulation circuit of the common signals. The level regulation circuit of the common signals can be embodied by means of anadder 551 and asubtractor 552 generating the high-level voltage VCSH and the low-level voltage VCSL of the common signals according to the formulas (1) and (2). The high-level voltage VCSH can be generated by theadder 551 adding the common voltage VCOM and the voltage difference, and the low-level voltage VCSL can be generated by thesubtractor 552 subtracting the voltage difference from the common voltage VCOM. Generally speaking, theadder 551 and thesubtrator 552 require an operational amplifier, respectively. However, in the present invention, the high-level voltage VCSH and the low-level voltage VCSL of the common signals can be generated by means of only one operational amplifier. - Please refer to
FIG. 6 .FIG. 6 is a circuit diagram illustrating the first embodiment of a level regulation circuit of the common signals according to the present invention. The level regulation circuit comprises anoperational amplifier 511, fiveresistors Zener diode 516. Both of the resistances of theresistors resistors resistor 517 is R. The breakdown voltage of theZener diode 516 is 2ΔV. Theresistor 512 is electrically connected between a negative input end of theoperational amplifier 511 and a ground end. Theresistor 513 is electrically connected between a positive input end of theoperational amplifier 511 and the common voltage source VCOM (providing the reference voltage VCOM). Theresistor 514 is electrically connected between the positive input end of theoperation amplifier 511 and a reference voltage source V1 (providing the reference voltage V1). Theresistor 515 is electrically connected between the negative input end of theoperation amplifier 511 and an output end of theoperation amplifier 511. TheZener diode 516 is electrically connected to the output end of theoperational amplifier 511. Theresistor 517 is electrically connected between theZener diode 516 and the ground end. In the level regulation circuit, the high-level voltage VCSH of the common signals can be generated from the output end of theoperational amplifier 511. The relationship between the common voltage VCOM and the high-level voltage VCSH can be represented as the following formula: -
VCSH=VCOM+V1×(R2/R1) (3); - according to formula (3), V1×(R2/R1) can be equal to ΔV by means of adjusting the resistance R1 and R2. In this way, the high-level voltage VCSH can be equal to (VCOM+ΔV). Since the
Zener diode 516 is operated at thebreakdown voltage 2 ΔV. The low-level voltage VCSL is generated by means of high-level voltage VCSH passing by the Zener diode 516 (VCSL=VCSH−2ΔV). Thus, the level regulation circuit of the present invention can generate the high-level voltage VCSH and the low-level voltage VCSL of the common signals by means of only one operational amplifier. - Please refer to
FIG. 7 .FIG. 7 is a circuit diagram illustrating the second embodiment of a level regulation circuit of the common signals according to the present invention. In the first embodiment shown inFIG. 6 , since the high-level voltage VCSH is varied with the reference voltage V1, the resistances of the resistors R1 and R2 have to be adjusted according to the voltage level of the reference voltage V1 for keeping high-level voltage VCSH equal to (VCOM+ΔV). In the second embodiment, the level regulation circuit can stably generate the high-level voltage VCSH equal to (VCOM+ΔV). In the second embodiment, the level regulation circuit comprises anoperational amplifier 531, tworesistors Zener diodes resistor 533 is R3. The resistance of theresistor 535 is R. The breakdown voltage of theZener diode 532 is ΔV. The breakdown voltage of theZener diode 534 is 2ΔV. Theresistor 533 is electrically connected between a positive input end of theoperational amplifier 531 and the reference voltage source V1. TheZener diode 532 is electrically connected between the positive input end of theoperational amplifier 531 and the common voltage source VCOM. A negative input end of theoperational amplifier 531 is electrically connected to an output end of theoperational amplifier 531. TheZener diode 534 is electrically connected to the output end of theoperational amplifier 531. Theresistor 535 is electrically connected between theZener diode 534 and the ground end. The voltage level of the reference voltage V1 must be higher than VCOM. In this way, even if the common voltage VCOM is varied, theZener diode 532 still can be operated at the breakdown voltage ΔV. In the level regulation circuit, the high-level voltage VCSH of the common signals can be generated from the output end of theoperational amplifier 531. The relationship between the common voltage VCOM and the high-level voltage VCSH can be represented as the following formula: -
VCSH=VCOM+ΔV (4); - the low-level voltage VCSL is generated to be equal to (VCOM−ΔV) by means of the high-level voltage VCSH passing by the
Zener diode 534. In the present embodiment, theoperational amplifier 531 forms a voltage follower. As a result, as long as the voltage on the positive input end of theoperational amplifier 531 is equal to (VCOM+ΔV), the voltage on the output end of theoperational amplifier 531 is equal to (VCOM+ΔV). - Please refer to
FIG. 8 .FIG. 8 is a circuit diagram illustrating a current amplifier. The current amplifier comprises anNPN transistor 611, aPNP transistor 612, and anoperational amplifier 613. TheNPN transistor 611 is electrically connected to the reference voltage source V1. ThePNP transistor 612 is electrically connected to the ground end. TheNPN transistor 611 and thePNP transistor 612 form an inverter. An output end of theoperational amplifier 613 is electrically connected to an input end of the inverter. A negative input end of theoperational amplifier 613 is electrically connected to an output end of the inverter. The high-level voltage VCSH and the low-level voltage VCSL generated by the level regulation circuit is inputted to a positive input end of theoperational amplifier 613. The current amplifier can increase the driving ability of the high-level voltage VCSH and the low-level voltage VCSL. - Please refer to
FIG. 9 .FIG. 9 is a circuit diagram illustrating a signal-outputting circuit. The signal-generating circuit comprises twoPMOS transistor NMOS transistor PMOS transistors NMOS transistors PMOS transistor 711 and theNMOS transistor 712 form a first inverter. ThePMOS transistor 713 and theNMOS transistor 714 form a second inverter. When a clock signal is inputted to the node A, the voltage level of the clock signal can be pulled up between the high-level voltage VCSH and the low-level voltage VCSL. Hence, the first common signal CSO is outputted from the node B, and the second common signal CSE is outputted from the node C. - In conclusion, the present invention provides a level regulation circuit of a common signal of an LCD generates a first level voltage and a second level voltage according to a common voltage so as to generate a first common signal and a second common signal. Each pixel of the LCD includes two storage capacitors receiving the first common signal and the second common signal respectively. The level regulation circuit of the common signal uses an operational amplifier and one or two Zener diodes to generate the first level voltage and the second level voltage. The first level voltage and the second level voltage have the same voltage difference to the common voltage, so the flicker of the LCD can be reduced.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Claims (10)
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TW098112817A TWI420479B (en) | 2009-04-17 | 2009-04-17 | Level regulation circuit of a common signal of an lcd |
TW98112817A | 2009-04-17 | ||
TW098112817 | 2009-04-17 |
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US20100265229A1 true US20100265229A1 (en) | 2010-10-21 |
US7825920B1 US7825920B1 (en) | 2010-11-02 |
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US12/536,468 Expired - Fee Related US7825920B1 (en) | 2009-04-17 | 2009-08-05 | Level regulation circuit of common signal of LCD |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US20120229441A1 (en) * | 2011-03-10 | 2012-09-13 | Chunghwa Picture Tubes, Ltd. | Liquid crystal display panel |
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TWI423729B (en) * | 2010-08-31 | 2014-01-11 | Au Optronics Corp | Source driver having amplifiers integrated therein |
TWI417833B (en) * | 2010-11-12 | 2013-12-01 | Au Optronics Corp | Driving method of half-source-driving (hsd) display device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5566064A (en) * | 1995-05-26 | 1996-10-15 | Apple Computer, Inc. | High efficiency supply for electroluminescent panels |
US5874828A (en) * | 1995-12-13 | 1999-02-23 | Samsung Electronics Co., Ltd. | Off-state voltage generating circuit capable of regulating the magnitude of the off-state voltage |
US20030197425A1 (en) * | 2001-12-05 | 2003-10-23 | Montante Charles J. | Dual input voltage adapter system and method |
US20080106538A1 (en) * | 2006-11-08 | 2008-05-08 | Chun-Seok Ko | Display device with improved gradation expression and driving method of the same |
US20080218149A1 (en) * | 2006-10-16 | 2008-09-11 | Yoshinori Aoki | Display device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200737711A (en) * | 2006-03-22 | 2007-10-01 | Ili Technology Corp | Level shifter circuit |
-
2009
- 2009-04-17 TW TW098112817A patent/TWI420479B/en not_active IP Right Cessation
- 2009-08-05 US US12/536,468 patent/US7825920B1/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5566064A (en) * | 1995-05-26 | 1996-10-15 | Apple Computer, Inc. | High efficiency supply for electroluminescent panels |
US5874828A (en) * | 1995-12-13 | 1999-02-23 | Samsung Electronics Co., Ltd. | Off-state voltage generating circuit capable of regulating the magnitude of the off-state voltage |
US20030197425A1 (en) * | 2001-12-05 | 2003-10-23 | Montante Charles J. | Dual input voltage adapter system and method |
US20080218149A1 (en) * | 2006-10-16 | 2008-09-11 | Yoshinori Aoki | Display device |
US20080106538A1 (en) * | 2006-11-08 | 2008-05-08 | Chun-Seok Ko | Display device with improved gradation expression and driving method of the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120229441A1 (en) * | 2011-03-10 | 2012-09-13 | Chunghwa Picture Tubes, Ltd. | Liquid crystal display panel |
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US7825920B1 (en) | 2010-11-02 |
TWI420479B (en) | 2013-12-21 |
TW201039321A (en) | 2010-11-01 |
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