JPH0876147A - Tft liquid crystal display - Google Patents

Abstract

PURPOSE: To provide a TFT liquid crystal display capable of lessening the heat generation of a semiconductor integrated circuit constituting a display controller. CONSTITUTION: This TFT liquid crystal display has a TFT liquid crystal display panel which has plural thin-film transistors(TFTs) disposed in a matrix form, common electrodes, liquid crystal disposed between the plural TFTs and the common electrodes, plural gate signal lines disposed in the row direction and plural drain signal lines disposed in the column direction, a gate driving circuit which drives the plural gate signal lines a drain driving circuit 211 which drives the plural drain signal lines, a common driving circuit which drives the common electrodes, a power source circuit and the display controller 201 to which the control signals from a computer section and data for display are inputted and which controls the respective circuits. In the liquid crystal display, buffer circuits 451 and 452 are inserted between the display controller 201 and at least either the driving circuit of the gate or the drain driving circuit 211.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a TFT (Thin Film Transi).
Stor) The present invention relates to a technology effectively applied to a liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, a TFT liquid crystal display module has been known as one of TFT liquid crystal displays.

FIG. 39 is a block diagram showing a schematic structure of the conventional TFT liquid crystal display module.

In FIG. 39, a liquid crystal display panel (TFT
-LCD) is composed of 640 × 3 × 480 pixels,
Drain drivers 511 are arranged above and below a liquid crystal display panel (TFT-LCD), and the drain drivers 511 above and below are alternately connected to the drain line (D) of the thin film transistor TFT, and a voltage for driving the liquid crystal is applied to the thin film transistor TFT. Supply.

The gate line (G) of the thin film transistor TFT is connected to a gate driver 506 arranged on the side surface of a liquid crystal display panel (TFT-LCD) to supply a voltage to the gate of the thin film transistor TFT for one horizontal operation time. .

A display control device 501 composed of one semiconductor integrated circuit (LSI) receives display data and a display control signal from a main computer, and drives a drain driver 511 and a gate driver 506 based on the display data and the display control signal. .

In this case, the display data from the main computer is in units of one pixel, that is, red (R), green (G),
Each data of blue (B) is made into one set and transferred every unit time.

Here, the display data is composed of 12 bits of 4 bits for each color or 18 bits of 6 bits for each color.

Further, since the drain driver 511 is arranged vertically, the output for driving the drain driver 511 from the display control device 501 has two systems for both the control signal and the display data bus.

FIG. 40 is a block diagram showing a schematic structure of a drain driver 511 of a conventional TFT liquid crystal display module.

As shown in FIG. 40, the drain driver 5
11 includes a data latch unit 551 for display data and an output voltage generation circuit 552.

The drain driver 51 shown in FIG.
In the case of 1, 6-bit display data and 9-value gradation reference voltage are input from the outside, and a 64-level output voltage value is obtained.

The data latch unit 551 takes in the display data as many as the number of outputs in synchronization with the display data latching clock signal (CL1), and the output voltage generating circuit 552 is generated from the gradation reference voltage input from the outside. The output voltage corresponding to the display data from the data latch unit 551 is selected from the output voltages of 64 gradations and is output to the drain signal line.

FIG. 41 shows an output voltage generation circuit 552 of the drain driver 511 of the conventional TFT liquid crystal display module.
2 is a diagram showing the circuit configuration of the above, and shows the circuit configuration of one circuit in the output voltage generation circuit provided for the total number of drain signal lines.

As shown in FIG. 41, the output voltage generating circuit includes a nine-value gradation reference voltage (V0 to V) input from the outside.
8) voltage values (VO0 to VO6) obtained by equally dividing the space
4) is generated, and the decoder 553 selects and outputs it.

FIG. 42 is a diagram showing the relationship between the gradation reference voltage and the output voltage in FIG.

In FIG. 42, a total of 65 output voltage values are obtained, of which the VO 64 equal to V 8 is not used.

[0018]

Generally, the AC power consumption of signals output from a semiconductor integrated circuit can be expressed by the following equation.

[0019]

## EQU1 ## p = fcv ₂ [w] where f: operating frequency [Hz], c: capacitance applied to the output terminal [F] v: potential difference [v] to be converted into alternating current Therefore, display control of the TFT liquid crystal display module If the number of terminals output from the device 501 increases or the output load capacity increases, the power consumption increases accordingly.

In the display control device 501 of the TFT liquid crystal display module, the power consumption (several hundreds) of AC generated at the output terminal for driving each driver is more than the power (several tens [mw]) consumed by the internal circuit. [Mw]) is larger.

A surface mount type synthetic resin mold package type LSI is used for the display control device 501 of the TFT liquid crystal display module, and the allowable power consumption of the surface mount type synthetic resin mold package type LSI is , About 500 [mw].

Further, the TFT liquid crystal display module is characterized by a sharpness and a response speed of the liquid crystal (rise speed + fall speed of about 50 [ns] or less). Therefore, higher performance such as higher resolution is desired.

However, increasing the number of gradations (colors) to be displayed, or increasing the drain driver 511 and the gate driver 506 which are driven in accordance with the increase in the number of display pixels, is a display control of the TFT liquid crystal display module. The power consumption generated at the output terminal of the device 501 is increased.

For example, when the drain driver 511 having 64 gradations (262144 colors) for each color is used for multi-gradation and the multi-bus driving is performed for high resolution driving,
In some cases, the allowable power consumption of the semiconductor integrated circuit (LSI) package is exceeded.

As a result, the semiconductor integrated circuit (LSI) package radiates a considerable amount of heat, and the semiconductor integrated circuit (LSI) is eventually destroyed.

It is an object of the present invention to provide a technique capable of reducing heat generation of a semiconductor integrated circuit which constitutes a display control device in a TFT liquid crystal display.

Further, as a common electrode driving method for the TFT liquid crystal display module, by adopting a common electrode alternating current driving method for alternating the voltage applied to the common electrode,
A low breakdown voltage drain driver can be used.

The above and other objects and novel constitution of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0029]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A plurality of pixels each having a pixel electrode and a thin film transistor provided in a matrix, a common electrode, a liquid crystal provided between the plurality of pixel electrodes and the common electrode, and a thin film transistor in a row direction. TF having a plurality of gate signal lines provided in the row direction to which the gate electrodes are connected and a plurality of drain signal lines provided in the column direction to which the drain electrodes of thin film transistors in the column direction are connected
In a TFT liquid crystal display including a T liquid crystal display panel, a gate drive circuit that drives the plurality of gate signal lines, a drain drive circuit that drives the plurality of drain signal lines, and a common electrode that drives the common electrode. A display control device that receives a control signal and display data from a computer section and controls each of the circuits, and includes at least one of the display control device and the gate drive circuit or the drain drive circuit. It is characterized in that a buffer circuit is inserted between the driving circuit and the driving circuit.

(2) A plurality of pixels each having a pixel electrode and a thin film transistor arranged in a matrix, a common electrode, a liquid crystal provided between the plurality of pixel electrodes and the common electrode, and a thin film transistor in a row direction. TF having a plurality of gate signal lines provided in the row direction to which the gate electrodes are connected and a plurality of drain signal lines provided in the column direction to which the drain electrodes of thin film transistors in the column direction are connected
In a TFT liquid crystal display including a T liquid crystal display panel, a gate drive circuit that drives the plurality of gate signal lines, a drain drive circuit that drives the plurality of drain signal lines, and a common electrode that drives the common electrode. A display circuit is provided with a drive circuit and a control signal and display data from a computer section for controlling each circuit, and the display control device is composed of a plurality of semiconductor integrated circuits. And

[0032]

According to the means of the first aspect, in the TFT liquid crystal display, a buffer circuit is inserted between the display control device and at least one drive circuit of the gate drive circuit and the drain drive circuit. Therefore, it is possible to disperse the power consumption of the semiconductor integrated circuit which constitutes the display control device, and thereby prevent the semiconductor integrated circuit which constitutes the display control device from being destroyed.

According to the means of the second item, in the TFT liquid crystal display, the display control device is composed of a plurality of semiconductor integrated circuits, so that the power consumption of the display control device can be dispersed. As a result, it is possible to prevent the semiconductor integrated circuit that constitutes the display control device from being destroyed.

[0034]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a TFT of a TFT liquid crystal display module which is an embodiment (Example 1) of a liquid crystal display device of the present invention.
FIG. 3 is a block diagram showing a liquid crystal display panel and circuits arranged around the liquid crystal display panel.

In the TFT liquid crystal display module of the first embodiment, the drain driver section 103 is arranged above the TFT liquid crystal display panel (TFT-LCD), and the side surface section of the TFT liquid crystal display panel (TFT-LCD) is provided. , Gate driver unit 104, controller unit 101, power supply unit 10
2 is placed.

The drain driver section 103, the gate driver section 104, the controller section 101 and the power source section 102.
Are mounted on their own printed circuit boards.

A liquid crystal display panel (TFT-LCD)
Is composed of 640 × 3 × 480 pixels.

FIG. 2 is a diagram showing an equivalent circuit of the TFT liquid crystal display panel (TFT-LCD) shown in FIG.

As shown in FIG. 2, the thin film transistor TF.
T is two adjacent drain signal lines (DiG, Di
B, ...) and two adjacent gate signal lines (G0, G
It is located in the intersection area with 1, ...).

Drain electrode of the thin film transistor TFT,
The gate electrodes are respectively drain signal lines (DiG, D
iB, ...) and gate signal lines (G0, G1, ...).

Since the source electrode of the thin film transistor TFT is connected to the pixel electrode and the liquid crystal layer is provided between the pixel electrode and the common electrode, the liquid crystal capacitance CLC is equivalently connected to the source electrode of the thin film transistor TFT. To be done.

The thin film transistor TFT becomes conductive when a positive bias voltage is applied to the gate electrode and becomes non-conductive when a negative bias voltage is applied to the gate electrode.

A storage capacitor CAD is provided between the source electrode of the thin film transistor TFT and the gate signal line of the previous line.
D is connected.

It should be understood that the source electrode and the drain electrode are originally determined by the bias polarity between them, and the polarity is reversed during operation in the circuit of this liquid crystal display device, so it should be understood that the source electrode and drain electrode are switched during operation. . However, in the following description, for convenience, one is fixed as the source electrode and the other is fixed as the drain electrode.

In this case, in order to prevent the other end of the storage capacitor CADD of the first gate line from being opened, the dummy gate signal line (G1) is provided outside the gate signal line (G1).
0) is provided, and the other end of the storage capacitance CADD of the first gate line is connected to the dummy gate signal line (G0).

In the equivalent circuit of one pixel of the TFT liquid crystal display panel (TFT-LCD) shown in FIG. 3, stray capacitances CGD and CGS exist between the drain and gate of the thin film transistor TFT and between the gate and source. To do.

Therefore, as shown in FIG. 4, a series circuit of the storage capacitance CADD and the gate-source floating capacitance CGS is connected between the gate signal lines.

However, since there is no gate signal line outside the gate signal line (Gend) of the final line, between the final gate signal line (Gend) and the other gate signal lines (G1 to Gend-1). The capacitance values of the capacitors connected to the gate signal lines are different.

In the TFT liquid crystal display module of the first embodiment, in order to make the capacitance values of the capacitors connected to the gate signal lines approximately the same, the final gate signal line (Gen)
A dummy gate signal line (Gend + 1) is provided outside d).

The normal gate signal lines (G1 to Gen)
d) Dummy gate signal lines (G0, Gen) provided on both sides of
d + 1) also has the effect of preventing static electricity from entering during the manufacturing process.

As is well known, the storage capacitor CADD serves to reduce the influence of the gate potential change on the pixel electrode potential when the thin film transistor (TFT) switches.

Further, the storage capacitor CADD also has the effect of prolonging the discharge time, and accumulates the image information after the thin film transistor TFT is turned off for a long time.

Further, as shown in FIG. 3, by providing the storage capacitor CADD between the pixel electrode and the gate signal line adjacent thereto, the structure of one pixel can be simplified, the area of the pixel electrode can be increased, and the aperture ratio can be increased. Can be improved.

FIG. 5 is a block diagram showing a schematic configuration of each driver (drain driver, gate driver, common driver) of the TFT liquid crystal display module of the first embodiment and a signal flow.

5, the display control device 201 and the buffer circuit 210 are provided in the controller section 101 shown in FIG. 1, the drain driver 211 is provided in the drain driver section 103 shown in FIG. 1, and the gate driver 206 is shown in FIG. The gate driver unit 104 is provided.

Like the drain driver 511 shown in FIG. 40, the drain driver 211 is composed of a data latch unit for display data and an output voltage generating circuit.

Further, the gradation reference voltage generator 208, multiplexer 209, common voltage generator 202, common driver 203, level shift circuit 207, gate-on voltage generator 204, gate-off voltage generator 205 and DC.
The DC converter 212 is provided in the power supply unit 102 shown in FIG.

As described in the prior art, in the conventional common electrode AC drive method, since a square wave is used as the AC waveform, a large peak current is generated in the common electrode driving transistor at the time of switching the phase. However, there is a problem in that a transistor having a large flow rate and a large rated value is required, and the drive circuit becomes large accordingly.

In order to solve the above problems, this embodiment 1
In the TFT liquid crystal display module of FIG. 5, the common voltage generation unit 202 shown in FIG. 5 converts the square wave alternating signal (M) into a trapezoidal alternating signal and applies a trapezoidal alternating drive voltage to the common electrode. are doing.

FIG. 6A is a circuit configuration of the common voltage generator 202 shown in FIG. 5, and FIG. 6B is a diagram showing input / output waveforms.

In the common voltage generating circuit 302 of FIG. 6A, when the high level of the square wave shown in FIG. 6B is applied to the AC signal input terminal of the operational amplifier OP1,
A current flows through the resistor R1 and the capacitor C1, and the capacitor C1 is charged, so that the operational amplifier OP
The output voltage of 1 gradually drops.

When the potential difference between both ends of the capacitor C1 exceeds the forward voltage of the diode D1 connected in parallel with the capacitor C1, the diode D1 becomes conductive, and the output voltage of the operational amplifier OP1 is on the low potential side. It becomes a constant voltage.

When the low level of the square wave shown in FIG. 6 (b) is applied to the AC signal input terminal of the operational amplifier, the capacitor C1 becomes the capacitor C1 and the resistor R1.
The output voltage of the operational amplifier OP1 gradually increases by being charged via the.

When the potential difference between both ends of the capacitor C1 exceeds the forward voltage of the diode D2 connected in parallel with the capacitor C1, the diode D2 conducts, and the output voltage of the operational amplifier OP1 is on the high potential side. It becomes a constant voltage.

As a result, as shown in FIG. 6B, a trapezoidal AC signal can be obtained from the output terminal of the operational amplifier.

The amplitude level of the trapezoidal wave can be changed by forming the diodes D1 or D2 by a plurality of unit diodes connected in series.

By inputting this trapezoidal wave AC signal to the common driver 203 and driving the common electrode with the trapezoidal wave AC drive voltage, the peak current of the driving transistor can be suppressed as shown in FIG. It is possible, and thereby, the drive circuit of the TFT liquid crystal display module can be downsized, and the outer size of the TFT liquid crystal display module can be reduced.

In the equivalent circuit shown in FIG. 3, the other end of the liquid crystal capacitance CLC is connected to the common electrode COM.

In the TFT liquid crystal display module of the first embodiment, since the common electrode is driven by the AC drive waveform, the gate signal line in the previous stage to which the other end of the storage capacitor CADD is connected is also the common electrode. The potential difference between both ends of the liquid crystal capacitor CLC cannot be kept constant unless the AC drive waveform having the same phase and amplitude as the applied AC drive waveform is added for driving.

Therefore, in the TFT liquid crystal display module of the first embodiment, as shown in FIG.
The AC signal from the signal No. 3 is input to the gate-on voltage generation unit 204 and the gate-off voltage generation unit 205 to generate the gate-on voltage and the gate-off voltage to which the common electrode AC drive waveform is added.

FIG. 8 is a diagram showing a circuit configuration of the gate-on voltage generation section 204 and the gate-off voltage generation section 205 in the TFT liquid crystal display module of the first embodiment.

In FIG. 8, the gate-on voltage generating circuit 3
Reference numeral 04 denotes a level shift circuit composed of a constant current source I1 and a Zener diode ZD1, and operational amplifiers OP2 and N2.
PN type transistor TR1 and PNP type transistor TR
And a buffer circuit composed of two, the output voltage of the common driver 203 is shifted by the level shift circuit, and the shifted voltage is amplified by the buffer circuit.

Further, the gate-off voltage generating circuit 305 is
The common driver 2 includes a level shift circuit including a constant current source I2 and a Zener diode ZD2, and a buffer circuit including an operational amplifier OP3, an NPN transistor TR3 and a PNP transistor TR4.
The output voltage of 03 is shifted by the level shift circuit, and the shifted voltage is amplified by the buffer circuit.

FIG. 9 shows the common voltage Vcom applied to the common electrode, the drain voltage applied to the drain, the on / off levels of the gate voltage applied to the gate electrode,
And the waveform is shown.

In FIG. 9, the drain waveform shows the drain waveform when black is displayed.

As shown in FIG. 9, the common voltage Vcom waveform, the gate voltage on-level waveform, and the gate voltage o
The ff level waveform has the same shape except for the direct current level. Therefore, the common voltage Vcom waveform, the on level waveform of the gate voltage, and the off level waveform of the gate voltage generate one waveform among them, and the other two waveforms can be obtained only by level shifting them. You can

In the first embodiment, the common voltage Vcom is first
A waveform is generated, and an on-level waveform of the gate voltage and an off-level waveform of the gate voltage are obtained by level-shifting the common voltage Vcom waveform.

In the method of generating the common voltage Vcom waveform, the gate voltage on level waveform, and the gate voltage off level waveform, the output from the common voltage generator 202 is the common driver 203, the gate on voltage generator 204, and the gate off voltage generator. There is also an orthodox method of inputting into the section 205.

However, according to the first embodiment, the gate-on voltage generation section 204 or the gate-off voltage generation section 205 shown in FIG. 5 can be configured by the simple circuit shown in FIG.
The mounting density of the liquid crystal display module is improved.

It is also possible to first generate an on-level waveform of the gate voltage or an off-level waveform of the gate voltage and shift the level thereof to obtain the common voltage Vcom waveform. In that case, the common driver 203 shown in FIG. 5 can be configured with a simple circuit, and the mounting density of the TFT liquid crystal display module is improved.

In the block diagram shown in FIG. 5, the common electrode AC drive waveform is added to both the gate-on voltage and the gate-off voltage. However, since the gate-on voltage is a DC voltage, the thin film transistor TFT can operate. In, the gate-on voltage generator 204 can be omitted.

By omitting the gate-on voltage generation section 204, the circuit structure is simplified, and as a result, the TFT
It is possible to reduce the size of the liquid crystal display module.

In FIG. 10, the common voltage V applied to the common electrode when the gate-on voltage generator 204 is omitted
com, the drain voltage applied to the drain, the on and off levels of the gate voltage applied to the gate electrode, and their waveforms.

As described above (see FIG. 2), the other end of the storage capacitor CADD on the first gate line is connected to the dummy gate signal line (G0).

The first dummy gate signal line (G0)
By applying a normal gate drive voltage (gate on level, gate off level) to the, the drive conditions can be made the same as those of the other gate signal lines.
The contrast of the pixels on the line can be improved.

Further, by applying a normal gate drive voltage (gate on level, gate off level) also to the final dummy gate signal line (Gend + 1), the drive conditions are made the same as those of the other gate signal lines. Therefore, it is possible to improve the contrast of the pixels on the final line.

As a publicly known example of applying a voltage waveform having the same phase and amplitude as the voltage applied to the common electrode to the gate signal line, Japanese Patent Laid-Open No. 5-297826 and U.S. Pat.
There are SP5,300,945.

However, the above-mentioned publicly known examples do not disclose the method of realizing the common electrode AC driving method in the liquid crystal panel of the type in which the storage capacitor is provided between the pixel electrode and the gate signal line adjacent to the pixel electrode of the present invention. It has not been.

FIG. 11 is a diagram showing a circuit configuration of a power supply section 102 of a TFT liquid crystal display module which is an embodiment (embodiment 2) of the liquid crystal display device of the present invention.

In the second embodiment, the gate-on voltage generator 2
04 is omitted.

In FIG. 11, the gray scale reference voltage generating section 208, the multiplexer 209, the common voltage generating section 202, the common driver 203, the level shift circuit 207, the gate-off voltage generating section 205 and the DC− in FIG.
The DC converter 212 is shown by a dotted frame.

In FIG. 11, the current mirror circuit CM
Corresponds to the constant current source I2 shown in FIG. 8, and the Zener diode ZD2 and the current mirror circuit CM form a level shift circuit.

The output voltage from the common driver 203 is
The level is shifted in the level shift circuit, and the level-shifted voltage is taken out as the gate off level.

Further, in FIG. 11, the frame signal (FLM) and the clock signal (CL3) are level-shifted by the level shift circuits (410, 420),
It is input to the buffer circuit 430.

Then, the frame signal (FLM ') and the clock signal (CL
3 ') is input to the gate driver.

However, if noise is superimposed on the positive power supply (VDG) for some reason, the buffer circuit 430 operates with the positive power supply (VDG) as a reference, and the buffer circuit 430 malfunctions, resulting in a TFT liquid crystal display module. Makes an erroneous display.

Therefore, in the circuit configuration shown in FIG. 11, the positive power supply (VDG) and the level shift circuit output (FL
The capacitor C2 is connected to M'or CL3 ').

The malfunction of the buffer circuit 430 will be described with reference to FIG.

Generally, in a TFT liquid crystal panel, as shown in FIG. 2, a large number of gate lines (G1, G2, ...) And drain lines (DiG, DiB, ...) Or common electrodes (CO).
M) is AC coupled by stray capacitance between lines or liquid crystal capacitance (CLC).

Therefore, even when the scan pulse is not input to the gate driver unit 104, another pulse (eg, display signal, etc.) is transmitted through the line capacitance or the liquid crystal capacitance (CLC) of the liquid crystal panel.
The common electrode drive pulse) enters the gate driver unit 104 as noise. Positive power supply for level shift circuit (VD
Since G) is also connected to the positive power supply of the gate driver unit 104, noise generated in the liquid crystal panel is superimposed on the positive power supply (VDG) of the level shift circuit.

In the differential amplifier type level shift circuit shown in FIG. 12A, when noise is superimposed on the positive power supply as shown in FIG. 12B, the level is changed when the capacitor C2 is not connected. Noise superimposed on the output terminal of the shift circuit from the positive power supply is
5 flows to the ground through the stray capacitance CCB between the collector and the base, the output voltage of the level shift circuit changes gently at the noise falling portion as shown by the solid line in FIG.

Therefore, considering the output voltage of the level shift circuit with reference to the positive power supply (VDG), FIG.
As shown in, the potential difference between the positive power supply and the output voltage of the level shift circuit becomes small at the noise falling portion, and a false pulse is generated, which causes the buffer circuit 43.
0 causes malfunction.

That is, C input to the power supply unit shown in FIG.
When L3 is low level, the false pulse is input to the gate driver instead of CL3. When the false pulse is applied to the gate driver, the gate driver performs a shift operation, resulting in erroneous display.

In the present embodiment, by connecting the capacitor C2 between the positive power source (VDG) and the output terminal of the level shift circuit, the noise having the same waveform as the noise superimposed on the positive power source (VDG) is generated. Since it is canceled by being superimposed on the output terminal of the level shift circuit through C2,
Considering the output voltage of the level shift circuit with reference to the positive power supply (VDG), the potential difference between the positive power supply (VDG) and the output voltage of the level shift circuit is a substantially constant potential difference as shown by the broken line in FIG. Becomes

As a result, no false pulse is generated as shown by the broken line in FIG. 12 (c), malfunction of the buffer circuit 430 can be prevented, and noise resistance can be improved.

If the value of the capacitor C2 is large, the function of the level shift circuit is lost, and if the value of C2 is small, the noise canceling effect is small. Therefore, the value of the capacitor C2 must be 20 to 100 pF. is there.

In the conventional TFT liquid crystal display module, the viewing angle is adjusted by changing the voltage applied to the drain signal line (D). However, in order to adjust the viewing angle, one pixel of the counter electrode of the liquid crystal is used. The voltage applied between the electrodes may be changed. Therefore, in the second embodiment, the voltage applied to the common electrode is changed in order to adjust the viewing angle.

Therefore, in the circuit configuration of the power supply section shown in FIG. 11, by connecting the variable resistors shown in FIG. 13 to the terminals VA1, VA2, VA3, the AC drive generated by the common voltage generation section 202 is performed. The amplitude of the waveform common voltage is changed.

As a result, the viewing angle of the TFT liquid crystal display module can be adjusted with a relatively simple circuit configuration, the driving circuit of the TFT liquid crystal display module can be simplified, and the external dimensions of the TFT liquid crystal display module can be reduced. It becomes possible to do.

Next, the gradation reference voltage generator 208 and the multiplexer 209 in the circuit configuration shown in FIG. 11 will be described.

As shown in FIG. 11, the gradation reference voltage generator 208 is composed of two voltage dividing circuits, and the outputs of the two voltage dividing circuits are input to the multiplexer 209.

The resistance series circuit of the two voltage dividing circuits is 1
The resistor series circuit that constitutes the second voltage dividing circuit is RB1, R
If B2 to RB10, the resistor series circuit forming the second voltage dividing circuit is RB10 and RB9 to RB1.
It is configured to have a relationship of.

Further, the multiplexer 209 switches the outputs from the two voltage dividing circuits according to the high level and the low level of the alternating signal (M) to change the gradation reference voltage (V0
~ V8) is output.

Now, it is assumed that the gray scale reference voltage of V7 is applied from the drain driver 211 to the drain electrode by the common driver 20.
Assuming that a low level common voltage (Vcom) is applied from 3 to the common electrode (COM), a high level is applied from the common driver 203 to the common electrode (COM) as the alternating signal (M) is inverted. Common voltage (Vcom) is applied.

In this case, the inverted display data is input to the drain driver 211, and the gradation reference voltage of V1 is applied to the drain electrode from the drain driver 211.

The reason why there are two resistor series circuits is that since the liquid crystal has a gamma characteristic as shown in FIG. 43, it is necessary to switch the gradation reference voltage applied to the drain driver 211 during forward rotation and during inversion. Is.

Further, the common driver 203 shown in FIG.
The semi-fixed resistor VR connected to the inverting input terminal of the operational amplifier OP4 is for adjusting the DC level of the common signal voltage (Vcom).

Next, a TFT liquid crystal display module which is another embodiment (embodiment 3) of the liquid crystal display device of the present invention will be described.

The TFT liquid crystal display module of the third embodiment is designed so that good gradation display can be performed.

FIG. 14 shows the circuit configuration of the output voltage generation circuit of the drain driver 211 of the TFT liquid crystal display module of the third embodiment, and among the output voltage generation circuits provided for the total number of drain signal lines (D). The circuit configuration for one circuit is shown.

The construction of the drain driver 211 of the TFT liquid crystal display module of the third embodiment is the same as that of the drain driver 511 shown in FIG. 40, and comprises a data latch portion for display data and an output voltage generating circuit. To be done.

In general, as shown in FIG. 43, the applied voltage-transmittance characteristic of the liquid crystal exhibits remarkable non-linear characteristics at both ends of the working voltage range and relatively linear characteristics at the central part.

Therefore, in the output voltage generation circuit of the drain driver 211 of the TFT liquid crystal display module of the third embodiment, the number of voltage values to be interpolated between the gradation reference voltages from the outside is set at both ends of the working voltage range. To reduce the number and increase it in the central portion, each of the nine-valued gradation reference voltages (V0 to V8) input from the outside is divided into 16 equal parts, and the working voltage at which the liquid crystal voltage-transmittance characteristic shows a non-linear characteristic. At the two ends of the range, the three most appropriate points out of 16 equal parts, or
The decoder selects 7 voltages, and the decoder 253 selects 16 equally divided voltages in the central portion of the operating voltage range where the voltage-transmittance characteristic of the liquid crystal shows a relatively linear characteristic. Is.

Therefore, in the output voltage generation circuit of the drain driver of the TFT liquid crystal display module of the third embodiment, the number of gray scales embedded between the gray scale reference voltages is in order.
It becomes 3,3,7,15,15,7,3,3.

Further, in the third embodiment, as in the second embodiment, as shown in FIG.
In the gradation reference voltage generation unit 208, the 9-value gradation reference voltage (V0 to V8) is used at both ends of the working voltage range in which the voltage-transmittance characteristic of the liquid crystal shows a non-linear characteristic. Gradation reference voltage (V0-V1, V1-V2, V2-
V3, V5-V6, V6-V7, V7-V8) have a small potential difference, and the voltage-transmittance characteristic of the liquid crystal shows a relatively linear characteristic. The gray-scale reference voltage (V3-
V4, V4-V5) generates a gradation reference voltage that increases the potential difference.

FIG. 15 is a diagram showing the relationship between each gradation reference voltage and the output voltage in FIG.

In FIG. 15, a total of 65 output voltage values are obtained, but of these, the VO64 equal to V8 is not used.

FIG. 16 is a table showing the correspondence between the decoder input and the decoder output in FIG.

As described above, the TFT of the third embodiment
Grayscale reference voltage generator 208 in liquid crystal display module
If the output voltage generator of the drain driver 211 is used, the number of gradation reference voltages that can be arbitrarily set from the outside can be increased at both ends of the operating voltage range in which the nonlinear characteristic of the applied voltage-transmittance characteristic of the liquid crystal is remarkable. The “deviation” between the originally desirable gradation voltage and the gradation voltage generated inside the drain driver can be reduced.

However, the applied voltage-transmittance characteristic of the liquid crystal is
In the central portion of the operating voltage range showing the linear characteristic, the number of gradation reference voltages that can be arbitrarily set from the outside decreases, and the number of gradation voltages generated inside the drain driver 211 increases.

However, the central part of the operating voltage range is
Since the applied voltage-transmittance characteristic of the liquid crystal exhibits a relatively linear characteristic, the “deviation” between the desired grayscale voltage and the grayscale voltage generated inside the drain driver 211 does not become too large, which is a big problem. There is no.

As a result, it is possible to obtain a gamma correction voltage that matches the voltage-luminance characteristics of the liquid crystal, and it is possible to obtain better gradation display characteristics.

Moreover, since it is not necessary to increase the number of gradation reference voltage values input from the outside, and it is not necessary to increase the number of peripheral circuits, there is no increase in cost and mounting area due to increase in peripheral circuit parts. .

In the TFT liquid crystal display module of the first embodiment, as shown in FIG.
Is arranged only above the liquid crystal display panel (TFT-LCD).

FIG. 17 is a diagram showing the flow of display data and clock signals for the drain driver 211 in the TFT liquid crystal display module of the first embodiment.

The carry output of the previous stage of the drain driver 211 is directly input to the carry input of the drain driver 211 of the next stage.

The carry signal controls the latch operation of the data latch unit 551 of the drain driver 211 to prevent erroneous display data from being written in the data latch unit 551.

The display control unit 201 has a role of an interface with the main computer, and drives the drain driver 211 and the gate driver 206 based on the control signal, the clock and the display data transmitted from the main computer. To do.

In the display control device 201 in the TFT liquid crystal display module of the first embodiment, the simple one-column display data transmitted from the main computer is input to the drain driver 211.

FIG. 18 shows a display controller 20 shown in FIG.
2 is a block diagram showing a schematic configuration of 1.

FIG. 19 shows a display controller 20 shown in FIG.
It is a figure which shows the timing chart of 1.

In the TFT liquid crystal display module of the first embodiment, the display control device 201 is composed of a data processing section 221 and a control signal processing / generating section 222, and the control signal processing / generating section 222 is a main computer. The control signal (clock, display timing signal, synchronization signal) is received and a control signal to the data processing unit 221 and each liquid crystal driver (drain driver 211, gate driver 206) is generated.

The control signal processing / generating section 222 comprises a drain driver driving circuit 224, a gate driver driving circuit 223, and an output clock generating circuit 225,
The output clock generation circuit 225 generates a data output clock and a shift clock (CL2) to the drain driver 211.

The data processing section 221 comprises a D-type flip-flop 226, a logic processing circuit 227, and a D-type flip-flop 228, which are connected in cascade, receives display data from the main computer, and processes / generates control signals. The drain driver 2 based on the clock signal from the unit 222
The display data is output to 11.

Logic processing circuit 227 of data processing unit 221
Is inserted to invert the display data,
It can be configured with the multiplexer shown in FIG.

Inversion and non-inversion of display data can be controlled by a signal given to Select.

The logic processing circuit 227 is not necessary if the display data need not be inverted.

The necessity of inverting the display data depends on the specifications of the drain driver 211.

As is apparent from FIG. 19, the shift clock and output data of the drain driver have the same frequency as the clock signal and display data input from the main computer, and have the same frequency as the clock signal from the main computer. The display data taken in by the D-type flip-flop 226 by the clock signal is output from the D-type flip-flop 228 to the data bus by the clock signal, and the simple 1-column display data transmitted from the main computer is converted into the data. Output to the bus.

As described above, according to the first embodiment, in the TFT liquid crystal display module, the drain driver is arranged on one of the upper and lower sides of the liquid crystal display panel, so that the area of the frame of the liquid crystal display panel is increased. Can be made smaller, which allows the display area to be larger than the external dimensions of the liquid crystal display device.

Further, in the TFT liquid crystal display module of the first embodiment, the buffer circuit 210 is provided between the display control device 201 and the drain driver 211 as shown in FIG.
Has been inserted.

FIG. 21 is a block diagram showing a schematic configuration of a buffer circuit of a TFT liquid crystal display module which is another embodiment (embodiment 4) of the liquid crystal display device of the present invention.

In the case of the first embodiment, the buffer circuit 21
All drain drivers 211 are driven by one system clock signal from 0.

In this case, when the number of drain drivers 211 increases, the buffer circuit 210 may not be able to drive the drain drivers 211, and a stable clock signal may not be supplied.

Therefore, in the TFT liquid crystal display module of the fourth embodiment, the clock signal is divided into two systems, and the two system clock signals are supplied from independent buffer circuits (451, 452). Is.

As a result, a stable clock signal can be supplied even when the number of drain drivers 211 serving as loads increases.

In each of the above-described embodiments, the actual liquid crystal drive circuit is constructed by using dedicated LSIs and ICs, respectively.

FIG. 22 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (fifth embodiment) of the liquid crystal display device of the present invention.

In FIG. 22, the difference from FIG. 39 is the display control device 201 of the TFT liquid crystal display module.
Between the LCD driver (drain driver 211) and
This is because the buffer circuits (451, 452) are inserted.

As a result, the buffer circuit (451, 452) drives the liquid crystal driver (drain driver 211), which has been borne by the display control device 201 of the conventional TFT liquid crystal display module.

This buffer circuit (451, 452) is
Depending on the number of output terminals to be driven, a plurality of semiconductor integrated circuits can be used.

As a result, the power consumption of the display control device 201, that is, the heat generation, can be distributed to the buffer circuits (451, 452).

Then, the wiring capacitance from the display control device 201 to the buffer circuits (451, 452) (about 20 [p
F]), the wiring capacitance from the buffer circuit (451, 452) to the liquid crystal driver group (drain driver 211, gate driver 206) (about 100 [pF] or more, depending on the number of driver ICs connected). Has a large effect that the power consumption of the display control device 201 is distributed to the respective buffer circuits (451, 452).

Further, in the above embodiment, the drain driver 2
11 between the display control device 201 and the display control device 201.
Although the description has been given by taking the example of providing 52, the gate driver 2
A buffer may be provided between the display control device 201 and the display control device 201 (not shown), which has an effect of suppressing heat generation of the display control device 201.

When the parts are mounted on the printed circuit board, the display control device 201 and the buffer circuit (451, 45).
Since the wiring capacitance is reduced as much as possible to 2), the power consumption of the display control device 201 can be suppressed.

In the TFT liquid crystal display module of the fifth embodiment, it is not necessary to intentionally develop the buffer circuit (451, 452) as a custom semiconductor integrated circuit, and it can be realized by a standard semiconductor integrated circuit.

Further, in the TFT liquid crystal display module of the fifth embodiment, the buffer circuits (451, 452) are provided with
Although the non-inverting circuit element is used, an inverting circuit element (inverter) or a flip-flop circuit can be used depending on the circuit configuration.

However, in the TFT liquid crystal display module of the fifth embodiment, since the buffer circuit (451, 452) is added, the total area of the mounted semiconductor integrated circuits increases and the display control device 201. Therefore, the power consumption for driving the buffer circuits (451, 452) is increased as a whole.

In the display control device 201, when driving the drain driver 211, the number of outputs from the display data bus is larger than that from the control signal.

As the display gradation increases, the number of data outputs from the display control device 201 also increases accordingly.

Therefore, the display control device 201 can be divided into the data processing unit 221 and the control signal processing / generating unit 222 to further reduce the power consumption.

FIG. 23 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (embodiment 6) of the liquid crystal display device of the present invention.

The sixth embodiment is an embodiment in which the display control device 201 is divided into a data processing unit 221 and a control signal processing / generating unit 222.

FIG. 24 is a diagram showing a circuit configuration of the data processing unit shown in FIG.

FIG. 25 is a diagram showing a timing chart of the data processing unit shown in FIG.

In FIG. 23, the control signal processing / generating section 2
30 is a control signal (clock,
Upon receiving the display timing signal and the synchronization signal, the data processing units (231, 232) and the respective liquid crystal drivers (drain driver 211, gate driver 20 not shown)
The control signal of 6) is generated.

FIG. 24 shows the data processing unit (231,
232) showing the multiplexer 233 and the clock C.
The D-type flip-flop 234 to which K1 is input and the D-type flip-flop 235 to which the clock CK2 is input are connected in cascade, receive display data from the main body computer, and receive from the control signal processing / generating unit 230. The display data is output to the drain driver 211 based on the clock signal.

The multiplexer 233 is the same as the logic circuit shown in FIG. 20 and has a signal SEL applied to Select.
Controls the inversion or non-inversion of the display data.

As is clear from the timing chart shown in FIG. 25, the clock signal (CK2) input to the upper data processing unit 231 and the clock signal (CK2 ') input to the lower data processing unit 232. Has a phase of 18
0 ° different, and the clock signal (CK2) is
2 of the clock signal (clock) from the main body computer
It has a double cycle.

As a result, in the upper and lower data processing sections (231, 232), the clock signal (CK1) having the same frequency as the clock signal from the main body computer.
Thus, the display data fetched by the D-type flip-flop 234 is stored in the D-type flip-flop 235 of the upper data processing unit 231 by the clock signal (CK2) every other display data (a, c, e ... ) Is fetched and output to the upper data bus, and similarly, in the D-type flip-flop 235 of the lower data processing unit 232, every other display data (b, d, f ...) Is generated by the clock signal (CK2). ) Is captured and output to the lower data bus.

The display data is made up of 18 bits, 6 bits for each color.

In the TFT liquid crystal display module of the sixth embodiment, since the data processing units (231, 232) also drive the drain driver 211, the display controller 20
The total power consumption of 1 is the same as the conventional example.

Further, since the control signal processing / generating section 230 does not need to perform data processing, the package size of the conventional display control device 201 is 100 to 150.
In contrast to the number of terminals, the TFT liquid crystal display module of the sixth embodiment can be realized with 50 or less terminals.

Although the multiplexer 233 is inserted in the TFT liquid crystal display module of the sixth embodiment,
This is because the IC used for the drain driver 211 needs to invert the data in accordance with the AC cycle of the voltage applied to the liquid crystal.

If data inversion is not necessary and data can be taken in only once, a standard semiconductor integrated circuit can be used for this data processing unit (231, 232).

FIG. 26 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (embodiment 7) of the liquid crystal display device of the present invention.

The seventh embodiment is an embodiment of the TFT liquid crystal display module in which the display data from the main body computer in the sixth embodiment is input to the upper and lower data processing units in parallel with two pixels. This is an example corresponding to a fine TFT liquid crystal display module.

FIG. 27 is a diagram showing a timing chart of the data processing unit shown in FIG.

In the TFT liquid crystal display module of the seventh embodiment, as is clear from the timing chart of FIG.
Since the display data from the main body computer is input to the upper and lower data processing units (231, 232) in parallel with two pixels, the clock signal (CK1) and the clock signal (CK2) are transmitted from the main body computer. It has the same frequency as the clock signal (Clock).

As a result, in the upper and lower data processing sections (231, 232), the clock signal (CK1) having the same frequency as the clock signal from the main body computer.
Thus, the display data taken into the D-type flip-flop 234 is the display data (A, B, C ...) And (a, b) input in parallel by the clock signal (CK2) from the D-type flip-flop 235. , C ...) are output to the upper and lower data buses.

Further, the TF of the sixth embodiment and the seventh embodiment
In the T liquid crystal display module, the data processing unit (23
1, 232) can be composed of a plurality of semiconductor integrated circuits, and further control signal processing / generating section 230 so as to cope with more gradations such as 256 gradations and higher definition.
With the above configuration, it is not necessary to newly develop the control signal processing / generating unit 230 when realizing multi-gradation.

Further, in this semiconductor integrated circuit, since heat generation is suppressed as described above, TSOP (Thin
It can also be realized by a semiconductor integrated circuit in a small package such as a Small Outline Package).

As described above, the TF of each of the above embodiments
In the T liquid crystal display module, the display control device 201 in the conventional TFT liquid crystal display module is configured by a plurality of semiconductor integrated circuits, or the function is configured by a plurality of semiconductor integrated circuits, so that the power consumption is dispersed. It is possible to

Further, as shown in FIG. 28, in the TFT liquid crystal display module of each of the embodiments, the display control device 2
Printed circuit board (interface board) on which 01 is mounted
The I / F (interface) connector is provided with a specific terminal, and a signal voltage desired to be monitored among various signal voltages of the power supply unit 102 of the TFT liquid crystal display module from the specific terminal, for example, the DC level of the common signal voltage, the common It is also possible to extract the amplitude level of the signal voltage, the DC level of the gate-on and gate-off signal voltages, the amplitude level of the gate-on and gate-off signal voltages, the gradation voltage, and the like.

Thereby, by inserting the I / F connector,
Various signal voltages of the power supply unit 102 of the TFT liquid crystal display module can be monitored, which simplifies the adjustment work of the adjustment portion during the manufacturing process and the final inspection process, and reduces the work process.

Further, as shown in FIG. 28, in the TFT liquid crystal display module of each of the embodiments, a specific terminal of the I / F connector is connected to a specific portion of the drive circuit of the TFT liquid crystal display module, for example, in FIG. The DC level of the common signal voltage can be adjusted from the outside by connecting to the inverting input terminal of the operational amplifier OP4 of the common driver 203 shown and applying a voltage from the outside.

Thereby, by inserting the I / F connector,
A regulation voltage can be applied from the outside, which allows
For the test of the drive circuit of the TFT liquid crystal display module, TF
It can be easily performed from the outside without disassembling the T liquid crystal display module.

Further, in the TFT liquid crystal display module of each of the above embodiments, the display data for each color is composed of 6 bits and 64 gradations can be displayed, whereas the display data transmitted from the main computer is Is assumed to be less than 6 bits for each color, for example, 4 bits for each color.

In this case, it is necessary to convert 4-bit display data for each color from the main computer side into 6-bit display data for each color.

Therefore, the present invention proposes the optimum digital-digital conversion method in the above case, as shown in FIG.

In FIG. 29 (a), the output 4 bits indicate the display data of 4 bits for each color outputted from the main body computer, and the input 6 bits indicate the TFT liquid crystal panel (TFT-LCD) in each of the above embodiments. 6-bit display data for each color input to the drain driver 211 of FIG.

In the digital-to-digital conversion method shown in FIG. 29 (a), the 4-bit display data from the main body computer side is used as it is for the TFT liquid crystal panel (TF).
6 input to the drain driver 211 of the T-LCD)
The upper 2 bits of the 4 bits from the main body computer side are used as the display data of the upper 4 bits of the bit, and the lower 2 bits without 6-bit input data input to the drain driver 211 of the TFT liquid crystal panel (TFT-LCD) I am trying to enter the data.

FIG. 30 shows the digital signal shown in FIG.
A bit string converted from 4 bits to 6 bits by a digital conversion method is shown.

As is apparent from FIG. 30, FIG. 29 (a)
According to the digital-to-digital conversion method shown in FIG.
A bit string is obtained by thinning out up to gh (1,1,1,1,1,1,1) with an optimum width.

As a result, the digital-to-digital conversion method shown in FIG. 29A can display 100% of white or black, as compared with the conventional method of fixing the low-order bits lacking in the display data to Low or High. At the same time, linear gradation display is possible.

In the digital-to-digital conversion method shown in FIG. 29, the case of converting from 4 bits to 6 bits has been described as an example, but the invention is not limited to this.

For example, if a 3-bit computer output is 6
When converting to bits and inputting to the liquid crystal module, linear gradation display can be performed by using the circuit shown in FIG. When converting a 2-bit computer output to a 6-bit signal and inputting it to the liquid crystal module, the circuit shown in FIG. 29C may be used.

FIGS. 31 to 38 are views showing a TFT liquid crystal display module which is another embodiment (Embodiment 8) of the present invention, including a connecting portion between each IC and an I / F connector. It is a figure which shows, and is a figure which shows the circuit structure of an actual liquid crystal drive circuit.

31 and 32 show the controller unit 101 shown in FIG. 1, FIGS. 33 and 34 show the drain driver unit 103 shown in FIG. 1, and FIGS. 35 and 36 show the gate driver unit 104 shown in FIG. 37 and 38 show the power supply unit 102 shown in FIG.

The eighth embodiment partially includes the above respective embodiments. For example, in FIG. 31 and FIG. 32, the display control device 201 is composed of one LSI, and the display control device 201 and Buffer circuits (IC2, IC3, IC4) are inserted between the drain driver 211 and the drain driver 211.

Further, the clock signal (CL2) is divided into two systems and supplied to every other drain driver IC from independent buffer circuits inside the IC3.

The I / F connector 15 to 15 shown in FIG.
Reference numeral 17 is a terminal for connecting a diopter adjustment resistor as shown in FIG. 13, and the I / F connector 18 is connected to the non-inverting terminal of the operational amplifier OP4 shown in FIG.
The DC level of the common signal voltage and the amplitude level of the common signal voltage are monitored or the DC level of the common signal voltage is externally adjusted by applying a voltage from the outside.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0216]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In the TFT liquid crystal display, since the buffer circuit is inserted between the display control device and at least one of the gate drive circuit and the drain drive circuit, the display control device is constructed. It is possible to disperse the power consumption of the semiconductor integrated circuit, thereby preventing the semiconductor integrated circuit constituting the display control device from being destroyed.

(2) In the TFT liquid crystal display, since the display control device is composed of a plurality of semiconductor integrated circuits, the power consumption of the display control device can be dispersed, and thus the display control device is configured. It is possible to prevent the breakdown of the semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a TFT liquid crystal display panel of a TFT liquid crystal display module which is an embodiment (embodiment 1) of a liquid crystal display device of the present invention and circuits arranged in the periphery thereof.

2 is a TFT liquid crystal display panel (TFT-L shown in FIG.
It is a figure which shows the equivalent circuit of (CD).

FIG. 3 is a TFT liquid crystal display panel (TFT-L shown in FIG.
It is a figure which shows the equivalent circuit of 1 pixel of (CD).

FIG. 4 is a TFT liquid crystal display panel (TFT-L shown in FIG.
It is a figure which shows the capacity | capacitance connected to each gate signal line of the equivalent circuit of 1 pixel of (CD).

FIG. 5 is a block diagram showing a schematic configuration of each driver of the TFT liquid crystal display module of the first embodiment and a signal flow.

6 is a diagram showing a circuit configuration of a common voltage generation unit shown in FIG. 5 and an input / output waveform.

FIG. 7 is a diagram showing that the peak current of the driving transistor can be suppressed by driving the common electrode with a trapezoidal wave AC driving voltage.

FIG. 8 is a diagram showing a circuit configuration of a gate-on voltage generation unit and a gate-off voltage generation unit in the TFT liquid crystal display module of the first embodiment.

FIG. 9 is a diagram showing a common voltage applied to a common electrode, a drain voltage applied to a drain, a level of a gate voltage applied to a gate electrode, and waveforms thereof in the first embodiment.

FIG. 10 is a diagram showing a common voltage applied to the common electrode, a drain voltage applied to the drain, a level of the gate voltage applied to the gate electrode, and It is a figure which shows the waveform.

FIG. 11 is an example (Example 2) of the liquid crystal display device of the present invention.
It is a figure which shows the circuit structure of the power supply part of the TFT liquid crystal display module which is.

12 is a diagram for explaining a malfunction of the buffer circuit 430 in FIG.

13 is a diagram showing a resistor network connected to terminals VA1, VA2, VA3 in order to change the amplitude of the common voltage of the trapezoidal wave generated by the common voltage generator in the circuit configuration shown in FIG. .

FIG. 14 is a diagram showing a circuit configuration of an output voltage generation circuit of the drain driver of the TFT liquid crystal display module of the third embodiment.

FIG. 15 is a diagram showing a relationship between each gradation reference voltage and an output voltage in FIG.

16 is a table showing a correspondence relationship between the decoder input and the decoder output in FIG.

FIG. 17 is a diagram showing the flow of display data and clock signals for the drain driver in the TFT liquid crystal display module of the first embodiment.

FIG. 18 is a block diagram showing a schematic configuration of the display control device shown in FIG. 17.

19 is a diagram showing a timing chart of the display control device shown in FIG.

20 is a diagram showing a circuit configuration of the logic processing circuit shown in FIG.

FIG. 21 is a block diagram showing a schematic configuration of a buffer circuit of a TFT liquid crystal display module which is another embodiment (embodiment 4) of the liquid crystal display device of the present invention.

FIG. 22 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (embodiment 5) of the liquid crystal display device of the present invention.

FIG. 23 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (embodiment 6) of the liquid crystal display device of the present invention.

FIG. 24 is a diagram showing a circuit configuration of a data processing unit shown in FIG. 23.

25 is a diagram showing a timing chart of the data processing unit shown in FIG. 23.

FIG. 26 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (embodiment 7) of the liquid crystal display device of the present invention.

FIG. 27 is a diagram showing a timing chart of the data processing unit shown in FIG. 26.

FIG. 28 is a diagram for explaining that a specific terminal can be provided on the I / F connector and a drive circuit inside the TFT liquid crystal display module can be adjusted from the specific terminal.

FIG. 29 is a diagram for explaining the digital-digital conversion method of the present invention.

30 is a table showing a bit string converted from 4 bits to 6 bits by the digital-digital conversion method shown in FIG.

FIG. 31 is a TF that is another embodiment (Embodiment 8) of the present invention.
It is a diagram showing a T liquid crystal display module, each IC and I / F
It is a figure including a connection part with a connector, and is a figure showing the circuit composition of an actual liquid crystal drive circuit.

32 is a TF that is another embodiment (Embodiment 8) of the present invention. FIG.
It is a diagram showing a T liquid crystal display module, each IC and I / F
It is a figure including a connection part with a connector, and is a figure showing the circuit composition of an actual liquid crystal drive circuit.

FIG. 33 is a TF that is another embodiment (Embodiment 8) of the present invention.
It is a diagram showing a T liquid crystal display module, each IC and I / F
It is a figure including a connection part with a connector, and is a figure showing the circuit composition of an actual liquid crystal drive circuit.

FIG. 34 is a TF that is another embodiment (Embodiment 8) of the present invention.
It is a diagram showing a T liquid crystal display module, each IC and I / F
It is a figure including a connection part with a connector, and is a figure showing the circuit composition of an actual liquid crystal drive circuit.

FIG. 35 is a TF that is another embodiment (Embodiment 8) of the present invention.
It is a diagram showing a T liquid crystal display module, each IC and I / F
It is a figure including a connection part with a connector, and is a figure showing the circuit composition of an actual liquid crystal drive circuit.

FIG. 36 is a TF which is another embodiment (Embodiment 8) of the present invention.
It is a diagram showing a T liquid crystal display module, each IC and I / F
It is a figure including a connection part with a connector, and is a figure showing the circuit composition of an actual liquid crystal drive circuit.

FIG. 37 is a TF that is another embodiment (Embodiment 8) of the present invention.
It is a diagram showing a T liquid crystal display module, each IC and I / F
It is a figure including a connection part with a connector, and is a figure showing the circuit composition of an actual liquid crystal drive circuit.

FIG. 38 is a TF that is another embodiment (Embodiment 8) of the present invention.
It is a diagram showing a T liquid crystal display module, each IC and I / F
It is a figure including a connection part with a connector, and is a figure showing the circuit composition of an actual liquid crystal drive circuit.

FIG. 39 is a block diagram showing a schematic configuration of a conventional TFT liquid crystal display module.

FIG. 40 is a block diagram showing a schematic configuration of a drain driver of a conventional TFT liquid crystal display module.

FIG. 41 is a diagram showing a circuit configuration of an output voltage generation circuit of a drain driver of a conventional TFT liquid crystal display module.

42 is a diagram showing the relationship between the gradation reference voltage and the output voltage in FIG. 41.

FIG. 43 is a diagram showing an applied voltage-transmittance characteristic of a typical liquid crystal.

[Explanation of symbols]

TFT-LCD ... TFT liquid crystal display panel, TR1 to TR
5 ... Transistors, OP1 to OP4 ... Operational amplifiers, 10
DESCRIPTION OF SYMBOLS 1 ... Controller part, 102 ... Power supply part, 103 ... Drain driver part, 104 ... Gate driver part, 201, 5
01 ... Display control device, 202 ... Common voltage generation unit, 20
3 ... Common driver, 204 ... Gate-on voltage generation unit,
205 ... Gate-off voltage generator, 206, 506 ... Gate driver, 207 ... Level shift circuit, 208 ... Grayscale reference voltage generator, 209, 233 ... Multiplexer, 2
10, 430, 451 and 452 ... Buffer circuit, 21
1, 511 ... Drain driver, 212 ... DC-DC converter, 221 ... Data processing unit, 222, 230 ... Control signal processing / generating unit, 223 ... Gate driver driving circuit, 224 ... Drain driver driving circuit, 225 ... Output clock generation Circuits, 226, 228, 234, 235 ...
D-type flip-flop 227 ... Logic processing circuit 231
... upper data processing unit, 232 ... lower data processing unit,
253, 553 ... Decoder, 302 ... Common voltage generating circuit, 304 ... Gate-on voltage generating circuit, 305 ... Gate-off voltage generating circuit, 410, 420 ... Level shift circuit, 551 ... Data latch section, 552 ... Output voltage generating circuit.

Claims (2)

[Claims] 1. A plurality of pixels each having a pixel electrode and a thin film transistor provided in a matrix, a common electrode, a liquid crystal provided between the plurality of pixel electrodes and the common electrode, and a gate of the thin film transistor in a row direction. TFT having a plurality of gate signal lines provided in the row direction to which electrodes are connected and a plurality of drain signal lines provided in the column direction to which the drain electrodes of thin film transistors in the column direction are connected
Liquid crystal display panel, gate drive circuit for driving the plurality of gate signal lines, drain drive circuit for driving the plurality of drain signal lines, common electrode drive circuit for driving the common electrode, and control from computer section A signal and display data are input, and a display control device that controls each of the circuits is provided, and between the display control device and at least one drive circuit of the gate drive circuit or the drain drive circuit,
A TFT liquid crystal display having a buffer circuit inserted therein. 2. A plurality of pixels each having a pixel electrode and a thin film transistor arranged in a matrix, a common electrode, a liquid crystal provided between the plurality of pixel electrodes and the common electrode, and a gate of the thin film transistor in a row direction. TFT having a plurality of gate signal lines provided in the row direction to which electrodes are connected and a plurality of drain signal lines provided in the column direction to which the drain electrodes of thin film transistors in the column direction are connected
Liquid crystal display panel, gate drive circuit for driving the plurality of gate signal lines, drain drive circuit for driving the plurality of drain signal lines, common electrode drive circuit for driving the common electrode, and control from computer section A TFT liquid crystal display, comprising: a display control device that receives signals and display data and controls each of the circuits, wherein the display control device includes a plurality of semiconductor integrated circuits.