JP3837153B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a technique effective when applied to a TFT (Thin Film Transistor) liquid crystal display.

  Conventionally, a TFT liquid crystal display module is known as one of TFT liquid crystal displays.

  FIG. 39 is a block diagram showing a schematic configuration of the conventional TFT liquid crystal display module.

  In FIG. 39, the liquid crystal display panel (LCD) is composed of 640 × 3 × 480 pixels, drain drivers 511 are arranged above and below the liquid crystal display panel (LCD), and the upper and lower drain drivers 511 are alternately arranged as thin film transistors TFT. Connected to the drain line (D), a voltage for driving the liquid crystal is supplied to the thin film transistor TFT.

  A gate driver 506 disposed on the side surface of the liquid crystal display panel (LCD) is connected to the gate line (G) of the thin film transistor TFT to supply a voltage to the gate of the thin film transistor TFT for one horizontal operation time.

  A display control device 501 composed of one semiconductor integrated circuit (LSI) receives display data and a display control signal from the main body computer, and drives the drain driver 511 and the gate driver 506 based on the data.

  In this case, display data from the main computer is transferred in units of one pixel, that is, each data of red (R), green (G), and blue (B) is made into one set.

  Here, the display data is composed of 12 bits of 4 bits for each color or 18 bits of 6 bits for each color.

  Further, since the drain driver 511 is arranged above and below, the output for driving the drain driver 511 from the display control device 501 has two systems for both the control signal and the display data bus.

  FIG. 40 is a block diagram showing a schematic configuration of a drain driver 511 of a conventional TFT liquid crystal display module.

  As shown in FIG. 40, the drain driver 511 includes a data latch section 551 for display data and an output voltage generation circuit 552.

  Note that the drain driver 511 shown in FIG. 40 receives 6-bit display data and 9-level gradation reference voltage from the outside, and obtains an output voltage value of 64 levels.

  The data latch unit 551 fetches display data by the number of outputs in synchronization with the display data latch clock signal (CL1), and the output voltage generation circuit 552 generates the 64th floor generated from the gradation reference voltage input from the outside. Among the output voltages, the output voltage corresponding to the display data from the data latch unit 551 is selected and output to the drain signal line.

  FIG. 41 is a diagram showing an outline of the circuit configuration of the output voltage generation circuit 552 of the drain driver 511 of the conventional TFT liquid crystal display module. One circuit among the output voltage generation circuits provided for the total number of drain signal lines is shown. The circuit configuration of is shown.

  As shown in FIG. 41, the output voltage generating circuit generates voltage values (VO0 to VO64) obtained by dividing the 9-level gradation reference voltages (V0 to V8) inputted from the outside into 8 equal parts, The data is selected by the decoder 553 and output.

  FIG. 42 is a diagram showing the relationship between the gradation reference voltage and the output voltage in FIG.

  In FIG. 42, 65 output voltage values are obtained in total, but among them, VO64 equal to V8 is not used.

  When the display data of the TFT liquid crystal display module is composed of 6 bits for each color, when the display data is transmitted with 4 bits for each color from the main body computer, 4 bits from the main body computer are displayed. The display data in the TFT liquid crystal display module is the upper 4 bits data of 6 bits, and the lower 2 bits without input data are fixed to Low or High. The bit display data is converted into 6-bit display data for each color of the TFT liquid crystal display module.

  In addition, it has been conventionally known that a low-voltage drain driver can be used by adopting a common electrode AC driving method in which the voltage applied to the common electrode is AC as a common electrode driving method of the TFT liquid crystal display module. Yes.

  In general, as is apparent from the applied voltage-transmittance characteristics of a typical liquid crystal shown in FIG. 43, the voltage applied to the liquid crystal and its transparency are non-linear.

  As is clear from FIG. 43, the applied voltage-transmittance characteristics of the liquid crystal are markedly nonlinear at both ends of the operating voltage range and relatively linear at the center.

  Usually, it is possible to obtain a linear preferable gradation display by inputting a voltage value in accordance with this nonlinear characteristic to the drain driver.

  However, the drain driver 511 is configured to generate voltage values (VO0 to VO64) obtained by equally dividing the nine gradation reference voltages (VI0 to VI8) inputted from the outside into eight equal parts, and select and output them. In, only 8 gradations can be arbitrarily set by the user among the 64 gradations.

  In addition, the grayscale voltages generated inside the drain driver 511 are equally spaced between the grayscale reference voltages input from the outside in order to simplify the versatility of the drain driver 511 and the internal circuit of the drain driver 511. It is generated by partial pressure.

  For this reason, the gradation voltage generated inside the drain driver 511 has a problem that a deviation occurs from a voltage for obtaining a preferable linear and preferable gradation display.

  In the central portion of the operating voltage range where the applied voltage-transmittance characteristics of the liquid crystal exhibit a relatively linear characteristic, the influence of the “deviation” is not so great, but at both ends of the operating voltage where the nonlinear characteristics are significant, this “ The influence of “shift” cannot be ignored, and there is a problem that good gradation display characteristics cannot be obtained.

  Although it is possible to reduce this “deviation” by increasing the number of gradation reference voltages input from the outside, this method drives the drain driver 511, which increases the number of input leads of the drain driver 511. For this reason, there is a problem that the external circuit configuration is complicated and not practical.

  Further, the conventional method of converting the display data of 4 bits for each color from the main body computer into the display data of 6 bits for each color of the TFT liquid crystal display module cannot display 100% white or black. was there.

  An object of the present invention is to provide a technique capable of performing good gradation display in a TFT liquid crystal display.

  Another object of the present invention is to provide a technique capable of displaying 100% white or black and linear gradation display in the TFT liquid crystal display digital-to-digital conversion method.

  The above and other objects and novel configurations of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) Provided in a row direction to which a plurality of thin film transistors provided in a matrix, a common electrode, a liquid crystal provided between the plurality of thin film transistors and the common electrode, and a gate electrode of the thin film transistor in the row direction are connected. A TFT liquid crystal display panel having a plurality of gate signal lines and a plurality of drain signal lines provided in a column direction to which drain electrodes of thin film transistors in the column direction are connected, and a plurality of gate signal lines of the TFT liquid crystal display panel. A gate drive circuit for driving, a drain drive circuit for driving a plurality of drain signal lines of a TFT liquid crystal display panel, a common drive circuit for driving a common electrode, a power supply circuit, a control signal and display data from a computer unit And a display control device for controlling each of the circuits. In a TFT liquid crystal display capable of multi-grayscale display, an intermediate voltage between each grayscale reference voltage is generated from a reference voltage, and the intermediate voltage and a plurality of grayscale reference voltages are applied to the drain signal line. In the voltage generation circuit, the potential difference between the gradation reference voltages of the gradation reference voltage in the working voltage range where the applied voltage-transmittance characteristic of the liquid crystal is a non-linear region is a region where the applied voltage-transmittance characteristic of the liquid crystal is relatively linear A plurality of gradation reference voltages smaller than the potential difference between the gradation reference voltages of the gradation reference voltage in the working voltage range to be generated are generated, and the applied voltage-transmittance characteristics of the liquid crystal become a non-linear region in the drain driving circuit The number of intermediate voltages generated from each gradation reference voltage in the working voltage range is determined based on the number of intermediate voltages generated from each gradation reference voltage in the working voltage range where the applied voltage-transmittance characteristics of the liquid crystal are relatively linear. Characterized by being smaller than the number.

(2) In a method of converting n-bit display data from a computer unit into m (n <m) bit display data of a TFT liquid crystal display, the upper n bits of display data of the TFT liquid crystal display are converted. , N-bit display data from the computer unit, and the remaining (mn) lower-order bit display data of the TFT liquid crystal display are higher-order (m-n) display data from the computer unit (m -N) It is characterized by being used as bit display data.

[Action]
According to the means of the first item, in the gradation reference voltage generating circuit of the TFT liquid crystal display, the number of intermediate voltages interpolated between the reference voltages in the region where the applied voltage-transmittance characteristic of the liquid crystal is relatively linear. In the region where the applied voltage-transmittance characteristics of the liquid crystal are non-linear, the number of intermediate voltages interpolated between the reference voltages is reduced, so that the number of reference voltages input from the outside is not increased. Therefore, a gamma correction voltage suitable for the applied voltage-transmittance characteristics of the liquid crystal can be obtained, and thus a good gradation display can be obtained.

According to the means of the second item, the upper n-bit display data of the TFT liquid crystal display is used as the n-bit display data from the computer unit, and the lower (mn) of the remaining (mn) of the TFT liquid crystal display. Since the display data of the upper (mn) bits in the display data of n bits from the computer unit is used as the display data of bits, between all the bits Low and all the bits High A bit string obtained by thinning out with the optimum width is obtained.
As a result, 100% white or black can be displayed, and linear gradation display can be performed.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  (1) In a gradation reference voltage generation circuit of a TFT liquid crystal display, in a region where the applied voltage-transmittance characteristics of the liquid crystal are relatively linear, the number of intermediate voltages interpolated between the reference voltages is increased to apply the liquid crystal In the region where the voltage-transmittance characteristics are non-linear, the number of intermediate voltages interpolated between the reference voltages is reduced, so that the applied voltage-transmission of the liquid crystal is not increased without increasing the number of reference voltages input from the outside. A gamma correction voltage suitable for the rate characteristic can be obtained, whereby a good gradation display can be obtained.

(2) The upper n-bit display data of the TFT liquid crystal display is used as the n-bit display data from the computer unit, and the remaining (mn) lower-order bit display data of the TFT liquid crystal display is used. Since the display data of the upper (mn) bits in the display data of n bits from the computer unit is used, the range from all the bits Low to all the bits High is thinned out with an optimum width. A bit string is obtained.
As a result, 100% white or black can be displayed, and linear gradation display can be performed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.

  FIG. 1 is a block diagram showing a TFT liquid crystal display panel of a TFT liquid crystal display module which is an embodiment (embodiment 1) of the liquid crystal display device of the present invention and a circuit disposed in the periphery thereof.

  In the TFT liquid crystal display module of the first embodiment, a drain driver unit 103 is disposed on the upper side of a TFT liquid crystal display panel (TFT-LCD), and a gate driver is provided on a side surface of the TFT liquid crystal display panel (TFT-LCD). Unit 104, controller unit 101, and power supply unit 102 are arranged.

  The drain driver unit 103, the gate driver unit 104, the controller unit 101, and the power supply unit 102 are each mounted on a dedicated printed circuit board.

  The liquid crystal display panel (LCD) is composed of 640 × 3 × 480 pixels.

  FIG. 2 is a diagram showing an equivalent circuit of the TFT liquid crystal display panel (TFTP-LCD) shown in FIG.

  As shown in FIG. 2, the thin film transistor TFT is disposed in an intersection region between two adjacent drain signal lines D and two adjacent gate signal lines G.

  The drain electrode and the gate electrode of the thin film transistor TFT are connected to the drain signal line D and the gate signal line G, respectively.

  Since the source electrode of the thin film transistor TFT is connected to the pixel electrode, and the liquid crystal layer is provided between the pixel electrode and the common electrode, the liquid crystal capacitor CLC is equivalently connected between the source electrode of the thin film transistor TFT.

  The thin film transistor TFT becomes conductive when a positive bias voltage is applied to the gate electrode, and becomes non-conductive when a negative bias voltage is applied to the gate electrode.

  A storage capacitor CADD is connected between the source electrode of the thin film transistor TFT and the previous gate signal line.

  It should be understood that the source electrode and the drain electrode are originally determined by the bias polarity between them, and the polarity is inverted during the operation in the circuit of this liquid crystal display device, so that the source electrode and the drain electrode are interchanged during the operation. However, in the following description, for convenience, one is fixed as a source electrode and the other is fixed as a drain electrode.

  In this case, a dummy gate signal line (G0) is provided outside the gate signal line (G1) in order to prevent the other end of the storage capacitor CADD in the first gate line from being opened. The other end of the holding capacitor CADD is connected to the dummy gate signal line (G0).

  In the equivalent circuit of one pixel of the TFT liquid crystal display panel (TFT-LCD) shown in FIG. 3, stray capacitances CGD and CGS exist between the drain and gate of the thin film transistor TFT and between the gate and source.

  Therefore, as shown in FIG. 4, a series circuit of a storage capacitor CADD and a gate-source stray capacitor CGS is connected between the gate signal lines.

  However, since there is no gate signal line outside the gate signal line (Gend) of the final line, the gate signal is between the final gate signal line (Gend) and the other gate signal lines (G1 to Gend-1). The capacitance value of the capacitor connected to the line is different.

  In the TFT liquid crystal display module of the first embodiment, the dummy gate signal line (Gend + 1) is provided outside the final gate signal line (Gend) so that the capacitance values of the capacitors connected to the gate signal line are substantially the same. Provided.

  Further, the dummy gate signal lines (G0, Gend + 1) provided on both sides of the regular gate signal lines (G1 to Gend) also have an effect of preventing static electricity from entering during the manufacturing process.

  As is well known, the storage capacitor CADD functions to reduce the influence of the change in the gate potential on the pixel electrode potential when the thin film transistor (TFT) is switched.

  The storage capacitor CADD also has an action of extending the discharge time, and accumulates video information after the thin film transistor TFT is turned off for a long time.

  FIG. 5 is a block diagram showing a schematic configuration of each driver (drain driver, gate driver, common driver) of the TFT liquid crystal display module of the first embodiment and a signal flow.

  5, the display control device 201 and the buffer circuit 210 are provided in the controller unit 101 shown in FIG. 1, the drain driver 211 is provided in the drain driver unit 103 shown in FIG. 1, and the gate driver 206 is the gate driver shown in FIG. The unit 104 is provided.

  Similar to the drain driver 511 shown in FIG. 40, the drain driver 211 includes a data latch unit for display data and an output voltage generation circuit.

  The gradation reference voltage generator 208, multiplexer 209, common voltage generator 202, common driver 203, level shift circuit 207, gate-on voltage generator 204, gate-off voltage generator 205, and DC-DC converter 212 are shown in FIG. Provided in the power supply unit 102.

  As described in the prior art, in the conventional common electrode AC driving method, a square wave is used as the AC waveform, so that a large peak current flows through the common electrode driving transistor when the phase is switched, A transistor having a large value is required, and the drive circuit is enlarged accordingly.

  In order to solve the above problems, in the TFT liquid crystal display module of the first embodiment, the common voltage generator 202 shown in FIG. 5 converts the square wave AC signal (M) into a trapezoidal AC signal. A trapezoidal AC drive voltage is applied to the common electrode.

  FIG. 6 is a diagram showing a circuit configuration and input / output waveforms of the common voltage generation unit 202 shown in FIG.

  In the common voltage generation circuit 302 in FIG. 6A, when the high-level square wave shown in FIG. 6B is applied to the AC signal input terminal of the operational amplifier OP1, a current is passed through the resistor R1 and the capacitor C1. When the capacitor C1 is charged, the output voltage of the operational amplifier OP1 gradually decreases.

  When the potential difference between both ends of the capacitor C1 exceeds the forward voltage of the diode D1 connected in parallel with the capacitor C1, the diode D1 is turned on, so that the output voltage of the operational amplifier OP1 is a constant voltage on the low potential side. It becomes.

  When a low-level square wave shown in FIG. 6B is applied to the AC signal input terminal of the operational amplifier, the capacitor C1 is charged via the capacitor C1 and the resistor R1, whereby the output of the operational amplifier OP1. The voltage gradually increases.

  When the potential difference between both ends of the capacitor C1 exceeds the forward voltage of the diode D2 connected in parallel with the capacitor C1, the diode D2 is turned on, so that the output voltage of the operational amplifier OP1 is a constant voltage on the high potential side. It becomes.

  Thereby, as shown in FIG. 6B, a trapezoidal AC signal is obtained from the output terminal of the operational amplifier.

  The trapezoidal wave amplitude level can be changed by connecting a plurality of diodes D1 and D2 in series.

  By inputting the trapezoidal AC signal to the common driver 203 and driving the common electrode with the trapezoidal AC drive voltage, the peak current of the driving transistor can be suppressed as shown in FIG. Thereby, the drive circuit of the TFT liquid crystal display module can be reduced in size, and the outer size of the TFT liquid crystal display module can be reduced.

  In the equivalent circuit shown in FIG. 3, the other end of the liquid crystal capacitor CLC is connected to the common electrode COM.

  In the TFT liquid crystal display module according to the first embodiment, the common electrode is driven with an AC drive waveform, so that the previous gate signal line to which the other end of the storage capacitor CADD is connected is also applied to the common electrode. Unless the AC drive waveform is driven by adding an AC drive waveform having the same phase and amplitude as the AC drive waveform, the potential difference between both ends of the liquid crystal capacitor CLC cannot be kept constant.

  Therefore, in the TFT liquid crystal display module according to the first embodiment, as shown in FIG. 5, the AC signal from the common voltage generation unit 202 is input to the gate-on voltage generation unit 204 and the gate-off voltage generation unit 205, and the common electrode AC A gate-on voltage and a gate-off voltage to which a drive waveform is added are generated.

  FIG. 8 is a diagram illustrating a circuit configuration of the gate-on voltage generation unit 204 and the gate-off voltage generation unit 205 in the TFT liquid crystal display module according to the first embodiment.

  In FIG. 8, the gate-on voltage generation circuit 304 is composed of a level shift circuit composed of a constant current source I1 and a Zener diode ZD1, and a buffer circuit composed of an operational amplifier OP2, a PNP transistor TR1, and an NPN transistor TR2. The output voltage of the common driver 203 is shifted by a level shift circuit, and the shifted voltage is amplified by a buffer circuit.

  The gate-off voltage generation circuit 305 includes a level shift circuit including a constant current source I2 and a Zener diode ZD2, and a buffer circuit including an operational amplifier OP3, a PNP transistor TR3, and an NPN transistor TR4. The output voltage of the driver 203 is shifted by a level shift circuit, and the shifted voltage is amplified by a buffer circuit.

  FIG. 9 shows the common voltage applied to the common electrode, the drain voltage applied to the drain, the level of the gate voltage applied to the gate electrode, and the waveform thereof.

  In FIG. 9, the drain waveform indicates the drain waveform when black is displayed.

  In the circuit shown in FIG. 5, the common electrode AC drive waveform is added to both the gate-on voltage and the gate-off voltage. However, since the thin film transistor TFT can operate even when the gate-on voltage is a DC voltage, in FIG. The generation unit 204 can be omitted.

  By omitting the gate-on voltage generation unit 204, the circuit configuration is simplified, and the TFT liquid crystal display module can be downsized.

  FIG. 10 shows the common voltage applied to the common electrode, the drain voltage applied to the drain, the level of the gate voltage applied to the gate electrode, and the waveform when the gate-on voltage generation unit 204 is omitted.

  Further, as described above, the other end of the storage capacitor CADD in the first gate line is connected to the dummy gate signal line (G0).

  By applying a normal gate drive voltage (gate-on voltage, gate-off voltage) to the first dummy gate signal line (G0), the drive conditions can be made the same as the other gate signal lines. The contrast of the pixels on the line can be improved.

  Further, by applying a normal gate drive voltage (gate-on voltage, gate-off voltage) to the final dummy gate signal line (Gend + 1), the drive condition can be made the same as other gate signal lines. As a result, the contrast of the pixels in the final line can be improved.

  FIG. 11 is a diagram showing a circuit configuration of a power supply unit of a TFT liquid crystal display module which is an embodiment (embodiment 2) of the liquid crystal display device of the present invention.

  In the second embodiment, the gate-on voltage generation unit is omitted.

  In FIG. 11, the gradation reference voltage generation unit 208, the multiplexer 209, the common voltage generation unit 202, the common driver 203, the level shift circuit 207, the gate-off voltage generation unit 205, and the DC-DC converter 212 in FIG. Shown in dotted frame.

  In FIG. 11, a current mirror circuit CM corresponds to the constant current source I2 shown in FIG. 8, and a Zener diode ZD1 and the current mirror circuit CM constitute a level shift circuit.

  The output voltage from the common driver 203 is level-shifted in the level shift circuit, and the level-shifted voltage is taken out as a gate-off voltage.

  In FIG. 11, the frame signal (FLM) and the clock signal (CL3) are level-shifted by the level shift circuits (410, 420) and input to the buffer circuit 430.

  The frame signal (FLM) and the clock signal (CL3) output from the buffer circuit 430 are input to the gate driver.

  However, if noise is superimposed on the positive power supply for some reason, the buffer circuit operates with reference to the positive power supply, so that the buffer circuit 430 malfunctions and the TFT liquid crystal display module performs an erroneous display.

  For this reason, in the circuit configuration shown in FIG. 11, the capacitor C2 is connected between the positive power supply and the level shift circuit output.

  The malfunction of the buffer circuit 430 will be described with reference to FIG.

  In the differential amplifier type level shift circuit shown in FIG. 12A, when noise as shown in FIG. 12B is superimposed on the positive power supply, when the capacitor C2 is not connected, the level shift circuit of FIG. Since the noise superimposed on the output terminal from the positive power supply flows to the ground via the stray capacitance CCB between the collector and base of the transistor TR5, the output voltage of the level shift circuit is as shown by the solid line in FIG. It changes gently at the falling edge of noise.

  Therefore, when considering the output voltage of the level shift circuit with reference to the positive power supply, as shown in FIG. 3C, the potential difference between the positive power supply and the output voltage of the level shift circuit is small at the falling edge of the noise. As a result, a false pulse is generated, whereby the buffer circuit 430 malfunctions.

  That is, when CL3 input to the power supply unit shown in FIG. 11 is at a low level, the false pulse is input to the gate driver as CL3. When the false pulse is input to the gate driver, the gate driver performs a shift operation, and thus erroneous display occurs.

  In this embodiment, by connecting the capacitor C2 between the positive power supply and the output terminal of the level shift circuit, noise having the same waveform as the noise superimposed on the positive power supply passes through the capacitor C and is output from the level shift circuit. When the output voltage of the level shift circuit is considered with reference to the positive power supply, the potential difference between the positive power supply and the output voltage of the level shift circuit is approximately as shown by the broken line in FIG. It becomes a constant potential difference.

  As a result, a false pulse is not generated as indicated by a broken line in FIG. 5C, so that the malfunction of the buffer circuit 430 can be prevented and the noise resistance can be improved.

  If the value of the capacitor C2 is large, the function of the level shift circuit is lost. If the value of C2 is small, the effect of noise cancellation is small. Therefore, the value of the capacitor C2 needs to be 20 to 100 pF.

  Further, in the conventional TFT liquid crystal display module, the viewing angle adjustment is performed by changing the voltage applied to the drain signal line (D). However, in order to perform the viewing angle adjustment, between the counter electrode of the liquid crystal and the pixel electrode. Since the applied voltage only needs to be changed, in the second embodiment, the voltage applied to the common electrode is changed in order to adjust the viewing angle.

  For this reason, in the circuit configuration of the power supply unit 102 shown in FIG. 11, the common voltage generator 202 is connected to the terminals VA1, VA2, and VA3 by connecting variable resistors as shown in FIG. 13 to the terminals VA1, VA2, and VA3. The amplitude of the common voltage of the generated AC drive waveform is changed.

  As a result, the viewing angle of the TFT liquid crystal display module can be adjusted with a relatively simple circuit configuration, the driving circuit of the TFT liquid crystal display module can be simplified, and the outer dimensions of the TFT liquid crystal display module can be reduced. It becomes possible.

  Next, the gradation reference voltage generation unit 208 and the multiplexer 209 in the circuit configuration shown in FIG. 11 will be described.

  As shown in FIG. 11, the gradation reference voltage generation unit 208 includes two voltage dividing circuits, and the outputs of the two voltage dividing circuits are input to the multiplexer 209.

  The resistor series circuit of the two voltage divider circuits is that if the resistor series circuit constituting the first voltage divider circuit is RB1, RB2 to RB10, the resistor series circuit constituting the second voltage divider circuit is , RB10, RB9 to RB1 are configured.

  Further, the multiplexer 209 switches the outputs from the two voltage dividing circuits according to the high level and low level of the alternating signal (M) and outputs the gradation reference voltages (V0 to V8).

  Assuming that the gray level reference voltage V7 is applied from the drain driver 211 to the drain electrode and the low level common voltage is applied from the common driver to the common electrode, the common signal is inverted along with the inversion of the alternating signal (M). A high level common voltage is applied from the driver 203 to the common electrode.

  In this case, inverted display data is input to the drain driver 211, and the gray scale reference voltage V1 is applied to the drain electrode from the drain driver 211.

  The reason why there are two resistor series circuits is that, as shown in FIG. 43, since the liquid crystal has a gamma characteristic, it is necessary to switch the gradation reference voltage applied to the drain driver 211 during forward rotation and inversion.

  Further, the semi-fixed resistor connected to the inverting input terminal of the operational amplifier OP4 of the common driver 203 shown in FIG. 11 is for adjusting the DC level of the common signal voltage.

  Next, a TFT liquid crystal display module which is another embodiment (Example 3) of the liquid crystal display device of the present invention will be described.

  The TFT liquid crystal display module of Example 3 is designed to perform good gradation display.

  FIG. 14 shows the circuit configuration of the output voltage generation circuit of the drain driver 211 of the TFT liquid crystal display module of the third embodiment, which corresponds to one circuit in the output voltage generation circuit provided for the total number of drain signal lines (D). The circuit configuration is shown.

  The configuration of the drain driver 211 of the TFT liquid crystal display module according to the third embodiment is the same as that of the drain driver 511 shown in FIG. 40, and includes a data latch unit for display data and an output voltage generation circuit.

  In general, as shown in FIG. 43, the applied voltage-transmittance characteristics of the liquid crystal are markedly non-linear at both ends of the operating voltage range and relatively linear at the center.

  Therefore, in the output voltage generation circuit of the drain driver 211 of the TFT liquid crystal display module of the third embodiment, the number of voltage values to be interpolated between the external gradation reference voltages is reduced at both ends of the working voltage range, As is increased at the center, each of the nine gradation reference voltages (V0 to V8) input from the outside is divided into 16 equal parts, and both ends of the operating voltage range where the voltage-transmittance characteristics of the liquid crystal exhibit nonlinear characteristics. In the section, the most suitable 3 or 7 voltages are selected from the 16 equal parts by the decoder, and the voltage-transmittance characteristic of the liquid crystal exhibits a relatively linear characteristic. , 16 divided voltages are selected by the decoder 253.

  Therefore, in the output voltage generation circuit of the drain driver of the TFT liquid crystal display module of the third embodiment, the number of gradations incorporated between the gradation reference voltages is 3, 3, 7, 15, 15, 7, 3 in order. , 3.

  Further, the gradation reference voltage generation unit 208 uses nine gradation reference voltages (V0 to V8) as gradation reference voltages (at both ends of the working voltage range where the voltage-transmittance characteristics of the liquid crystal exhibit nonlinear characteristics). V0-V1, V1-V2, V2-V3, V5-V6, V6-V7, V7-V8), the potential difference is small, and the voltage-transmittance characteristic of the liquid crystal exhibits a relatively linear characteristic. The gray scale reference voltages are generated so that the potential difference becomes large between the gray scale reference voltages (V3-V4, V4-V5).

  FIG. 15 is a diagram showing the relationship between each gradation reference voltage and the output voltage in FIG.

  In FIG. 15, a total of 65 output voltage values are obtained, but VO64 equal to V8 is not used.

  FIG. 16 is a table showing the correspondence between decoder inputs and decoder outputs in FIG.

  As described above, if the gradation reference voltage generation unit 208 and the output voltage generation unit of the drain driver 211 in the TFT liquid crystal display module of the third embodiment are used, the nonlinear characteristic of the applied voltage-transmittance characteristic of the liquid crystal is remarkable. At both ends of the operating voltage range, the number of gradation reference voltages that can be arbitrarily set from the outside can be increased, and “deviation” between the originally desired gradation voltage and the gradation voltage generated inside the drain driver can be reduced.

  However, the number of gradation reference voltages that can be arbitrarily set from the outside decreases in the central portion of the working voltage range where the applied voltage-transmittance characteristics of the liquid crystal exhibit linear characteristics, and the level generated inside the drain driver 211. The number of regulated voltages increases.

  However, since the applied voltage-transmittance characteristic of the liquid crystal exhibits a relatively linear characteristic at the center of the operating voltage range, there is a “shift” between the desired gradation voltage and the gradation voltage generated inside the drain driver 211. It won't be too big and won't be a big problem.

  As a result, a gamma correction voltage suitable for the voltage-luminance characteristics of the liquid crystal can be obtained, and better gradation display characteristics can be obtained.

  In addition, it is not necessary to increase the number of gradation reference voltage values input from the outside, and it is not necessary to increase the number of peripheral circuits. Therefore, there is no increase in cost and increase in mounting area due to an increase in peripheral circuit components.

  In the TFT liquid crystal display module of the first embodiment, as shown in FIG. 1, the drain driver 211 is disposed only on the upper side of the liquid crystal display panel (LCD).

  FIG. 17 is a diagram illustrating the flow of display data and clock signals for the drain driver 211 in the TFT liquid crystal display module according to the first embodiment.

  The carry output of the previous stage of the drain driver 211 is directly input to the carry input of the drain driver 211 of the next stage.

  The carry signal controls the latch operation of the data latch unit 511 of the drain driver 211 to prevent erroneous display data from being written to the data latch unit 511.

  The display control unit 201 serves as an interface with the main computer, and drives the drain driver 211 and the gate driver 206 based on a control signal, a clock, and display data transmitted from the main computer.

  In the display control device 201 in the TFT liquid crystal display module according to the first embodiment, simple one-line display data transmitted from the main body computer is input to the drain driver 211.

  18 is a block diagram showing a schematic configuration of the display control apparatus 201 shown in FIG.

  FIG. 19 is a diagram showing a timing chart of the display control apparatus 201 shown in FIG.

  In the TFT liquid crystal display module according to the first embodiment, the display control device 201 includes a data processing unit 221 and a control signal processing / generation unit 222, and the control signal processing / generation unit 222 receives a control signal ( In response to the clock, the display timing signal, and the synchronization signal, control signals to the data processing unit 221 and each liquid crystal driver (the drain driver 211 and the gate driver 206) are generated.

  The control signal processing / generation unit 222 includes a drain driver drive circuit 223, a gate driver drive circuit 224, and an output clock generation circuit 225. The output clock generation circuit 225 shifts the data output clock and the drain driver 211. A clock (CL2) is generated.

  The data processing unit 221 includes a D-type flip-flop 226, a logic processing circuit 227, and a D-type flip-flop 228 that are connected in cascade, receives display data from the main body computer, and receives data from the control signal processing / generation unit 222. The display data is output to the drain driver 211 based on the clock signal.

  The logic processing circuit 227 of the data processing unit 221 is inserted to invert the display data, and can be configured by a multiplexer shown in FIG.

  Note that the logic processing circuit 227 is not necessary if the display data is not inverted.

  As is apparent from FIG. 19, the data output clock has the same frequency as the clock signal input from the main computer and the display data, and a D-type flip-flop is generated by the clock signal having the same frequency as the clock signal from the main computer. The display data fetched by the H.226 is output from the D-type flip-flop 228 to the data bus by the clock signal, and the simple one-line display data transmitted from the main computer is output to the data bus.

  As described above, according to the first embodiment, in the TFT liquid crystal display module, the drain driver is arranged on either the upper or lower side of the liquid crystal display panel, so that the frame area of the liquid crystal display panel can be reduced. Thus, the display area can be made larger than the external dimensions of the liquid crystal display device.

  Further, in the TFT liquid crystal display module of the first embodiment, a buffer circuit 210 is inserted between the display control device 201 and the drain driver 211 as shown in FIG.

  FIG. 21 is a block diagram showing a schematic configuration of a buffer circuit of a TFT liquid crystal display module which is another embodiment (embodiment 4) of the liquid crystal display device of the present invention.

  In the case of the first embodiment, all the drain drivers 211 are driven by one clock signal from the buffer circuit 210.

  In this case, when the number of drain drivers 211 increases, the buffer circuit 210 may not be able to drive the drain drivers 211, and a stable clock signal may not be supplied.

  Therefore, in the TFT liquid crystal display module of the fourth embodiment, the clock signal is divided into two systems, and the two systems of clock signals are supplied from independent buffer circuits (451, 452).

  This makes it possible to supply a stable clock signal even when the number of drain driver 211 serving as a load increases.

  In each of the above-described embodiments, the actual liquid crystal drive circuit is configured using a dedicated LSI and IC, respectively.

  FIG. 22 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (embodiment 5) of the liquid crystal display device of the present invention.

  In FIG. 22, the difference from FIG. 39 is that a buffer circuit (451, 452) is inserted between the display controller 201 of the TFT liquid crystal display module and the liquid crystal drivers (drain driver 211, gate driver 206). It is in.

  Accordingly, the buffer circuits (451, 452) drive the liquid crystal drivers (drain driver 211, gate driver 206) which are borne by the display control device 201 of the conventional TFT liquid crystal display module.

  The buffer circuits (451, 452) can be constituted by a plurality of semiconductor integrated circuits depending on the number of output terminals to be driven.

  As a result, the power consumption of the display control device 201, that is, the heat generation, can be distributed to each buffer circuit (451, 452).

  Then, compared with the wiring capacitance (about 20 [pF]) from the display control device 201 to the buffer circuit (451, 452), the buffer circuit (451, 452) to the liquid crystal driver group (drain driver 211, gate driver 206). Since the wiring capacitance (approximately 100 [pF] or more depending on the number of connected driver ICs) is large, the effect of distributing the power consumption of the display control device 201 to each buffer circuit (451, 452) is large. There is something.

  When components are placed on a printed circuit board, the display controller 201 and the buffer circuits (451, 452) are as close as possible to reduce the wiring capacity, so that the power consumption of the display controller 201 is suppressed. Is possible.

  In the TFT liquid crystal display module of the fifth embodiment, it is not necessary to develop the buffer circuit (451, 452) as a custom semiconductor integrated circuit, and it can be realized with a standard semiconductor integrated circuit.

  In the TFT liquid crystal display module of the fifth embodiment, non-inverted circuit elements are used for the buffer circuits (451, 452). However, depending on the circuit configuration, an inverted circuit element (inverter) or flip-flop element is used. It is also possible to use a flop circuit.

  However, in the TFT liquid crystal display module of the fifth embodiment, the buffer circuit (451, 452) is added, so that the total area of the semiconductor integrated circuit to be mounted increases, and the buffer circuit from the display control device 201 is increased. The power consumption corresponding to driving (451, 452) will increase overall.

  In the display control device 201, when the drain driver 211 is driven, the display data bus has more outputs than the control signal.

  When the display gradation increases, the number of data output from the display control apparatus 201 increases accordingly.

  Therefore, the display control apparatus 201 can be divided into a data processing unit and a control signal processing / generation unit to reduce power consumption.

  FIG. 23 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (embodiment 6) of the liquid crystal display device of the present invention.

  In the sixth embodiment, the display control apparatus 201 is divided into a data processing unit and a control signal processing / generation unit.

  24 is a diagram showing a circuit configuration of the data processing unit shown in FIG.

  FIG. 25 is a diagram showing a timing chart of the data processing unit shown in FIG.

  In FIG. 24, the control signal processing / generation unit 230 receives the control signals (clock, display timing signal, synchronization signal) from the main body computer, and sends them to the data processing units (231, 232) and each liquid crystal driver (drain driver 211). , A control signal of the gate driver 206) is generated.

  24 includes a multiplexer 233, a D-type flip-flop 234 to which the clock CK1 is input, and a D-type flip-flop 235 to which the clock CK2 is input. Display data from the main computer is received, and the display data is output to the drain driver 211 based on the clock signal from the control signal processing / generation unit 230.

  As is clear from the timing chart shown in FIG. 25, the clock signal (CK2) input to the upper data processing unit 231 and the clock signal (CK2) input to the lower data processing unit 232 have phases. The clock signal (CK2) is 180 ° different and has a cycle twice that of the clock signal from the main computer.

  As a result, in the upper and lower data processing units (231 and 232), the display data fetched into the D-type flip-flop 234 by the clock signal (CK1) having the same frequency as the clock signal from the main computer is In the D-type flip-flop 235 of the data processing unit 231, every other display data (a, c, e...) Is taken in by the clock signal (CK 2) and output to the upper data bus. In the D-type flip-flop 235 of the data processor 232, every other display data (b, d, f...) Is taken in by the clock signal (CK2) and output to the lower data bus.

  The display data is composed of 18 bits of 6 bits for each color.

  In the TFT liquid crystal display module of the sixth embodiment, the data processing units (231 and 232) also serve to drive the drain driver 211, so the total power consumption of the display control device 201 is the same as in the conventional example.

  In addition, since the control signal processing / generation unit 230 does not need to perform data processing, the size of the package is 100 to 150 in the conventional display control apparatus 201, which is different from that in the present embodiment. The TFT liquid crystal display module of Example 6 can be realized with the number of terminals of 50 or less.

  In the TFT liquid crystal display module of the sixth embodiment, a multiplexer 233 is inserted. This is because the IC used for the drain driver 211 needs to invert the data in accordance with the AC cycle of the voltage applied to the liquid crystal. Because there is.

  When data inversion is not necessary and data can be captured once, a standard semiconductor integrated circuit can be used for the data processing units (231 and 232).

  FIG. 26 is a block diagram showing a schematic configuration of a display control device of a TFT liquid crystal display module which is another embodiment (embodiment 7) of the liquid crystal display device of the present invention.

  The seventh embodiment is an embodiment of the TFT liquid crystal display module in which display data from the main body computer is input to the upper and lower data processing sections in parallel with the main computer in the sixth embodiment. This is an embodiment corresponding to a display module.

  FIG. 27 is a diagram showing a timing chart of the data processing unit shown in FIG.

  In the TFT liquid crystal display module of the seventh embodiment, as is apparent from the timing chart of FIG. 27, display data from the main body computer is input to the upper and lower data processing units (231, 232) in parallel in two pixels. Therefore, the clock signal (CK1) and the clock signal (CK2) have the same frequency as the clock signal from the main computer.

  As a result, in the upper and lower data processing units (231 and 232), the display data fetched into the D-type flip-flop 234 by the clock signal (CK1) having the same frequency as the clock signal from the main computer is D Display data (A, B, C...) And (a, b, c...) Input in parallel by the clock signal (CK2) from the type flip-flop 235 are output to the upper and lower data buses.

  In the TFT liquid crystal display modules of the sixth embodiment and the seventh embodiment, the data processing units (231 and 232) can be composed of a plurality of semiconductor integrated circuits. It is necessary to newly develop the control signal processing / generation unit 230 when realizing the multi-gradation by configuring the control signal processing / generation unit 230 so as to support multi-gradation and high definition. Disappear.

  Further, this semiconductor integrated circuit can be realized by a small package semiconductor integrated circuit such as TSOP (Thin Small Outline Package).

  As described above, in the TFT liquid crystal display module of each of the above embodiments, the display control device 201 in the conventional TFT liquid crystal display module is composed of a plurality of semiconductor integrated circuits, or the function is a plurality of semiconductor integrated circuits. Since it is configured, it is possible to disperse power consumption.

  Further, as shown in FIG. 28, in the TFT liquid crystal display module of each of the above embodiments, a specific terminal is provided on the I / F connector of the printed circuit board (interface board) on which the controller unit 101 is mounted. Signal voltage to be monitored among various signal voltages of the power supply unit 102 of the TFT liquid crystal display module, for example, DC level of common signal voltage, amplitude level of common signal voltage, DC level of gate on and gate off signal voltage, gate on and gate off signal voltage It is also possible to extract the amplitude level, gradation voltage, etc.

  Thereby, an I / F connector can be inserted to monitor various signal voltages of the power supply unit 102 of the TFT liquid crystal display module, thereby simplifying the adjustment work of the adjustment part during the manufacturing process and the final inspection process. The work process is reduced.

  As shown in FIG. 28, in the TFT liquid crystal display module of each of the above embodiments, the specific terminal of the I / F connector is connected to a specific portion of the driving circuit of the TFT liquid crystal display module, for example, the common driver shown in FIG. The DC level of the common signal voltage can be adjusted from the outside by connecting to the inverting input terminal of the operational amplifier OP4 203 and applying a voltage from the outside.

  As a result, an I / F connector can be inserted and an adjustment voltage can be applied from the outside, whereby a test of the driving circuit of the TFT liquid crystal display module can be easily performed from the outside.

  In the TFT liquid crystal display module of each of the embodiments, the display data for each color is composed of 6 bits and can display 64 gradations, whereas the display data transmitted from the main computer is It is assumed that it is configured with less than 6 bits for each color, for example, 4 bits for each color.

  In that case, it is necessary to convert 4-bit display data for each color from the main computer side into 6-bit display data for each color.

  Therefore, the present invention proposes an optimum digital-to-digital conversion method in the above case as shown in FIG.

  In FIG. 29, output 4 bits indicate display data of 4 bits for each color output from the main body computer, and input 6 bits are input to the drain driver 211 of the TFT liquid crystal panel (LCD) in each of the above embodiments. 6-bit display data for each color is shown.

  In the digital-to-digital conversion method shown in FIG. 29, the display data of 4 bits from the main body computer side is used for the display of the upper 4 bits of 6 bits which are inputted to the drain driver 211 of the TFT liquid crystal panel (LCD) as it is. As data, the upper 2 bits of 4 bits from the main computer side are input to the lower 2 bits without 6 bits of input data input to the drain driver 211 of the TFT liquid crystal panel (LCD).

  FIG. 30 shows a bit string converted from 4 bits to 6 bits by the digital-digital conversion method shown in FIG.

  As is apparent from FIG. 30, according to the digital-to-digital conversion method shown in FIG. 29, all bits Low (0, 0, 0, 0, 0, 0) are changed to all bits High (1, 1, 1, 1). , 1, 1), a bit string obtained by thinning out with an optimum width is obtained.

  As a result, the digital-to-digital conversion method shown in FIG. 29 can display 100% white or black and linear gradation compared to the conventional method of fixing the low-order bits with insufficient display data to Low or High. Display is possible.

  In the digital-digital conversion method shown in FIG. 29, the case of converting from 4 bits to 6 bits has been described as an example, but the present invention is not limited to this.

  FIG. 31 to FIG. 38 are diagrams showing a TFT liquid crystal display module according to another embodiment (Embodiment 8) of the present invention, including a connection portion between each IC and an I / F (interface) connector. FIG. 2 is a diagram illustrating a circuit configuration of an actual liquid crystal driving circuit.

  31 and 32 show the controller unit 101 shown in FIG. 1, FIGS. 33 and 34 show the drain driver unit 103 shown in FIG. 1, FIGS. 35 and 36 show the gate driver unit 104 shown in FIG. FIG. 38 shows the power supply unit 102 shown in FIG.

  The eighth embodiment includes a part of each of the embodiments described above. For example, in FIGS. 31 and 32, the display control device 201 is configured by one LSI, and the display control device 201 and the drain driver are included. Buffer circuit (IC2, IC3, IC4) is inserted between

  Further, the clock signal (CL2) is divided into two systems, and is supplied to every other drain driver IC from each independent buffer circuit in the IC3.

The I / F connectors 15 to 17 shown in FIG. 31 are terminals for connecting diopter adjusting resistors as shown in FIG. 13, and the I / F connector 18 is an operational amplifier OP4 shown in FIG. Connected to the non-inverting terminal to monitor the DC level of the common signal voltage and the amplitude level of the common signal voltage, or to adjust the DC level of the common signal voltage from the outside by applying an external voltage It is.
Although the present invention has been specifically described above based on the embodiments, it is needless to say that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

It is a block diagram which shows the circuit arrange | positioned in the TFT liquid crystal display panel of the TFT liquid crystal display module which is an Example (Example 1) of the liquid crystal display device of this invention, and its periphery. It is a figure which shows the equivalent circuit of the TFT liquid crystal display panel (TFTP-LCD) shown in FIG. It is a figure which shows the equivalent circuit of 1 pixel of the TFT liquid crystal display panel (TFTP-LCD) shown in FIG. It is a figure which shows the capacity | capacitance connected to each gate signal line of the equivalent circuit of 1 pixel of the TFT liquid crystal display panel (TFTP-LCD) shown in FIG. FIG. 2 is a block diagram showing a schematic configuration of each driver of the TFT liquid crystal display module of Example 1 and a signal flow. FIG. 6 is a diagram illustrating a circuit configuration and input / output waveforms of a common voltage generation unit illustrated in FIG. 5. It is a figure which shows that the peak current of the transistor for a drive can be suppressed by driving a common electrode with the alternating current drive voltage of a trapezoidal wave. It is a figure which shows the circuit structure of the gate-on voltage generation part in the TFT liquid crystal display module of the present Example 1, and a gate-off voltage generation part. It is a figure which shows the level of the common voltage applied to a common electrode, the drain voltage applied to a drain, the level of the gate voltage applied to a gate electrode, and its waveform in the present Example 1. FIG. 5 shows the common voltage applied to the common electrode, the drain voltage applied to the drain, the level of the gate voltage applied to the gate electrode, and the waveform when the gate-on voltage generator is omitted in the first embodiment. FIG. It is a figure which shows the circuit structure of the power supply part of the TFT liquid crystal display module which is an Example (Example 2) of the liquid crystal display device of this invention. FIG. 12 is a diagram for explaining a malfunction of the buffer circuit 430 in FIG. 11. 12 is a diagram illustrating a resistor network connected to terminals VA1, VA2, and VA3 in order to change the amplitude of a trapezoidal common voltage generated by a common voltage generator in the circuit configuration illustrated in FIG. It is a figure which shows the circuit structure of the output voltage generation circuit of the drain driver of the TFT liquid crystal display module of the present Example 3. It is a figure which shows the relationship between each gradation reference voltage and output voltage in FIG. 16 is a table showing a correspondence relationship between decoder inputs and decoder outputs in FIG. It is a figure which shows the flow of the display data with respect to a drain driver, and a clock signal in the TFT liquid crystal display module of the present Example 1. FIG. It is a block diagram which shows schematic structure of the display control apparatus shown in FIG. It is a figure which shows the timing chart of the display control apparatus shown in FIG. It is a figure which shows the circuit structure of the logic processing circuit shown in FIG. It is a block diagram which shows schematic structure of the buffer circuit of the TFT liquid crystal display module which is another Example (Example 4) of the liquid crystal display device of this invention. It is a block diagram which shows schematic structure of the display control apparatus of the TFT liquid crystal display module which is another Example (Example 5) of the liquid crystal display device of this invention. It is a block diagram which shows schematic structure of the display control apparatus of the TFT liquid crystal display module which is another Example (Example 6) of the liquid crystal display device of this invention. It is a figure which shows the circuit structure of the data processing part shown in FIG. It is a figure which shows the timing chart of the data processing part shown in FIG. It is a block diagram which shows schematic structure of the display control apparatus of the TFT liquid crystal display module which is another Example (Example 7) of the liquid crystal display device of this invention. It is a figure which shows the timing chart of the data processing part shown in FIG. It is a figure for demonstrating that a specific terminal is provided in an I / F connector and the drive circuit inside a TFT liquid crystal display module can be adjusted from the specific terminal. It is a figure for demonstrating the digital-digital conversion method of this invention. 30 is a table showing a bit string converted from 4 bits to 6 bits by the digital-digital conversion method shown in FIG. 29. It is a figure which shows the TFT liquid crystal display module which is another Example (Embodiment 8) of this invention, is a figure which shows the connection part between each IC and I / F connector, and is an actual liquid crystal drive circuit FIG. It is a figure which shows the TFT liquid crystal display module which is another Example (Embodiment 8) of this invention, is a figure which shows the connection part between each IC and I / F connector, and is an actual liquid crystal drive circuit FIG. It is a figure which shows the TFT liquid crystal display module which is another Example (Embodiment 8) of this invention, is a figure which shows the connection part between each IC and I / F connector, and is an actual liquid crystal drive circuit FIG. It is a figure which shows the TFT liquid crystal display module which is another Example (Embodiment 8) of this invention, is a figure which shows the connection part between each IC and I / F connector, and is an actual liquid crystal drive circuit FIG. It is a figure which shows the TFT liquid crystal display module which is another Example (Embodiment 8) of this invention, is a figure which shows the connection part between each IC and I / F connector, and is an actual liquid crystal drive circuit FIG. It is a figure which shows the TFT liquid crystal display module which is another Example (Embodiment 8) of this invention, is a figure which shows the connection part between each IC and I / F connector, and is an actual liquid crystal drive circuit FIG. It is a figure which shows the TFT liquid crystal display module which is another Example (Embodiment 8) of this invention, is a figure which shows the connection part between each IC and I / F connector, and is an actual liquid crystal drive circuit FIG. It is a figure which shows the TFT liquid crystal display module which is another Example (Embodiment 8) of this invention, is a figure which shows the connection part between each IC and I / F connector, and is an actual liquid crystal drive circuit FIG. It is a block diagram which shows schematic structure of the conventional TFT liquid crystal display module. It is a block diagram which shows schematic structure of the drain driver of the conventional TFT liquid crystal display module. It is a figure which shows the circuit structure of the output voltage generation circuit of the drain driver of the conventional TFT liquid crystal display module. It is a figure which shows the relationship between the gradation reference voltage and output voltage in FIG. It is a figure which shows the applied voltage-transmittance characteristic of typical liquid crystal.

Explanation of symbols

TFT-LCD TFT liquid crystal display panel TR1 to TR5 Transistors OP1 to OP4 Operational amplifier 101 Controller unit 102 Power supply unit 103 Drain driver unit 104 Gate driver unit 201,501 Display control device 202 Common voltage generation unit 203 Common driver 204 Gate on voltage generation unit 205 Gate off Voltage generation unit 206, 506 Gate driver 207 Level shift circuit 208 Gradation reference voltage generation unit 209, 233 Multiplexer 210, 430, 451, 452 Buffer circuit 211, 511 Drain driver 212 DC-DC converter 221 Data processing unit 222, 230 Control Signal processing / generation unit 223 Gate driver driving circuit 224 Drain driver driving circuit 225 Output clock generation circuit 226, 228, 34,235 D-type flip-flop 227 Logic processing circuit 231 Upper data processing unit 232 Lower data processing unit 253, 553 Decoder 302 Common voltage generation circuit 304 Gate on voltage generation circuit 305 Gate off voltage generation circuit 410, 420 Level shift circuit 551 Data latch 552 output voltage generation circuit

Claims (2)

A plurality of drain signal lines and a plurality of gate signal lines arranged so as to intersect the plurality of drain signal lines, and a plurality of regions each surrounded by the plurality of drain signal lines and the plurality of gate signal lines In a liquid crystal display device having a display region configured with the pixels, and having a liquid crystal sandwiched between a pair of substrates,
A drain driver connected to the plurality of drain signal lines and a gate driver connected to the plurality of gate signal lines are disposed outside the display region,
The drain driver generates a plurality of intermediate voltages interpolated between the plurality of gradation reference voltages based on a plurality of gradation reference voltages;
The liquid crystal display characterized in that the plurality of gradation reference voltages are assigned so that the number of both end portions is larger than the center portion in the voltage range used for voltage application-transmittance characteristics of the liquid crystal. apparatus. 2. The liquid crystal display according to claim 1, wherein each of the plurality of pixels includes a thin film transistor arranged corresponding to an intersection of the gate signal line and the drain signal line, and a pixel electrode connected to the thin film transistor. apparatus.

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