WO2008072553A1 - デジタルagc装置 - Google Patents
デジタルagc装置 Download PDFInfo
- Publication number
- WO2008072553A1 WO2008072553A1 PCT/JP2007/073608 JP2007073608W WO2008072553A1 WO 2008072553 A1 WO2008072553 A1 WO 2008072553A1 JP 2007073608 W JP2007073608 W JP 2007073608W WO 2008072553 A1 WO2008072553 A1 WO 2008072553A1
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- WO
- WIPO (PCT)
- Prior art keywords
- signal
- output
- outputs
- multiplier
- digital agc
- Prior art date
Links
- 238000012935 Averaging Methods 0.000 claims abstract description 8
- 230000002123 temporal effect Effects 0.000 claims abstract description 6
- 230000005540 biological transmission Effects 0.000 claims description 24
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 7
- 238000009499 grossing Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 241001591518 Norape Species 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
Definitions
- the present invention relates to a digital gain AGC (Automatic Gain Control) apparatus used when digitally demodulating a digitally modulated signal.
- AGC Automatic Gain Control
- An object of the present invention is to keep the average amplitude of a signal substantially constant without depending on the characteristics of a transmission line.
- a first digital AGC device multiplies an in-phase signal and a filter output signal, and multiplies a first multiplier that outputs the result, an orthogonal signal, and the filter output signal.
- a second multiplier that outputs the result, and a determination unit that enables and outputs the enable signal when the outputs of the first and second multipliers satisfy a condition defined by the threshold signal, and The square of the output of the first multiplier when the enable signal is valid.
- the second digital AGC device multiplies the in-phase signal and the filter output signal and outputs the result, an orthogonal signal, and the filter output signal.
- a second multiplier that multiplies and outputs the result, a transmission path quality estimation unit that obtains transmission path quality based on at least one of the outputs of the first and second multipliers, and the transmission path quality.
- a reference signal generation unit for generating a reference signal based on the square of the output of the first multiplier and the square of the output of the second multiplier, and calculating the output time square
- a loop filter that obtains a difference between a sum average unit, a calculation result of the reference signal and the square sum average unit, outputs the difference, and outputs the filter output signal as a filter output signal.
- the reference signal is generated based on the transmission path quality, the average amplitude of the output signal of the digital AGC device can be kept substantially constant even when a reflected wave or the like exists.
- Power S can be.
- the average amplitude of the output signal of the digital AGC device can be kept substantially constant. Since the amplitude of the output signal does not become too large, it is possible to reduce the performance of the demodulation circuit using this output signal.
- FIG. 1 is a block diagram showing a configuration of a demodulator having a digital AGC device according to a first embodiment of the present invention.
- FIG. 2 is an explanatory diagram showing received signal values when a reflected wave is present.
- Figure 3 shows the gain control by the analog AGC unit when there is a reflected wave. It is explanatory drawing which shows the value of the received signal.
- FIG. 4 is an explanatory diagram showing the value of a signal subjected to gain control by the analog AGC unit when no reflected wave exists.
- Fig. 5 is a graph showing the distribution of signal points in the presence of reflected waves (in the case of Fig. 3).
- FIG. 6 is a graph showing the distribution of signal points when no reflected wave exists (in the case of FIG. 4).
- FIG. 7 is a block diagram showing a configuration of a digital AGC apparatus according to the first embodiment of the present invention.
- FIG. 8 is a graph showing an example of signal points and threshold values of the determination unit in FIG.
- FIG. 9 is a block diagram showing a configuration of a digital AGC apparatus according to a second embodiment of the present invention.
- FIG. 10 is a graph for explaining generation of a reference signal REF.
- FIG. 1 is a block diagram showing a configuration of a demodulation device having a digital AGC device according to the first embodiment of the present invention.
- the demodulator shown in Fig. 1 includes an amplifier unit 12, an A / D converter 14, and an I A Q detection unit 22, a carrier wave and clock recovery unit 24, a digital AGC device 26, and an analog AGC unit 28 are included.
- the amplifier unit 12 amplifies the received signal according to the amplifier control signal AMC and outputs the amplified signal to the A / D converter 14.
- the A / D converter 14 converts the received signal into a digital signal and outputs it to the IQ detection unit 22 and the analog AGC unit 28.
- the analog AGC unit 28 generates and outputs an amplifier control signal AMC. Since the amplifier unit 12, the A / D converter 14 and the analog A GC unit 28 form a negative feedback loop and adjust the gain of the amplifier unit 12, the amplitude of the input signal to the A / D converter 14 is adjusted. The temporal average value (average amplitude) is kept almost constant.
- the IQ detector 22 performs quadrature detection on the output of the A / D converter 14 and outputs an in-phase signal and a quadrature signal.
- the carrier wave and clock recovery unit 24 performs digital demodulation processing on these in-phase signal and quadrature signal V, and outputs the result to the digital AGC device 26 as in-phase signal BI and quadrature signal BQ.
- the carrier wave and clock recovery unit 24 generates a symbol enable signal SYE and outputs it to the digital AGC device 26.
- the digital AGC device 26 keeps the average amplitude of the in-phase signal BI and the quadrature signal BQ substantially constant. At this time, the digital AGC device 26 follows amplitude fluctuations that cannot be followed by the analog AGC unit 28.
- the symbol position of the 8-level VSB modulation signal is one of the following:
- FIG. 2 is an explanatory diagram showing received signal values when a reflected wave is present.
- FIG. 3 is an explanatory diagram showing the value of the signal subjected to gain control by the analog AGC unit 28 when there is a reflected wave.
- FIG. 4 is an explanatory diagram showing the value of a signal subjected to gain control by the analog AGC unit 28 when no reflected wave exists. It is assumed that the probability of occurrence of eight values represented by an eight-value VSB modulation signal is the same.
- FIGS. 2 to 4 show the values of the received signals with respect to combinations of the main wave value and the reflected wave value.
- the value of the signal input to the demodulator in Fig. 1 is as shown in Fig. 2, and the average amplitude of the signal is kept constant by the control of the analog AGC unit 28. It becomes like this.
- each value is squared to obtain the sum (square sum) thereof. If the sum of squares in Figs. 3 and 4 is Z3 and Z4, respectively,
- Fig. 5 is a graph showing the distribution of signal points in the presence of reflected waves (in the case of Fig. 3).
- Fig. 6 is a graph showing the distribution of signal points when there is no reflected wave (in the case of Fig. 4).
- the negative AGC process is performed if a reflected wave exists.
- the feedback loop is controlled to make the signal larger than necessary. This is because the sum of squares is estimated to be small as described with reference to FIG. 3 when there is a reflected wave even if the optimum reference signal is used when the reflected wave is small.
- the digital AGC device 26 is configured as follows.
- FIG. 7 is a block diagram showing a configuration of the digital AGC apparatus 26 according to the first embodiment of the present invention.
- the digital AGC device 26 in FIG. 1 includes a first multiplier 31, a second multiplier 32, A square sum averaging unit 34, a subtractor 35, a loop filter unit 36, and a determination unit 38 are provided.
- the multipliers 31 and 32 receive the baseband in-phase signal BI and the quadrature signal BQ, respectively.
- the multiplier 31 multiplies the in-phase signal BI by the output of the loop filter unit 36, and outputs the result as a gain-controlled in-phase signal GI.
- the multiplier 32 multiplies the quadrature signal BQ and the output of the loop filter unit 36, and outputs the result as a gain-controlled quadrature signal GQ.
- the determination unit 38 enables the enable signal EN and outputs it to the square sum averaging unit 34.
- the square sum average unit 34 squares the in-phase signal GI and the quadrature signal GQ to obtain the sum, and further temporally averages the subtraction unit 35. Output to.
- the subtractor 35 subtracts the reference signal REF from the square sum average, and outputs the obtained error to the loop finisher unit 36.
- the loop filter unit 36 smoothes the error and outputs it to the multipliers 31 and 32. That is, the loop filter unit 36 multiplies the error by a predetermined coefficient “a”, performs further integration processing, and outputs the result to the multipliers 31 and 32.
- the digital AGC device 26 controls the gain for the in-phase signal BI and the quadrature signal BQ so that the error output from the subtractor 35 approaches 0, and the average amplitude of the output signal is increased. I try to keep it almost constant.
- FIG. 8 is a graph showing an example of signal points and threshold values of the determination unit 38 in FIG.
- the determination unit 38 enables the enable signal EN when the amplitude of at least one of the in-phase signal GI and the quadrature signal GQ is larger than the threshold signal TH, and disables the enable signal EN in other cases. To do.
- the determination unit 38 determines that the in-phase signal GI is not less than the threshold value TI1 and not more than the threshold value TI2, and the orthogonal signal GQ is not less than the threshold value TQ 1 and not more than the threshold value TQ 2 (for example, the signal point of the symbol).
- Enable signal EN is disabled when signal point SB), and enable signal EN is enabled otherwise (for example, when the signal point of the symbol is signal point SA).
- the thresholds TI2 and TQ2 are equal to the value of the threshold signal TH
- the thresholds TI1 and TQ1 are equal to ⁇ 1 times the value of the threshold signal TH.
- the square sum average unit 34 performs an operation for obtaining the mean square average for the symbol at that time, and when the enable signal EN is invalid, Do not calculate the sum of squares for the current symbol! /.
- the signal points of the symbol are concentrated near the origin of the complex plane, but the square sum averaging unit 34 does not use the symbol near the origin. For this reason, even if there is a reflected wave, the square sum average calculated by the square sum average unit 34 is not much smaller than when all symbols are used. Therefore, the gain of the negative feedback loop of the digital AGC device 26 can be prevented from becoming too large.
- the sum of squares unit 34 does not use a symbol near the origin of the complex plane, when there is no reflected wave, the sum of squares calculated by the sum of squares unit 34 is calculated as follows. The value is larger than when using symbols. At this time, since the gain of the negative feedback loop of the digital AGC device 26 becomes small and no reflected wave exists, the demodulation performance after the digital AGC device 26 does not deteriorate so much.
- the gain of the digital AGC device 26 can be adjusted by a simple calculation, and the average amplitude of the output signal is kept almost constant without depending on the characteristics of the transmission line. That power S.
- threshold value TI1 and the threshold value TQ1 shown in FIG. 8 may be different from each other, and the threshold value TI2 and the threshold value TQ2 are different from each other! /!
- the determination unit 38 determines that the sum of the square of the in-phase signal GI and the square of the quadrature signal GQ is the threshold signal T
- enable signal EN may be enabled, otherwise enable signal EN may be disabled.
- the threshold signal TH input to the determination unit 38 may be a fixed value or may be dynamically set from the outside.
- FIG. 9 is a block diagram showing the configuration of the digital AGC apparatus 226 according to the second embodiment of the present invention.
- the digital AGC device 226 in FIG. 9 includes a first multiplier 31, a second multiplier 32, a square sum averaging unit 234, a subtractor 35, a loop filter unit 36, and a transmission path quality estimation unit 4.
- the digital AGC device 226 In place of the digital AGC device 26 of FIG. 7, detailed description thereof is omitted.
- the transmission path quality estimation unit 48 determines whether a known data pattern and an actually received data pattern are based on the in-phase signal GI and the quadrature signal GQ output from the multipliers 31 and 32, respectively. Is obtained as the transmission path quality. At this time, the transmission path quality estimation unit 48 obtains a correlation value corresponding to the reflected wave included in the received wave. For example, a VSB modulation signal compliant with the ATSC standard includes a known data pattern in the field sync segment.
- FIG. 10 is a graph for explaining the generation of the reference signal REF.
- the normalized correlation value difference NR is 1 when there is no reflected wave, and is 0 when there is one reflected wave and the magnitude of the main wave and the reflected wave are the same.
- the reference signal generation unit 49 sets a value corresponding to the normalized correlation value difference NR as the reference signal REF.
- REF 10 * NR + 90. That is, when the reflected wave is large, the value of the reference signal REF is small.
- the relationship between the reference value REF and the normalized correlation value difference NR shown in FIG. 10 is an example, and may have another relationship.
- the square sum average unit 234 squares the in-phase signal GI and the quadrature signal GQ to obtain the sum, further averages the sum, and outputs the obtained square sum average to the subtractor 35.
- the subtractor 35 subtracts the reference signal REF from the square sum average, and outputs the obtained error to the loop filter unit 36.
- the value of the reference signal REF is appropriately controlled, so that the average amplitude of the output signal is substantially constant without depending on the characteristics of the transmission line. Can be kept in.
- the reference signal generator 49 generates a reference signal based on the tap coefficient value of the waveform equalizer.
- the reference signal generation unit 49 may switch the value of the reference signal REF depending on whether the reflected wave is present or not, and the switching operation has a hysteresis characteristic. Let's go.
- the transmission path quality estimation unit 48 may select one of the outputs of the multipliers 31 and 32, and obtain the transmission path quality based on the selected output. Yo.
- n-phase PSK phase modulation
- nQAM multi-level quadrature modulation
- the n-value VSB signal can be processed! /.
- the present invention can prevent the signal amplitude from becoming too large even in the presence of a reflected wave, and is useful as a digital AGC device or the like.
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- Control Of Amplification And Gain Control (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008549276A JPWO2008072553A1 (ja) | 2006-12-15 | 2007-12-06 | デジタルagc装置 |
EP07850217A EP2053739A4 (en) | 2006-12-15 | 2007-12-06 | DIGITAL AGC DEVICE |
US12/440,861 US20090279648A1 (en) | 2006-12-15 | 2007-12-06 | Digital agc device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-338381 | 2006-12-15 | ||
JP2006338381 | 2006-12-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2008072553A1 true WO2008072553A1 (ja) | 2008-06-19 |
Family
ID=39511573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2007/073608 WO2008072553A1 (ja) | 2006-12-15 | 2007-12-06 | デジタルagc装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20090279648A1 (ja) |
EP (1) | EP2053739A4 (ja) |
JP (1) | JPWO2008072553A1 (ja) |
KR (1) | KR20090088847A (ja) |
CN (1) | CN101523718A (ja) |
WO (1) | WO2008072553A1 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3334066B1 (en) * | 2015-08-27 | 2019-10-09 | Huawei Technologies Co., Ltd. | Optical signal processing method and coherent receiver |
Citations (6)
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JPH06216954A (ja) * | 1993-01-20 | 1994-08-05 | Nec Corp | バースト信号用agc回路 |
JP2001024454A (ja) * | 1999-07-07 | 2001-01-26 | Matsushita Electric Ind Co Ltd | 自動利得制御装置及び方法、並びに自動利得制御機能を持った無線通信装置 |
JP2001102947A (ja) * | 1999-09-29 | 2001-04-13 | Toshiba Corp | 自動利得制御回路および受信機 |
JP2001230690A (ja) * | 2000-02-15 | 2001-08-24 | Hitachi Kokusai Electric Inc | 受信機 |
JP2006050585A (ja) * | 2004-07-07 | 2006-02-16 | Sharp Corp | デジタル放送受信装置及び自動利得制御回路 |
JP2006148735A (ja) * | 2004-11-24 | 2006-06-08 | Matsushita Electric Ind Co Ltd | 受信機 |
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US5134631A (en) * | 1990-07-26 | 1992-07-28 | Unisys Corp. | Digital gain controller |
AU673390B2 (en) * | 1993-01-20 | 1996-11-07 | Nec Corporation | An AGC circuit for burst signal |
US5469115A (en) * | 1994-04-28 | 1995-11-21 | Qualcomm Incorporated | Method and apparatus for automatic gain control in a digital receiver |
JPH09307380A (ja) * | 1996-05-13 | 1997-11-28 | Toshiba Corp | Agc機能を備えた無線通信装置 |
US6148046A (en) * | 1998-01-20 | 2000-11-14 | Texas Instruments Incorporated | Blind automatic gain control system for receivers and modems |
US6081565A (en) * | 1998-02-05 | 2000-06-27 | Lucent Technologies Inc. | Amplitude based coarse automatic gain control circuit |
US6160443A (en) * | 1999-09-08 | 2000-12-12 | Atmel Corporation | Dual automatic gain control in a QAM demodulator |
US6516183B1 (en) * | 1999-09-10 | 2003-02-04 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for disturbance compensation of a direct conversion receiver in a full duplex transceiver |
US6843597B1 (en) * | 2001-05-15 | 2005-01-18 | Golden Bridge Technology Inc. | Method and apparatus of a fast two-loop automatic gain control circuit |
US7031409B2 (en) * | 2002-08-23 | 2006-04-18 | Samsung Electronics Co., Ltd. | Fully digital AGC circuit with wide dynamic range and method of operation |
TWI222794B (en) * | 2002-11-07 | 2004-10-21 | Realtek Semiconductor Corp | Initialization method for network system |
US7440526B2 (en) * | 2003-03-31 | 2008-10-21 | Intel Corporation | Method and apparatus to acquire frame within transmission |
DE60329633D1 (de) * | 2003-07-30 | 2009-11-19 | Mitsubishi Electric Corp | Schaltung zur veränderung der verstärkung eines vorverstärkers |
US8401128B2 (en) * | 2003-08-28 | 2013-03-19 | Telefonaktiebolaget L M Ericsson (Publ) | Method and system for adaptable receiver parameters |
JP4126005B2 (ja) * | 2003-10-08 | 2008-07-30 | 株式会社リコー | 無線通信システムの自動利得制御回路 |
KR100565306B1 (ko) * | 2003-11-22 | 2006-03-30 | 엘지전자 주식회사 | 이동통신 수신단의 증폭 오프셋 조정장치 |
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US7724842B2 (en) * | 2006-06-27 | 2010-05-25 | Freescale Semiconductor, Inc. | System and method for EVM self-test |
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2007
- 2007-12-06 KR KR1020097004728A patent/KR20090088847A/ko not_active Application Discontinuation
- 2007-12-06 US US12/440,861 patent/US20090279648A1/en not_active Abandoned
- 2007-12-06 JP JP2008549276A patent/JPWO2008072553A1/ja not_active Ceased
- 2007-12-06 WO PCT/JP2007/073608 patent/WO2008072553A1/ja active Application Filing
- 2007-12-06 CN CNA200780036837XA patent/CN101523718A/zh active Pending
- 2007-12-06 EP EP07850217A patent/EP2053739A4/en not_active Withdrawn
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH06216954A (ja) * | 1993-01-20 | 1994-08-05 | Nec Corp | バースト信号用agc回路 |
JP2001024454A (ja) * | 1999-07-07 | 2001-01-26 | Matsushita Electric Ind Co Ltd | 自動利得制御装置及び方法、並びに自動利得制御機能を持った無線通信装置 |
JP2001102947A (ja) * | 1999-09-29 | 2001-04-13 | Toshiba Corp | 自動利得制御回路および受信機 |
JP2001230690A (ja) * | 2000-02-15 | 2001-08-24 | Hitachi Kokusai Electric Inc | 受信機 |
JP2006050585A (ja) * | 2004-07-07 | 2006-02-16 | Sharp Corp | デジタル放送受信装置及び自動利得制御回路 |
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Non-Patent Citations (1)
Title |
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See also references of EP2053739A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP2053739A1 (en) | 2009-04-29 |
JPWO2008072553A1 (ja) | 2010-03-25 |
EP2053739A4 (en) | 2010-10-06 |
KR20090088847A (ko) | 2009-08-20 |
CN101523718A (zh) | 2009-09-02 |
US20090279648A1 (en) | 2009-11-12 |
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