Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K1/00—Soldering, e.g. brazing, or unsoldering
  • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K1/00—Soldering, e.g. brazing, or unsoldering
  • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
  • B23K1/0016—Soldering of electronic components
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
  • B23K20/002—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
  • B23K20/004—Wire welding
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
  • B23K20/24—Preliminary treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/019—Manufacture or treatment of bond pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/851—Dispositions of multiple connectors or interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
  • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W99/00—Subject matter not provided for in other groups of this subclass
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
  • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
  • B23K2101/00—Articles made by soldering, welding or cutting
  • B23K2101/36—Electric or electronic devices
  • B23K2101/40—Semiconductor devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
  • H10W72/01251—Changing the shapes of bumps
  • H10W72/01255—Changing the shapes of bumps by using masks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/015—Manufacture or treatment of bond wires
  • H10W72/01571—Cleaning, e.g. oxide removal or de-smearing
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/075—Connecting or disconnecting of bond wires
  • H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/221—Structures or relative sizes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/241—Dispositions, e.g. layouts
  • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/29—Bond pads specially adapted therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
  • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
  • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
  • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
  • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
  • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/59—Bond pads specially adapted therefor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/921—Structures or relative sizes of bond pads
  • H10W72/922—Bond pads being integral with underlying chip-level interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/981—Auxiliary members, e.g. spacers
  • H10W72/983—Reinforcing structures, e.g. collars

Definitions

• the invention relates generally to semiconductor device packaging, and more particularly, to methods of forming wire and solder bonds.
• wire and solder bonds are advantageous for use in multi-part wafers (MPWs), which are currently increasing in popularity.
• MPWs multi-part wafers
• Some of these MPWs include chips that require both wire bonds and solder bonds designed into a common reticle, i.e., they are fabricated together.
• a solder bond a solder joint flip chip, connection to a substrate is made where the surface tension forces of the molten solder controls the height of the joint and supports the weight of the chip.
• the solder bond is oftentimes referred to as a controlled collapse chip connection (C 4).
• C 4 controlled collapse chip connection
• a wire bond a wire is joined to an opening in the chip. Where both types of bonds are used, the fabrication process must be capable of opening both wire bond and solder bond final via structures in parallel.
• FEOL front-end-of-line
• BEOL back-end-of-line
• a method includes providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region.
• Wire bond and solder bond structures can be made accessible on a single multi-part wafer (MPW) wafer or on a single chip, if necessary.
• MPW multi-part wafer
• a first aspect of the invention provides a method of forming wire and solder bond structures, the method comprising: providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region including removing the protective layer; and forming the wire bond to the wire bond metal region.
• a second aspect of the invention provides a method of forming wire and solder bond structures, the method comprising: providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming a protective layer over the wire bond metal region only by: forming an uncured polyimide layer over the silicon nitride layer over the solder bond metal region and the wire bond metal region, forming a first opening exposing the wire bond metal region through the polyimide layer, the silicon nitride layer and the silicon oxide layer, and a second opening exposing the solder bond metal region through the polyimide layer, the silicon nitride layer and the silicon oxide layer, and forming the protective layer by forming an uncured photosensitive polyimide (PSPI) layer over the exposed wire bond metal region only; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered;
• a third aspect of the invention provides a method of forming wire and solder bond structures, the method comprising: providing a structure including a wire bond metal region for the wire bond and a solder bond metal region for the solder bond; forming a protective layer over the wire bond metal region only by forming a barrier layer portion over the wire bond metal region only; forming a silicon nitride layer over a silicon oxide layer over the wire bond metal region and the solder bond metal region; forming an uncured polyimide layer over the silicon nitride layer over the solder bond metal region and the wire bond metal region; and forming a first opening exposing the barrier layer portion over the wire bond metal region through the polyimide layer, the silicon nitride layer and the silicon oxide layer, and a second opening exposing the solder bond metal region through the polyimide layer, the silicon nitride layer and the silicon oxide layer; forming the solder bond to the solder bond metal region while maintaining the wire bond metal region covered; exposing the wire bond metal region by removing the barrier
• FIG. 1 shows a preliminary structure according to one embodiment of the invention.
• FIG. 2 shows a result of one step of a method according to one embodiment of the invention.
• FIGS. 3A-B show one embodiment of forming the structure of FIG. 2.
• FIGS. 4A-C show another embodiment of forming the structure of FIG. 2.
• FIGS. 5-6 show one embodiment of a method of completing forming of a solder bond and a wire bond according to the invention.
• FIG. 1 shows a preliminary structure 100 that is provided and includes a wire bond metal region 102 for a wire bond 190 (FIG. 6) and a solder bond metal region 104 for a solder bond 180 (FIGS. 5-6). Although shown separated, regions 102, 104 may be included in a single chip or be provided in a multi-part wafer. Hence, the separation indicated in the figures is meant to illustrate potential distance between regions 102, 104, not necessarily total separation.
• substrate 110 e.g., a dielectric
• wire 112 e.g., copper or aluminum
• barrier layers 114, 116, 118 e.g., silicon nitride, silicon oxide and silicon nitride, respectively.
• metal region 102, 104 may include, for example, aluminum or copper.
• FIGS. 2A-B show a first embodiment and FIGS. 3A-B show a second embodiment of a method of forming a protective layer 150 (FIG. 2B), 250 (FIGS. 3A-B) over wire bond metal region 102 only.
• a silicon nitride layer (Si N ) 106 is formed over a silicon oxide layer (SiO ) 108, which is formed over wire bond metal region 102 and solder bond metal region 104.
• Silicon nitride layer 106 may have a thickness of, for example, approximately 0.4 ⁇ m
• silicon oxide layer 108 may have a thickness of, for example, approximately 0.45 ⁇ m.
• An uncured polyimide or photosensitive polyimide (PSPI) layer 130 (hereinafter “polyimide layer 130") is then formed over silicon nitride layer 106 over solder bond metal region 102 and wire bond metal region 104.
• Layers 106, 108 and 130 may be formed using any now known or later developed techniques, e.g., depositing. Depositing, as used herein, may include any now known or later developed deposition technique.
• depositing may include but is not limited to spin application of organic materials like photoresist and polyimide, in addition to inorganic films deposited by chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma- enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), depending on the materials deposited.
• CVD chemical vapor deposition
• LPCVD low-pressure CVD
• PECVD plasma- enhanced CVD
• SACVD semi-atmosphere CVD
• HDPCVD high density plasma CVD
• RTCVD rapid thermal CVD
• UHVCVD ultra-high vacuum CVD
• sputtering deposition i
• a first opening 132 exposing wire bond metal region 102 through polyimide layer 130, silicon nitride layer 106 and silicon oxide layer 108, and a second opening 134 exposing solder bond metal region 104 through polyimide layer 130, silicon nitride layer 106 and silicon oxide layer 108 are substantially simultaneously formed.
• This step may occur in a number of ways, which are all considered within the scope of the invention.
• a photoresist 140 in phantom may be formed over silicon nitride layer 106 over solder bond metal region 104 and wire bond metal region 102.
• Photoresists described herein may include any now known or later developed photoresist material, e.g., a positive resist such as HD4000 PSPI material, JSR M20 or Shipley UV2HS, except where expressly denoted.
• An intermediate opening 142 may be formed through photoresist 140 over wire bond metal region 102 and solder bond metal region 104 in any now known or later developed manner, e.g., patterning and etching.
• An etching 144 is performed such as a wet develop/etch to remove polyimide layer 130, followed by a reactive ion etch (RIE) to remove silicon nitride layer 106 and silicon oxide layer 108 over wire bond metal region 102 and solder bond metal region 104 using intermediate opening 142.
• RIE reactive ion etch
• Photoresist 140 is then removed using any now known or later developed stripping process.
• Each of the above- described protective layer forming stages occur prior to formation of a protective layer 150 (FIG. 2B).
• protective layer 150 is formed over wire bond metal region 102 only.
• This stage may include forming protective layer 150 by forming an uncured photosensitive polyimide (PSPI) layer 152 over exposed wire bond metal region 102 only, for example, by depositing PSPI and patterning to leave PSPI layer 152 only over wire bond metal region 102.
• PSPI layer 152 may include, for example, HD4000 series photosensitive polyimide materials from HD Microsystems, etc. However, other materials may also be used.
• FIGS. 3A-B a second embodiment of a method of forming a protective layer 250 over wire bond metal region 102 only is illustrated.
• a protective layer 250 is formed prior to silicon oxide layer 108 and silicon nitride layer 106.
• protective layer 250 is formed as a barrier layer portion 252 over wire bond metal region 102 only, prior to forming silicon oxide layer 108 (FIG. 3B) and silicon nitride layer 106 (FIG. 3B).
• Barrier layer portion 252 may include, for example, silicon nitride, polysilicon, refractory metal film, or any other now known or later developed and appropriate barrier materials.
• This stage may include depositing a silicon nitride layer (not shown) and patterning to leave barrier layer portion 252 only over wire bond metal region 102.
• silicon oxide layer (SiO ) 108 and silicon nitride layer (Si N ) 106 are next formed over barrier layer portion 252 over wire bond metal region 102 and over solder bond metal region 104.
• Silicon nitride layer 106 may have a thickness of, for example, approximately 0.4 ⁇ m, and silicon oxide layer 108 may have a thickness of, for example, approximately 0.45 ⁇ m.
• Polyimide layer 130 is then formed over silicon nitride layer 106 over solder bond metal region 102 and wire bond metal region 104. Layers 106, 108 and 130 may be formed using any now known or later developed techniques, e.g., deposition. FIG.
• FIG. 3B also shows forming first opening 132 exposing barrier layer portion 252 over wire bond metal region 102 through polyimide layer 130, silicon nitride layer 106 and silicon oxide layer 108, and a second opening 134 exposing solder bond metal region 104 through polyimide layer 130, silicon nitride layer 106 and silicon oxide layer 108.
• This stage may occur substantially similarly to that described above relative to FIG. 2A. That is, briefly, using photoresist 140 (in phantom) patterning and etching 144, e.g., using a wet develop/etch to remove polyimide layer 130, followed by a RIE to remove silicon nitride layer 106 and silicon oxide layer 108 over wire bond metal region 102 and solder bond metal region 104. Photoresist 140 is then removed using any now known or later developed stripping process.
• FIG. 4A shows forming solder bond 180 to solder bond metal region 104 while maintaining wire bond metal region 102 covered using the embodiment of FIGS. 2A-2B.
• FIG. 4B shows forming solder bond 180 to solder bond metal region 104 while maintaining wire bond metal region 102 covered using the embodiment of FIGS. 3A-B.
• this process may include depositing a ball limiting metallurgy (BLM) layer 182, e.g., by PVD.
• BLM layer 182 includes a solder wettable terminal metallurgy (e.g., tin (Sn) alloy), which defines the size and area of solder bond 180 when completed.
• BLM ball limiting metallurgy
• FIGS. 4A-B also show depositing a photoresist 184 and forming an opening 186 in photoresist 184 over solder bond metal region 104 only (i.e., no opening over wire bond metal region 102) to BLM layer 182.
• photoresist 184 may include a photosensitive dry polymer resist such as RISTON® available from DuPont. However, other photoresist material may also be employed.
• Solder for solder bond 180 is formed (deposited) in photoresist opening 186.
• Solder bond 180 may include any now known or later developed solder materials, e.g., including typically any alloy of lead-tin (PbSn) or tin (Sn)(Pb-free). Wire bond metal region 102 remains covered during this entire process by photoresist 184 and the respective protective layers 150 (FIG. 4A) and 250 (FIG. 4B).
• solder materials e.g., including typically any alloy of lead-tin (PbSn) or tin (Sn)(Pb-free).
• Wire bond metal region 102 remains covered during this entire process by photoresist 184 and the respective protective layers 150 (FIG. 4A) and 250 (FIG. 4B).
• FIG. 5 shows exposing wire bond metal region 102 including removing protective layer 150 (FIG. 4A), 250 (FIG. 4B) to wire bond metal region 102.
• This process includes removing photoresist 184 (FIGS. 4A-4B) and BLM layer 182 (FIGS. 4 A-B) except BLM layer 182S under solder bond 180 to expose wire bond metal region 102, e.g., by etching 192.
• this stage includes removing uncured PSPI layer 152 (FIG. 4A), e.g., using a dry etch 194, to expose wire bond metal region 102.
• this stage includes removing barrier layer portion 252, e.g., by RIE 194, to expose wire bond metal region 102.
• This process may optionally include performing a wet clean 196 (FIG. 6) using, for example, hydrofluoric acid, of wire bond metal region 102 subsequent to protective layer 150, 250 (FIGS. 4A-B) removal.
• this process may include cleaning and reflowing solder bond 180.
• Wire bond 190 may then be formed to wire bond metal region 102 using any now known or later developed techniques.

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• Engineering & Computer Science (AREA)
• Mechanical Engineering (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Wire Bonding (AREA)
• Die Bonding (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

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Family Applications (1)

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Citations (4)

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• 2006
  • 2006-11-20 US US11/561,434 patent/US7521287B2/en not_active Expired - Fee Related
• 2007
  • 2007-10-31 KR KR1020097009880A patent/KR20090075858A/ko not_active Abandoned
  • 2007-10-31 DE DE602007012367T patent/DE602007012367D1/de active Active
  • 2007-10-31 JP JP2009536694A patent/JP5055634B2/ja not_active Expired - Fee Related
  • 2007-10-31 EP EP07822113A patent/EP2097202B1/en not_active Not-in-force
  • 2007-10-31 AT AT07822113T patent/ATE497419T1/de not_active IP Right Cessation
  • 2007-10-31 WO PCT/EP2007/061766 patent/WO2008061865A1/en not_active Ceased

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