Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
  • H05B41/14—Circuit arrangements
  • H05B41/24—Circuit arrangements in which the lamp is fed by high frequency AC, or with separate oscillator frequency
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
  • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
  • H05B41/14—Circuit arrangements
  • H05B41/26—Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC
  • H05B41/28—Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC using static converters
  • H05B41/282—Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC using static converters with semiconductor devices
  • H05B41/2825—Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC using static converters with semiconductor devices by means of a bridge converter in the final stage
  • H05B41/2828—Circuit arrangements in which the lamp is fed by power derived from DC by means of a converter, e.g. by high-voltage DC using static converters with semiconductor devices by means of a bridge converter in the final stage using control circuits for the switching elements

Definitions

• the present invention relates to a method of synchronizing the frequency of a discharge tube lighting device, a discharge tube lighting device, and a semiconductor integrated circuit used for lighting a discharge tube, particularly a liquid crystal display device using a cold cathode tube.
• FIG. 1 is a circuit diagram showing a configuration when a synchronization signal is not input to a conventional discharge tube lighting device.
• FIG. 2 is a timing chart showing signals at various parts when no sync signal is input to the conventional discharge tube lighting device.
• a high-side P-type MOSFET Qpl referred to as P-type FETQpl
• a low-side N-type MOSFET Qnl referred to as N-type FETQnl
• the DC power supply Vin is supplied to the source of the P-type FETQpl, and the gate of the P-type FETQpl is connected to the terminal DRV1 of the controller IC1.
• the gate of N-type FETQnl is connected to terminal DRV2 of control IC 1!
• the control IC 1 includes a start circuit 10, a constant current determination circuit 11, an oscillator 12, a frequency divider 13, an error amplifier 15, a PWM comparator 16, a NAND circuit 17a, an AND circuit 17b, and drivers 18a and 18b. .
• the constant current determining circuit 11 is connected to one end of the constant current determining resistor R 1 via the terminal RF.
• the oscillator 12 is connected to one end of the capacitor C1 through the terminal CF.
• the start circuit 10 receives a power supply from the DC power supply Vin, generates a predetermined voltage REG, and supplies it to each internal part.
• the constant current determination circuit 11 can be arbitrarily set by the constant current determination resistor R1. The set constant current is applied.
• the oscillator 12 charges and discharges the capacitor C1 with the constant current of the constant current determining circuit 11, and shows a sawtooth oscillation waveform as shown in FIG. 2 (in FIG. 2, the charge / discharge voltage of the capacitor C1 at the terminal CF is shown). )
• the clock CK is a pulse voltage waveform in which the rising period synchronized with the sawtooth oscillation waveform at the terminal CF is H level and the falling period is L level, and is sent to the frequency divider 13 .
• the tube current detection circuit 5 includes diodes Dl and D2 and resistors R3 and R4.
• the tube current detection circuit 5 detects a current flowing through the discharge tube 3, and supplies a voltage proportional to the detected current via the feedback terminal FB of the control IC1. Output to one terminal of error amplifier 15.
• the error amplifier 15 amplifies the error voltage FBOUT between the voltage from the tube current detection circuit 5 input to one terminal and the reference voltage E1 input to the + terminal, and converts the error voltage FBOUT to the PW M comparator. Send to 16 + terminals.
• the PWM comparator 16 is input to the + terminal.
• Error voltage from the error amplifier 15 is FB when the error voltage FBOUT is input to the-terminal.
• the error voltage FBOUT is the sawtooth waveform voltage.
• a pulse signal that is L level when it is less than the threshold value, and outputs it to the NAND circuit 17a and the AND circuit 17b.
• the frequency divider 13 divides the noise signal from the oscillator 12, outputs the divided pulse signal Q to the NAND circuit 17a, and inverts the divided noise signal Q.
• a low signal (having a predetermined dead time with respect to the divided noise signal Q) is output to the AND circuit 17b.
• the NAND circuit 17a performs a NAND operation on the divided pulse signal from the frequency divider 13 and the signal from the PWM comparator 16, and outputs a drive signal to the P-type FETQpl via the driver 18a and the terminal DRV1.
• the AND circuit 17b calculates the AND of the divided and inverted pulse signal from the frequency divider 13 and the signal from the PWM comparator 16, and outputs the drive signal to the N-type FET Qnl via the driver 18b and the terminal DRV2. To do.
• control IC1 turns P-type FE TQpl and N-type FETQnl on and off alternately at the frequency of the sawtooth oscillation waveform. As a result, electric power is supplied to the discharge tube 3 and the current flowing through the discharge tube 3 is controlled to a predetermined value.
• the oscillation frequency of the oscillator 12 provided in the discharge tube lighting device shown in FIG. 1 is generally determined by the resistor R1 and the capacitor C1. However, depending on the components used (resistors and capacitors), it interferes with the low-frequency burst dimming oscillation frequency and the SMPS oscillation frequency located in the front stage of the discharge tube lighting device. May cause flickering of the screen.
• a synchronization pulse voltage signal is input from the outside to the discharge tube lighting device and the oscillation frequency of the oscillator 12 is defined in synchronization with the external synchronization pulse voltage signal.
• the lighting frequency of the discharge tube is synchronized with the frequency of the external synchronization pulse voltage signal or the half frequency of the external synchronization pulse voltage signal.
• a synchronizing circuit as shown in Fig. 3 is added.
• the synchronizing circuit shown in FIG. 3 has an external rising edge of the synchronizing pulse voltage signal TRI.
• It has a one-shot circuit 2 that generates a one-shot pulse, a diode D3 connected between the output of the one-shot circuit 2 and one end of a capacitor C1, and a Zener diode ZD1 connected to both ends of the capacitor C1. As shown in Fig.
• a synchronous pulse voltage signal TRI with a frequency higher than the frequency of the sawtooth oscillation waveform CF of the capacitor C1 is input from this synchronization circuit to the capacitor C1, and the sawtooth oscillation waveform CF of the capacitor C1 is
• the frequency of the discharge tube 3 is synchronized with the frequency of the synchronized pulse voltage signal TRI and the frequency of the discharge tube 3 is synchronized with the 1/2 frequency of the synchronized pulse voltage signal TRI.
• a semiconductor switch circuit is provided in the primary winding of the transformer where the secondary winding is connected to the load, and each switch of the semiconductor switch circuit is controlled by PWM to control the constant current.
• the control circuit block When the stop signal stop command is entered, the control circuit block is turned off and placed in a standby state. At the same time, by turning off the switch drive signal that turns on the switch in the semiconductor switch circuit, it is possible to prevent the generation of an excessive current when shifting to the standby state.
• the frequency synchronization is lower than the frequency of the sawtooth oscillation waveform CF of the capacitor C1.
• the noise signal TRI is input, the continuity of the triangular wave waveform is lost, the noise width of the two drive signals is different, and the phase is no longer 180 ° out of phase. That is, in the figure, the drive signal at the terminal DRV2 is different in pulse width from the drive signal at the terminal DRV1, and the phase difference is not 180 °.
• the current flowing through the discharge tube becomes unbalanced, and the mercury distribution inside the discharge tube is biased, causing a brightness gradient and a decrease in life.
• the present invention can be synchronized regardless of whether the frequency of the synchronization noise voltage signal is high or low with respect to the oscillation frequency of the oscillator, and can broaden the frequency band of the synchronization noise voltage signal, and is stable and easy. It is another object of the present invention to provide a frequency synchronization method for a discharge tube lighting device, a discharge tube lighting device, and a semiconductor integrated circuit that can synchronize an oscillation frequency with a synchronization noise voltage signal.
• the frequency synchronization method for a discharge tube lighting device includes a capacitor connected to at least one of the primary winding and the secondary winding of the transformer, and the output thereof.
• the oscillation slope of the oscillator capacitor is the same as the slope of the discharge and generates a triangular wave signal for turning on / off the plurality of switching elements and oscillates, and less than a half cycle of the triangular wave signal.
• the plurality of switching units so that a current flows through the discharge tube with a width corresponding to a current flowing through the discharge tube.
• a positive voltage value is switched when the duty voltage is approximately 50%, and a positive current value is converted to a pulse current with the same absolute value, and superimposed on the triangular wave signal of the oscillator to generate a no-less current.
• Generating the first drive signal and generating the second drive signal in synchronization with the frequency of the pulse current in the process of generating the pulse current.
• Generate drive signal and second drive signal Characterized in that it.
• a discharge tube lighting device is a discharge tube lighting device that supplies electric power to a discharge tube by converting from direct current to positive and negative symmetrical alternating current, and includes at least a primary winding and a secondary winding of a transformer.
• a capacitor is connected to one winding, and the discharge tube is connected to the output thereof.
• a current is supplied to the primary winding of the transformer and the capacitor connected to both ends of the DC power source and the capacitor.
• a plurality of switching elements having a bridge configuration for flowing a current, and an oscillator that generates a triangular wave signal for turning on and off the plurality of switching elements having the same slope of charging and discharging slope of the oscillator capacitor;
• One or more switching elements of one of the plurality of switching elements so that a current flows through the discharge tube with a pulse width corresponding to a current flowing through the discharge tube within a half cycle of the triangular wave signal.
• a first drive signal is generated to drive the discharge tube, has a phase difference of about 180 degrees with substantially the same pulse width as the first drive signal, and the discharge tube in a direction opposite to that when the first drive signal is generated.
• a pulse current generation circuit that switches between positive and negative current values and converts them into pulse currents having the same absolute value of the positive and negative current values and superimposes them on the triangular wave signal of the oscillator, and the signal generation unit includes the pulse current generation circuit.
• the first drive signal and the second drive signal are generated in synchronization with the frequency of the pulse current from.
• a semiconductor integrated circuit includes a plurality of bridges configured to supply power to a discharge tube.
• a signal generator for generating a second drive signal for driving one or more other switching elements of the plurality of switching elements; an input terminal for inputting a synchronous pulse voltage signal; and the input terminal
• the pulsed current that is converted to a pulse current with a duty cycle of approximately 50% and a positive / negative current value is switched and the absolute value of the positive / negative current value is equal and superimposed on the triangular wave signal of the oscillator.
• the signal generator generates the first drive signal and the second drive signal in synchronization with the frequency of the pulse current from the pulse current generation circuit.
• FIG. 1 is a circuit diagram showing a configuration in a case where a synchronous noise voltage signal is not input to a related discharge tube lighting device.
• FIG. 2 is a timing chart showing signals at various parts when a synchronous noise voltage signal is not input to the related discharge tube lighting device.
• FIG. 3 is a circuit diagram showing a configuration when a synchronous pulse voltage signal is input to the related discharge tube lighting device.
• FIG. 4 is a timing chart showing signals at various parts when a synchronous pulse voltage signal is input to the related discharge tube lighting device.
• Fig. 5 shows the signal of each part when the synchronous pulse voltage signal is input to the related discharge tube lighting device and the frequency of the synchronous pulse voltage signal is lower than the frequency of the sawtooth oscillation waveform of the capacitor. It is a timing chart which shows.
• FIG. 6 is a circuit diagram showing a configuration of a discharge tube lighting device according to Embodiment 1 of the present invention.
• Fig. 7 is a diagram showing charge / discharge noise provided in the discharge tube lighting device according to Embodiment 1 of the present invention. It is a circuit diagram which shows the structure of a current generation circuit.
• FIG. 8 is a timing chart for explaining the operation of the charge / discharge noise current generation circuit shown in FIG.
• FIG. 9 is a timing chart showing signals at various parts when a synchronous noise voltage signal is input to the discharge tube lighting device according to Embodiment 1 of the present invention.
• Fig. 10 is a timing chart showing signals at various parts when a synchronous noise voltage signal is input to the discharge tube lighting device according to Embodiment 1 of the present invention.
• FIG. 11 is a circuit diagram showing a configuration of a discharge tube lighting device according to Embodiment 2 of the present invention.
• FIG. 12 is a circuit diagram showing a configuration of a charge / discharge pulse current generating circuit provided in the discharge tube lighting device according to Embodiment 2 of the present invention.
• FIG. 13 is a timing chart for explaining the operation of the charge / discharge pulse current generating circuit shown in FIG. 12.
• FIG. 14 is a timing chart showing signals at various parts when a synchronous noise voltage signal is input to the discharge tube lighting device according to Embodiment 2 of the present invention.
• FIG. 15 is a timing chart showing signals at various parts when a synchronous noise voltage signal is input to the discharge tube lighting device according to Embodiment 3 of the present invention.
• FIG. 16 is a timing chart showing signals at various parts when a synchronous noise voltage signal is inputted to the discharge tube lighting device according to Embodiment 3 of the present invention.
• FIG. 17 is a timing chart showing signals at various parts when a synchronous noise voltage signal is input to the discharge tube lighting device according to Embodiment 4 of the present invention.
• FIG. 18 is a circuit diagram showing a configuration of a discharge tube lighting device according to Embodiment 5 of the present invention.
• FIG. 19 is a timing chart showing signals at various parts when a synchronous noise voltage signal is input to the discharge tube lighting device according to Embodiment 5 of the present invention.
• FIG. 6 is a circuit diagram showing a configuration of the discharge tube lighting device according to Embodiment 1 of the present invention.
• the discharge tube lighting device shown in Fig. 6 differs from the discharge tube lighting device shown in Fig. 1 only in the control ICla.
• the other configuration shown in FIG. 6 is the same as the configuration shown in FIG. 1.
• the same parts are denoted by the same reference numerals, description of those parts is omitted, and only different parts will be described here.
• the control ICla corresponds to the semiconductor integrated circuit of the present invention, and includes a charge / discharge pulse current generation circuit 20, a start circuit 10, a constant current determination circuit lla, an oscillator 12a, an error amplifier 15, a subtraction circuit 19, and a PWM comparator 16a. , 16b, NAND circuit 17c, logic circuit 17d, and drivers 18a and 18b.
• the configuration of the start circuit 10 is the same as that shown in FIG.
• the constant current determining circuit 11a is connected to one end of a constant current determining resistor R2 via a terminal RF.
• the oscillator 12a is connected to one end of the capacitor C2 via the terminal CF.
• the constant current determining circuit 11a passes a constant current arbitrarily set by the constant current value determining resistor R2.
• the oscillator 12a charges and discharges the capacitor C2 with the constant current of the constant current determination circuit 11a, generates a triangular wave signal, generates a clock CK based on the triangular wave signal, and sends it to the NAND circuit 17c and the logic circuit 17d.
• the triangular wave signal has the same rising slope and falling slope. Rising and falling slopes are set by the value of capacitor C2 and resistor R2.
• the output terminal of the error amplifier 15 is connected to the + terminal of the PWM comparator 16a, and is connected to one terminal of the subtraction circuit 19 via the resistor R4.
• a resistor R5 is connected between one terminal of the subtraction circuit 19 and the output terminal.
• the subtraction circuit 19 is a voltage obtained by inverting the error voltage FBOUT from the error amplifier 15 via the resistor R4 at the midpoint potential between the upper limit value and lower limit value of the triangular wave signal, which is the reference voltage E2 of the + terminal, that is, an error.
• the inverted waveform of voltage FBOUT is output to the — terminal of PWM comparator 16b.
• the PWM comparator 16a is at the H level when the error voltage FB OUT input to the + terminal is equal to or higher than the triangular wave signal voltage from the terminal CF input to the-terminal. When the error voltage FBOUT is less than the triangular wave signal voltage, a pulse signal that goes low is generated and output to the NAND circuit 17c.
• the PWM comparator 16b has a triangular wave signal voltage level S from the terminal CF that is input to the + terminal, an error voltage from the subtraction circuit 19 that is input to the-terminal, and is at the H level when it is greater than the inverted waveform voltage of FBOUT. Generates a pulse signal that goes low when the voltage is less than the inverted waveform voltage of the error voltage FBOUT and outputs it to the logic circuit 17d.
• the NAND circuit 17c performs a NAND operation on the clock from the oscillator 12a and the signal from the PWM comparator 16a, and outputs the first drive signal to the P-type FE TQpl via the driver 18a and the terminal DRV1.
• the logic circuit 17d performs an AND operation on the signal obtained by inverting the clock from the oscillator 12a and the signal from the PWM comparator 16b, and outputs the second drive signal to the N-type FET Qnl via the driver 18b and the terminal DRV2.
• the PWM comparator 16a, the NAND circuit 17c, and the dryno 18a drive the P-type FETQpl so that the current flows through the discharge tube 3 with a pulse width corresponding to the current flowing through the discharge tube 3 within a half period of the triangular wave signal.
• Subtractor 19, PWM comparator 16b, NAND circuit 17d, and driver 18b have approximately the same pulse width as the first drive signal and a phase difference of approximately 180 degrees, and discharge in the opposite direction to the time when the first drive signal is generated.
• the charge / discharge pulse current generation circuit 20 switches the positive and negative current values when the duty cycle is 50% (or near 50%), and the absolute values of the positive and negative current values are equal.
• the frequency of the synchronous noise voltage signal is converted into a pulse current having a frequency divided by two and superimposed on the triangular wave signal of the oscillator 12a.
• the signal generator generates the first drive signal and the second drive signal in synchronization with the frequency obtained by dividing the pulse current from the charge / discharge pulse current generation circuit 20 by two. That is, the oscillation frequency is synchronized with the half frequency of the synchronous pulse voltage signal, and the lighting frequency of the discharge tube 3 is synchronized with the half frequency of the synchronous pulse voltage signal.
• FIG. 7 is a circuit diagram showing a configuration of a charge / discharge pulse current generation circuit provided in the discharge tube lighting device according to Embodiment 1 of the present invention.
• Charge / discharge pulse current generator circuit 20 T-type flip A series circuit of flop circuit T—FF, resistor R6 and resistor R7 connected between power supply REG and ground GND, power supply REG is connected to the + terminal via resistor R6, and reference voltage V2 is connected to one terminal Comparator COMP1 connected, Comparator COMP2 with one terminal connected to ground GND via resistor R7 and reference voltage V3 connected to the + terminal, OR circuit OR1, NAND circuit NAND1, AND circuit AND1 A constant current source 21a, a P-type FET 22, a constant current source 21b and an N-type FET 23 connected between the power supply REG and the ground GND.
• V2 and the reference voltage V3 are set so as to satisfy the relationship of V3 ⁇ (REG voltage) X R7 / (R6 + R7) ⁇ V2.
• the T-type flip-flop circuit T-FF is the Q of the pulse signal T FF, which is alternately repeated between the H level and the L level at every rising edge of the synchronous pulse voltage signal TRI, and inverted. Generate a pulse signal.
• this no-less signal and the inverted no-less signal are signals obtained by dividing the frequency of the synchronous noise voltage signal TRI by two.
• Comparator COMP1 outputs an H level when synchronization pulse voltage signal TRI is equal to or higher than reference voltage V2, and in the example shown in FIG. 8, the same signal as that of synchronization pulse voltage signal TRI is output to OR circuit OR1. Is done.
• the comparator COMP2 outputs an L level when the synchronization pulse voltage signal TRI is equal to or higher than the reference voltage V3.
• a signal obtained by inverting the synchronization pulse voltage signal TRI is output to the OR circuit OR1. For this reason, the output of the off circuit OR1 is always H level.
• NAND circuit NAND1 performs a NAND operation on the Q of the pulse signal T-FF from the T-type flip-flop circuit T-FF and the output of the OR circuit OR1, so the pulse from the T-type flip-flop circuit T-FF Signal T—A signal obtained by inverting Q of FF is output to the gate of P-type FET22. It is. Therefore, from time tl to t2, the P-type FET 22 is turned on by the L level from the NAND circuit NAND1, and the pulse current + ⁇ I from the constant current source 22a passes through the P-type FET 22 in the positive direction (
• the N-type FET 23 is turned on by the H level from the AND circuit AND1, and the pulse current ⁇ flows into the ground GND from the negative direction () through the N-type FET 23.
• the charge / discharge pulse current generation circuit 20 shown in FIG. 7 switches the synchronous noise voltage signal TRI between positive and negative current values Sat ⁇ ⁇ with a duty of 50%, as shown in FIG. Is converted to a pulse current having a frequency that is equal to the absolute value of the current value soil ⁇ 2 and having a frequency obtained by dividing the frequency of the synchronous noise voltage signal by 2, and is superimposed on the triangular wave signal of the oscillator 12a.
• the oscillator 12a charges and discharges the capacitor C2 by the constant current 12 arbitrarily set by the constant current determining resistor R2, and generates the triangular wave signal CF having the same rising slope and falling slope.
• the clock CK is generated based on the triangular wave signal CF.
• the clock CK is a pulse signal synchronized with the triangular wave signal, for example, having a rising period of H level and a falling period of L level.
• the NAND circuit 17c outputs an L level pulse signal to the P-type FET Qpl and turns it on only when the clock CK from the oscillator 12a is at H level and the signal from the PWM comparator 16a is at H level. . That is, when the error voltage FBOUT from the error amplifier 15 is equal to or higher than the triangular wave signal CF during the rising period of the triangular wave signal CF (clock CK is H level, for example, time tl to t3, t5 to t7) (from the PWM converter 16a).
• the subtracting circuit 19 generates an inverted waveform of the error voltage FBOUT obtained by inverting the error voltage FBOUT from the error amplifier 15 at the midpoint potential between the upper limit value and the lower limit value of the triangular wave signal. Output to the terminal.
• the logic circuit 17d outputs an H level pulse signal to the N-type FETQnl only when the inverted output of the clock CK (L level) from the oscillator 12a is H level and the signal from the PWM comparator 16b is H level. And turn it on.
• H level pulse signal is output to N-type FETQnl. That is, the pulse signal is sent to the terminal DRV2 only during the falling period of the triangular wave signal CF.
• the control ICla uses the first drive signal and the second drive signal having substantially the same panoramic width as that of the first drive signal and having a phase difference of about 180 degrees to cause the rising and falling periods.
• P-type FETQpl and N-type FETQn 1 are turned on / off alternately at the frequency of the triangular wave signal CF with the same slope period to supply power to the discharge tube 3 and to set the current flowing through the discharge tube 3 to a predetermined value. Control.
• the oscillator 12a charges and discharges the capacitor C2 by the constant current 12 arbitrarily set by the constant current determining resistor R2, and generates the triangular wave signal CF having the same rising slope and falling slope.
• the charge / discharge current of capacitor C2 is 50% duty and positive / negative current value ⁇ 12 is switched and the absolute value of positive / negative current value ⁇ 12 is equal.
• Charge / discharge pulse current generation As shown in FIG.
• the circuit 20 switches the synchronous noise voltage signal TRI from the positive and negative current value soil ⁇ when the duty is 50% and the positive and negative current value soil ⁇ are equal in absolute value and synchronous
• the voltage signal is converted to a pulse current having a frequency divided by two and superimposed on the triangular wave signal of the oscillator 12a.
• the charging / discharging current of the capacitor C2 is as shown in FIG. From time tl to t3, + 12— ⁇ , from time t3 to t4, + 12 + ⁇ , from time t4 to t6, ⁇ 12 + ⁇ , and time from! Jt6 to t7, ⁇ 12— ⁇ . For this reason, the triangular wave signal CF changes according to the charge / discharge current of the capacitor C2, and becomes a signal synchronized with the frequency of the pulse current.
• the charging / discharging current of the oscillator 12a determined by the current value determining resistor R2 is ⁇ 12
• the oscillation frequency when the charging / discharging current of the oscillator 12a is determined only by ⁇ 12 is f.
• the frequency can be synchronized. Conversely, if f is set to around 50kHz,
• the current value ⁇ may be determined by R2 so that the current value ⁇ of the pulse current is always the same ratio as the fixed force 12.
• the semiconductor integrated circuit la may have a terminal for independently determining ⁇ I so that the current value ⁇ ⁇ can be adjusted independently! /.
• the charge / discharge pulse current generation circuit 20 switches the positive / negative current value of the synchronous noise voltage signal with a duty of 50% and the absolute value of the positive / negative current value.
• the value is converted to a Norse current having the same frequency and the frequency of the synchronous Norse voltage signal divided by 2 and superimposed on the triangular wave signal.
• the signal generation unit generates the first drive signal and the second drive signal in synchronization with the frequency obtained by dividing the pulse current by two.
• the oscillation frequency is synchronized with the frequency obtained by dividing the frequency of the synchronous noise voltage signal by 2
• the discharge The lighting frequency of tube 3 is synchronized with the frequency obtained by dividing the frequency of the synchronous noise voltage signal by two. Therefore, synchronization is possible regardless of whether the frequency of the synchronizing pulse voltage signal is high or low with respect to the oscillation frequency of the oscillator 12a, and the frequency band of the synchronizing pulse voltage signal can be widened. It is possible to synchronize the oscillation frequency.
• FIG. 11 is a circuit diagram showing a configuration of a discharge tube lighting device according to Embodiment 2 of the present invention.
• FIG. 12 is a circuit diagram showing a configuration of a charge / discharge pulse current generation circuit provided in the discharge tube lighting device according to Embodiment 2 of the present invention.
• the charging / discharging pulse current generation circuit 20a generates the pulse current of the synchronous pulse voltage signal TRI having a duty of 50% from the microcomputer with the same absolute value of the positive and negative current values with the duty being 50%. And superimposed on the charge / discharge current of oscillator 12a.
• the signal generation unit generates the first drive signal and the second drive signal in synchronization with the frequency of the pulse current from the charge / discharge pulse current generation circuit 20a.
• the oscillation frequency is synchronized with the frequency of the synchronization pulse voltage signal
• the lighting frequency of the discharge tube 3 is synchronized with the frequency of the synchronization pulse voltage signal.
• FIG. 12 is a circuit diagram showing a configuration of a charge / discharge pulse current generation circuit provided in the discharge tube lighting device according to Embodiment 2 of the present invention.
• the charge / discharge pulse current generation circuit 20a deletes the T-type flip-flop circuit TFF, the OR circuit OR1, the NAND circuit NAND1, and the AND circuit AND1 from the charge / discharge pulse current generation circuit 20 shown in FIG.
• Comparator COMP 1 is changed to comparator COMP3, the output of comparator COMP3 is connected to the gate of P-type FET22, and the output of comparator COMP2 is connected to the gate of N-type FET23.
• the comparator COMP3 has the + terminal and one terminal opposite to the comparator COMP1.
• FIG. 12 is the same as the configuration shown in FIG. 7, and the same components are denoted by the same reference numerals and description thereof is omitted.
• the comparator COMP3 outputs an L level when the synchronization pulse voltage signal TRI is equal to or higher than the reference voltage V2.
• the signal power obtained by inverting the synchronization pulse voltage signal TRI is output to the Sp-type FET22.
• the comparator COMP2 outputs an H level when the synchronization pulse voltage signal TRI is less than the reference voltage V3. In the example shown in FIG.
• a signal obtained by inverting the synchronization pulse voltage signal TRI is output to the N-type FET 23.
• the charge / discharge pulse current generation circuit 20a shown in FIG. 12 generates a synchronous pulse voltage signal TRI with a duty of 50% and a positive / negative current value with a duty of 50%. It is converted into a pulse current with the same absolute value of ⁇ and superimposed on the triangular wave signal of oscillator 12a.
• the charging / discharging current of the oscillator 12a determined by the current value determining resistor R2 is ⁇ 12
• the oscillation frequency when the charging / discharging current of the oscillator 12a is determined only by ⁇ 12 is f.
• fmax f X (12+ ⁇ ⁇ ) / ⁇ 2
• the area can be expanded in both the upper and lower directions.
• FIG. 14 is a timing chart showing the signals of the respective parts when the synchronous noise voltage signal is input to the discharge tube lighting device according to the second embodiment of the present invention. Since it is the same as the operation of the timing chart shown in FIG.
• FIG. 15 is a timing chart showing the signals of the respective parts when the synchronous noise voltage signal is not input to the discharge tube lighting device according to Embodiment 3 of the present invention.
• Figure 16 shows the realization of the present invention.
• 10 is a timing chart showing signals at various parts when a synchronous noise voltage signal is input to the discharge tube lighting device according to Example 3.
• FIG. The basic circuit configuration is the same as that of the discharge tube lighting device shown in FIG. 6.
• the timings of the clock CK and the triangular wave signal CF from the power oscillator 12a are different from those shown in FIG.
• the clock CK is synchronized with the triangular wave signal CF, and the triangular wave signal CF is at the H level during the period below the midpoint potential between the upper limit value VH and the lower limit value VL.
• the pulse voltage waveform in which the period above the midpoint potential is at the L level.
• the NAND circuit 17c outputs the L level pulse signal to the P-type FET Qpl and turns it on only when the clock CK from the oscillator 12a is at H level and the signal from the PWM comparator 16a is at H level. . That is, when the triangular wave signal CF is lower than the midpoint potential between the upper limit value and lower limit value (clock CK is at the H level) and the error voltage F BOUT from the error amplifier 15 is equal to or higher than the triangular wave signal CF. (The signal from the PWM converter 16a is H level, for example, from time t6 to t7, tl l to tl2) L level pulse signal power is output to the ⁇ type FETQpl. That is, the pulse signal is output to the terminal DRV1 only during the period when the triangular wave signal CF is lower than the midpoint potential between the upper limit value and the lower limit value.
• the subtraction circuit 19 generates an inverted waveform of the error voltage FBOUT obtained by inverting the error voltage FBOUT from the error amplifier 15 at the midpoint potential between the upper limit value and the lower limit value of the triangular wave signal. Output to the terminal.
• the logic circuit 17d outputs an H level pulse signal to the N-type FET Qnl only when the inverted output of the clock CK (L level) from the oscillator 12 is H level and the signal from the PWM comparator 16b is H level. Turn it on
• the triangular wave signal CF inverts the error voltage FBOUT from the error amplifier 15 while the triangular wave signal CF is above the midpoint potential between the upper limit value and the lower limit value (clock CK is at L level).
• clock CK is at L level.
• the H level pulse signal is output to the N-type FET Qnl. That is, the pulse signal is sent to the terminal DRV2 only during the period when the triangular wave signal CF is above the midpoint potential between the upper limit value and the lower limit value.
• the current flowing through the discharge tube 3 is predetermined. Can be controlled to a value.
• the operation of the timing chart shown in FIG. 16 also operates in the same manner as the operation of the timing chart shown in FIG. That is, the charging / discharging current of the capacitor C2 is the same as that shown in FIG. 10, and the triangular wave signal CF changes according to the charging / discharging current of the capacitor C2, and becomes a signal synchronized with the frequency of the pulse current. As a result, the oscillation frequency can be synchronized to half the frequency of the synchronous nores voltage signal.
• FIG. 17 is a timing chart showing signals at various parts when a synchronous noise voltage signal is input to the discharge tube lighting device according to Embodiment 4 of the present invention. Note that the operation waveforms when no sync signal is input are exactly the same as those shown in FIG.
• the basic circuit configuration is the same as that of the discharge tube lighting device shown in FIG. 11, and the timings of the clock oscillator CK and the triangular wave signal CF are different from those shown in FIG.
• the current flowing through the discharge tube 3 can also be controlled to a predetermined value by the control by the discharge tube lighting device of the fourth embodiment.
• the oscillation frequency can be synchronized with the frequency of the synchronous noise voltage signal with a duty of 50%.
• FIG. 18 is a circuit diagram showing a configuration of a discharge tube lighting device according to Embodiment 5 of the present invention.
• the discharge tube lighting device shown in Fig. 18 is an example of a discharge tube lighting device in the case of a full-bridge circuit, and the control IClc has a P-type FETQp2, N-type FETQn 2 compared to Example 1 shown in Fig. 6.
• a series circuit of a high-side P-type FETQp2 and a low-side N-type FETQn2 is connected between the DC power supply Vin and the ground.
• a series circuit of the resonant capacitor C3 and the primary winding P of the transformer T is connected between the connection point of P-type FETQpl and N-type FETQnl and the connection point of P-type FETQp2 and N-type FETQn2.
• Terminal DRV1 is connected to the gate of P-type FETQpl and the gate of N-type FETQnl
• terminal DRV2 is connected to the gate of P-type FETQp2 and the gate of N-type FETQn2.
• the logic circuit 17e includes an output obtained by inverting the clock CK from the oscillator 12a and a PWM comparator. NAND with the signal from the 16b.
• the dead time creation circuit 21a creates a third drive signal DRV3 having a predetermined time dead time DT for the first drive signal DRV1 to the driver 18a based on the signal from the NAND circuit 17c and outputs the third drive signal DRV3 to the driver 18b.
• the dead time creation circuit 21b creates a second drive signal DRV2 having a predetermined dead time DT for the fourth drive signal DRV4 to the driver 18c based on the signal from the logic circuit 17e and outputs the second drive signal DRV2 to the driver 18c. .
• the first drive signal, the third drive signal, the second drive signal, and the fourth drive signal are the third drive signal except for the force S having a dead time DT that prevents them from turning on simultaneously, and the dead time DT.
• the drive signal is substantially the same as the first drive signal
• the fourth drive signal is substantially the same as the second drive signal.
• the charge / discharge pulse current generation circuit 20a has the same configuration as the circuit shown in FIG.
• the L level noise signal is converted to the dead time generation circuit 21a and the driver 18a, It is output to P-type FETQpl and N-type FETQnl via 18b, and P-type FETQpl turns on.
• an H level pulse signal is output to the P-type FETQp2 and N-type FETQn2 via the dead time creation circuit 21b and the drivers 18c and 18d, and the N-type FETQn2 is turned on.
• current flows along the path extending along Vin, Qpl, C3, P, Qn2, and GND, and on the secondary side of the transformer, along the S, Lr, discharge tube 3, and tube current detection circuit 5. Current flows through the extended path.
• the H level signal is output to the P-type FETQpl and the N-type FETQnl via the dead time generator circuit 21a and the drivers 18a and 18b. FETQnl turns on.
• an H level panelless signal is output to the logic circuit 17e, and the logic circuit 17e L level is output to P-type FETQp2 and N-type FETQn2 via the creation circuit 21b and drivers 18c and 18d, and P-type FETQp2 is turned on.
• FIG. 19 is a timing chart showing a signal of each part when a synchronous noise voltage signal is input to the discharge tube lighting device according to Embodiment 5 of the present invention. Except for the dead time DT of the fourth drive signal, the operation is the same as the operation of the timing chart shown in FIG. Therefore, the discharge tube lighting device according to the fifth embodiment using the full bridge circuit can achieve the same effect as the discharge tube lighting device according to the first embodiment.
• discharge tube lighting device of the present invention is not limited to the above-described embodiments.
• the second drive signal has a complete phase difference of 180 degrees from the first drive signal.
• the phase difference is A slight error, for example, 179 degrees, 181 degrees, etc., may be used with respect to 180 degrees, which is completely 180 degrees.
• the noise current is a complete rectangular wave, but the duty cycle is 50% and the positive and negative waveforms are switched, and the positive and negative waveforms have a phase difference of 180 degrees. If they are equal, they do not have to be a perfect square wave.
• the duty is 50%
• the positive and negative are switched, and a pulse voltage with the same positive and negative absolute value with respect to the midpoint potential of the triangular wave signal is connected to the capacitor C1 through a resistor, so that the charge / discharge current of the oscillator 12a is A method may be used in which a positive or negative polarity is switched at 50%, and a similar Norse current with the same absolute value is superimposed.
• the symmetry of the current flowing through the discharge tube is not greatly broken! /, As long as it falls within the category, the pulse current may not have a duty of just 50%. Also, there may be some error in the absolute polarity of the positive current.
• synchronization is possible regardless of whether the frequency of the synchronizing pulse voltage signal is high or low with respect to the oscillation frequency of the oscillator, and the frequency band of the synchronizing pulse voltage signal can be widened.
• the oscillation frequency can be synchronized with the voltage signal.
• the present invention relates to a frequency synchronization method for a discharge tube lighting device, a discharge tube lighting device, and a semiconductor. It can be applied to a body integrated circuit.

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• 2006
  • 2006-10-05 JP JP2006274214A patent/JP2008091306A/ja active Pending
• 2007
  • 2007-09-10 WO PCT/JP2007/067611 patent/WO2008044413A1/ja not_active Ceased
  • 2007-09-10 KR KR1020097009381A patent/KR101069360B1/ko not_active Expired - Fee Related
  • 2007-09-10 CN CN200780036795XA patent/CN101523994B/zh not_active Expired - Fee Related
  • 2007-09-10 US US12/302,617 patent/US8049435B2/en not_active Expired - Fee Related
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• 2011
  • 2011-06-08 US US13/156,008 patent/US20110235383A1/en not_active Abandoned

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