WO2008023660A1 - Procédé de conception d'un modèle de masque et procédé de fabrication d'un dispositif semi-conducteur comprenant ce dernier - Google Patents

Procédé de conception d'un modèle de masque et procédé de fabrication d'un dispositif semi-conducteur comprenant ce dernier Download PDF

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WO2008023660A1
WO2008023660A1 PCT/JP2007/066108 JP2007066108W WO2008023660A1 WO 2008023660 A1 WO2008023660 A1 WO 2008023660A1 JP 2007066108 W JP2007066108 W JP 2007066108W WO 2008023660 A1 WO2008023660 A1 WO 2008023660A1
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Prior art keywords
pattern
cell
region
cells
mask pattern
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PCT/JP2007/066108
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English (en)
Japanese (ja)
Inventor
Hirokazu Nosato
Tetsuaki Matsunawa
Eiichi Takahashi
Hidenori Sakanashi
Tetsuya Higuchi
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National Institute Of Advanced Industrial Science And Technology
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Priority to JP2008530891A priority Critical patent/JP4714930B2/ja
Publication of WO2008023660A1 publication Critical patent/WO2008023660A1/fr

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Definitions

  • the present invention relates to a mask technology for photolithography, and more particularly to a mask pattern design technology for forming a pattern smaller than the exposure wavelength of photolithography and a semiconductor device manufacturing technology using the same. is there.
  • a semiconductor device is an optical lithography that irradiates a mask, which is an original plate on which a circuit pattern is drawn, with exposure light, and transfers the pattern onto a semiconductor substrate (hereinafter referred to as “Ueno”) via a reduction optical system. It is mass-produced by repeatedly using the Yae process!
  • OPC optical proximity correction
  • the genetic algorithm is a search method using population genetics as a model, and is known to have excellent performance such as high optimization performance without depending on the target problem.
  • References to the genetic algorithm include, for example, David E. Goldberg (David E.), published by ADISON — WESLEY PUBLISHING COMPANY, INC. In 989. Goldberg's genetic 'algorithms in search, optimization, and machine learning patent ⁇
  • the method for optimizing the OPC was described in Japanese Patent No. 3512954 (Patent Document 4).
  • a solution candidate of a search problem is expressed by a bit string called a chromosome, and a character string operation is performed on a group consisting of a plurality of chromosomes to make a survival competition.
  • Each chromosome is evaluated by an objective function, which is the search problem itself, and the result is calculated as a fitness value that is a scalar value.
  • a chromosome with high fitness is given the opportunity to leave many offspring.
  • crossovers are made between chromosomes within a group, and mutations are made to generate new chromosomes. By repeating such a process, a chromosome with a higher fitness is generated, and the chromosome with the highest fitness is the final solution.
  • Patent Document 5 describes a method of changing a figure for each portion that is not in the entire mask layout. The procedure is as follows. For each target cell included in the design layout data, an environmental profile expressed in a specific format is determined depending on whether or not there are other shapes around the target cell. decide. Then, referring to the cell replacement table, the replacement cell name, which is the name of the correction pattern to be replaced corresponding to the determined environment profile, is read out, and after the correction, layout data is generated. Finally, the correction pattern corresponding to the read replacement cell name is extracted from the cell library, and mask data that has been corrected is generated.
  • Patent Document 6 Japanese Unexamined Patent Application Publication No. 2006-058413
  • 2005-156606 Japanese Unexamined Patent Application Publication No. 2005-156606.
  • Patent Document 7 a dangerous location that is likely to cause a short circuit failure or an open failure in the actual lithographic process is obtained by optical simulation of the entire chip, and measurement points are arranged around the dangerous location. Techniques for adjusting OPC figures by simulating only the periphery in more detail are disclosed.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2002-303964
  • Patent Document 2 Japanese Patent Laid-Open No. 2001-281836
  • Patent Document 3 Japanese Patent Application Laid-Open No. 2004-0661720
  • Patent Document 4 Japanese Patent No. 3512954
  • Patent Document 5 Japanese Patent Laid-Open No. 2002-328457
  • Patent Document 6 Japanese Unexamined Patent Application Publication No. 2006-058413
  • Patent Document 7 Japanese Unexamined Patent Publication No. 2005-156606
  • Non-Patent Document 1 David E. Goldberg, Genetic Algorithms in Search, Optimization, and 'Machine' Learning (Genetic Algorithms in Search, Optimization, and Machine) Learning), / Einno 'Wasele PUBLISHING COMPANY, IN C.' 1989
  • Non-patent document 2 Puneet Gupta, Fook-Luen Heng and Mark Lavin, Merit bu Senolewise Modenole-based OP C Design and Process Integration for Microelectronics Edited by Lars W. Liebmann, Merits of Cellwise Model-Based OPC Design and Process Integration for Microelectronic Manufacturing II, edited by Lars W. Liebmann, Proceedings of S.P. ⁇ (Proc. Of SPIE) Vol.5379, 2004
  • Non-Patent Document 3 Xin Wang, et al., Etasprouting, hire rachikanole structure, toenhas, senore base, areno lay with low power, risen OPC, recon figure, design and process integration, for microelectronics Exploiting hierar chical structure to enhance cell-oased RE with localized OPC reconriguration, De sign and Process Integration for Microelectronic Manufacturing III), edited by Lars W. Liebmann, Proceeding of S ⁇ Pee I'i (Proceedings of SPIE) Vol.5756, 2005
  • Patent Document 5 determines the optimum correction pattern to be replaced for all possible environmental profiles for the correction target cell, and determines each correction pattern. Given a replacement cell name, the environment profile and the replacement cell name must be associated and stored in the cell replacement table in advance, which requires a large amount of storage space that requires a large amount of preparation costs. There's a problem.
  • the EDA tool such as the HALO-OPC described above adopts a method in which OPC processing is performed only on the surrounding area when corrections are made to the mask layout data that has been processed by OPC.
  • OPC processing is performed only on the surrounding area when corrections are made to the mask layout data that has been processed by OPC.
  • the consistency with the design is inferior because it is not processed in units of cells.
  • the fidelity degradation called hot spot during pattern transfer may occur. Since it is easy to bend, there is a problem that a high calculation cost is required for the processing that is precisely obtained by the verification tool after the OPC processing at the place where the possibility of short circuit or disconnection is high.
  • An object of the present invention is to provide a mask pattern design method that realizes a reduction in OPC processing time.
  • Another object of the present invention is to provide a method that enables generation of a mask pattern in a practical time and shortens the manufacturing period of a semiconductor device.
  • Still another object of the present invention is to provide a mask pattern design method capable of reducing the manufacturing cost of a semiconductor device.
  • the mask pattern design method of the present invention adjusts the OPC correction amount of the plurality of cells after designing a mask pattern by arranging a plurality of cells subjected to OPC processing included in the library. Including steps,
  • Each of the plurality of cells is a
  • Information on a first region that is directed inward from the cell boundary of the cell and may be affected by shape change from other cells arranged around the cell;
  • the correction amount of the OPC is adjusted for a region where the first region and the second region of cells adjacent to each other overlap among the plurality of cells.
  • a mask pattern is designed by arranging a plurality of cells subjected to OPC processing included in a library, and then the correction amount of the OPC of the plurality of cells is adjusted. And thereafter, exposing the mask pattern to transfer the pattern onto the semiconductor wafer,
  • Each of the plurality of cells is a
  • Information on a first region that is directed inward from the cell boundary of the cell and may be affected by shape change from other cells arranged around the cell;
  • the correction amount of the OPC is adjusted for a region where the first region and the second region of cells adjacent to each other overlap among the plurality of cells. .
  • the manufacturing device manufacturing TAT can be shortened. As a result, it is possible to reduce the manufacturing cost of semiconductor devices.
  • FIG.1 Used in the SRAM gate to which the study example is applied to verify the effectiveness of the study example. It is a top view which shows V and a mask pattern.
  • FIG. 12 is a partially enlarged plan view of the mask pattern shown in FIG.
  • FIG. 13A is a plan view showing a transfer pattern of the mask pattern shown in FIG. 2
  • FIG. 13B is a plan view showing the transfer pattern of the mask pattern shown in FIG.
  • Sono 15 is a plan view showing the mask pattern used for verification of the study example.
  • FIG. 16 is a partially enlarged plan view of the transfer pattern of the mask pattern shown in FIG.
  • FIG. 18 is a diagram showing an example of chromosome expression used in the OPC processing method of the examination example.
  • FIG. 19A is a diagram showing a symbol of a NAND gate
  • FIG. 19B is a circuit diagram of the NAND gate
  • FIG. 19C is a plan view showing a pattern layout of the NAND gate.
  • FIG. 20 is a plan view showing a unit logic cell and a broken line defining a cross section in the NAND gate pattern layout shown in FIG. 19 (c).
  • FIG. 21 (a) to (f) are diagrams showing mask patterns used in forming the unit logic cell portion shown in FIG.
  • FIG. 22] (a) to (e) are cross-sectional views showing the steps up to the element isolation step in the order of steps.
  • FIG. 23] (a) to (e) are cross-sectional views showing steps up to channel formation in the order of steps.
  • FIG. 24 (a) to (e) are cross-sectional views showing steps up to the formation of a part of the wiring.
  • FIG. 25 is a block diagram showing a pattern of the mask shown in FIG. 21 (d).
  • FIG. 26 is a diagram showing an example in which a differential dimension from the design target in FIG. 25 is expressed as a gene.
  • FIG. 27 is a diagram showing an example in which cells are grouped based on relative positions.
  • FIG. 29 A diagram showing a difference image between a design pattern and a resist pattern.
  • FIG. 30 is a diagram showing a manufacturing process flow of a semiconductor device.
  • FIG. 31 is a plan view showing cells of a cell library that has been subjected to OPC processing for a single cell.
  • FIG. 32 is an enlarged view of an essential part of the cell shown in FIG. 31.
  • FIG. 34 is a diagram showing an example of an adjustment variable for the alignment margin between the outer contour and the diffusion layer.
  • FIG. 35 is a diagram illustrating an example of resolution failure avoidance between adjacent cells.
  • FIG. 36 is a diagram showing an example of avoiding failure of a gate wiring on a diffusion layer.
  • This figure shows the gate length, the resolution avoidance failure between adjacent cells (pattern connection failure) avoidance margin, the gate wiring failure failure avoidance allowance to the diffusion layer, and the re-OPC adjustment part of the protruding amount from the active region.
  • FIG. 38 (a) and (b) are diagrams showing examples of gate length adjustment variables.
  • FIG. 39 is a diagram illustrating an example of resolution failure avoidance between adjacent cells.
  • FIG. 40 is a diagram illustrating an example of avoiding failure of a gate wiring on a diffusion layer.
  • FIG. 41] (a) to (c) are diagrams showing examples of protrusion correction from an active region.
  • FIG. 42 is a diagram showing a layout example of a contact layer.
  • FIG. 43 is a diagram showing an example of contact pattern adjustment variables.
  • FIG. 44 is a graph showing the relationship between the intensity of a diffraction pattern and 2 ⁇ X ⁇ ⁇ ⁇ / ⁇ .
  • FIG. 45 is a diagram showing the adjustable regions of four types of cells with the OPC figure shape adjusted.
  • FIG. 46 is a diagram showing an evaluation area of the cell shown in FIG. 45.
  • FIG. 47 is a diagram showing the maximum value, the minimum value, and the average value of the line width variation in the evaluation region shown in FIG. 46 as a ratio.
  • FIG. 48 is a diagram showing an adjustable region when a part of the cell shown in FIG. 45 is replaced with another cell.
  • FIG. 49 is a diagram showing an evaluation region of the cell shown in FIG. 48.
  • Fig. 50 is a diagram showing the measurement results of line width fluctuations that occur due to changing the cell for each evaluation area.
  • FIG. 52 (a) and (b) are schematic views showing a data structure of a cell.
  • FIG. 53 is a schematic diagram showing an example of a design pattern of an OPC-treated cell in a mask design process which is a manufacturing process of a semiconductor device according to an embodiment of the present invention.
  • FIG. 54 is a layout plan view showing an adjustable region and a fixed region in the cell of FIG. 53.
  • FIG. 55 is a schematic diagram showing the surrounding area of the cell of FIG. 53.
  • En] 56 is a schematic diagram showing the adjustable region and surrounding region of the cell in FIG. 53 superimposed.
  • FIG. 57 is a schematic diagram showing that the width power of the surrounding area is smaller than the width of the adjustable area!
  • FIG. 58 is a plan view of a mask pattern layout in the process of mask pattern design.
  • FIG. 59 is a layout plan view of a mask pattern in which an adjustable region and a surrounding region are added to each cell during fine adjustment of the mask pattern.
  • FIG. 60 is an enlarged layout plan view of the main part of FIG.
  • this study example 1 was applied to one of the mask patterns used for the SRAM (Static RAM) gate shown in Fig. 1 as a cell.
  • FIG. 2 to 11 show the mask patterns P;! To P10 used in this verification experiment. These ten mask patterns P1 to P10 are designed with a width of 90 nm, so the ideal line width is 90 nm. In this experiment, these transfer patterns were created, and the two values of line width (S31) and gap (S32) shown in Fig. 12 (enlarged view of region S12 shown in Fig. 1) were compared as evaluation values. The impact of the surrounding environment was verified.
  • the transfer pattern is generated by optical simulation software. As such software, for example, “SOLID-C” of RISOTECH JAPAN is well known to those skilled in the art (reference URL; http: ⁇ www.ltj.co.jp/index.html>).
  • Table 2 shows two evaluation values of the transfer patterns of the mask patterns P;! To P10.
  • FIG. 13 (a) shows an ideal transfer pattern of the mask pattern P1.
  • Fig. 13 (b) shows the transfer pattern of mask pattern P3, which has the greatest effect. It can be seen that the pattern P3 is greatly influenced by the entire line width (S31) and the gap (S32).
  • S31 line width
  • S32 gap
  • verification experiment 1 was carried out to see if it could be solved by the method of this study example 1.
  • verification experiment 1 A simulation was performed to optimize the mask pattern P3 (Fig. 14), which had the most impact on the N / A, and the target to be the closest to the ideal! / Mask pattern P1 (Fig. 15).
  • the optimization by the method of this study example 1 was performed using the two locations (S71 and S72) in the cell shown in Fig. 16 (enlarged view of the transfer pattern of region S12 shown in Fig. 1) as optimization parameters. was made.
  • FIG. 17 is a flowchart showing the most basic calculation procedure of the genetic algorithm.
  • Initialization A plurality of chromosomes as solution candidates are randomly generated to form a group.
  • the optimization problem to be solved is expressed as an evaluation function that returns a scalar value.
  • Chromosome evaluation The evaluation function is used to evaluate the chromosome, and the fitness of each chromosome is calculated. Generation of next-generation populations: Using genetic manipulation (selection, crossover, mutation), gives chromosomes with higher fitness the opportunity to leave more offspring.
  • Determination of search end criteria Repeat evaluation of chromosomes and generation of next generation population until a predetermined condition is satisfied.
  • FIG. 18 shows an example of a chromosome.
  • Ai a set of integers, a range of real values, symbol strings, etc. are used according to the nature of the problem to be solved.
  • “Initial chromosome population generation” usually generates N chromosomes randomly according to the rules defined in “Definition of chromosome expression”. This is because the characteristics of the optimization problem to be solved are unknown, and what kind of chromosome is superior is completely unknown. However, if there is some a priori knowledge about the problem, the search speed and accuracy may be improved by generating a chromosome population centering on the region that is predicted to have high fitness in the solution space. is there.
  • chromosome evaluation the fitness of each chromosome in a population is calculated based on the method defined in “determination of evaluation function”!
  • the chromosome population is genetically manipulated based on the fitness of each chromosome to generate the next generation chromosome population. As a typical procedure for genetic manipulation
  • a chromosome with high fitness is extracted from the chromosome population of the current generation, left in the next generation population, and conversely, a chromosome with low fitness is removed.
  • Cross is an operation that creates a new chromosome by randomly selecting a pair of chromosomes with a predetermined probability from a group of chromosomes extracted by selection and recombining part of those genes.
  • a chromosome is randomly selected with a predetermined probability from the chromosome group extracted by selection, and the gene is changed with a predetermined probability with a predetermined probability.
  • the probability of sudden mutation is called the mutation rate.
  • search end criterion determination it is checked whether or not the generated next-generation chromosome population satisfies the criterion for ending the search. If the criterion is satisfied, the search is terminated, and the chromosome having the highest fitness in the chromosome population at that time is determined as the solution to the optimization problem to be obtained. If the termination condition is not satisfied, return to the “chromosome evaluation” process and continue the search.
  • the end criterion of the search process depends on the nature of the optimization problem to be solved, but the maximum fitness in the representative ⁇ chromosome population is greater than a certain threshold. (b) The average fitness of the entire chromosome population became larger than a certain threshold.
  • Step (1) Reconstruct a graphic pattern using a variable vector uniquely determined from the chromosome.
  • Step (2) Perform an optical simulation to calculate an exposure pattern.
  • Step (3) For the calculated exposure pattern, the line width (S31) and gap (S3
  • Step (4) Since the goal here is to obtain an exposure pattern that is as close as possible to the design value, the smaller the error, the better. Therefore, the reciprocal of the sum of the measured errors is set as the fitness.
  • chromosome expression a vector consisting of two real-valued elements is defined as a chromosome.
  • the number of chromosomes N is 100, and 100 chromosomes are randomly generated using a pseudo-random number generator.
  • roulette selection is used.
  • the probability that each chromosome can survive in the next generation is proportional to the fitness. In other words, the higher the fitness, the more the arrangement on the roulette, and the greater the probability of hitting the roulette.
  • the size of the chromosome population is N
  • the fitness of the i-th chromosome is Fi
  • the sum of the fitness of all chromosomes is ⁇
  • each chromosome is extracted with a probability of (Fi ⁇ ⁇ ). This is realized by repeating the procedure N times.
  • the number of chromosomes is 100, 100 generations of 100 chromosomes are selected by repeating 100 times.
  • uniform crossover is used.
  • This is a method in which two chromosomes are selected from each chromosome group, and at each locus, whether or not to replace a variable that is a gene is determined randomly.
  • the first random number is for the first locus. If it is 1, X 1 and X 2 are exchanged. If it is 0, it is not exchanged.
  • the process for the second locus is similar.
  • a process of adding random numbers generated according to the normal distribution to the loci selected with the mutation rate ⁇ ⁇ according to the uniform distribution is adopted.
  • the mutation rate ⁇ 1/50
  • the mean of normal distribution u 0
  • the standard deviation ⁇ 5 X 10'9.
  • the search is terminated when a chromosome having an error from the design value of 0 is found or when the chromosome is evaluated 5000 times.
  • FIGS. 19 (a) to 19 (c) show a two-input NAND gate circuit ND.
  • FIG. 19 (a) is a symphonor diagram
  • FIG. 19 (b) is a circuit diagram
  • FIG. 19 (c) is a pattern layout.
  • FIG. FIG. 20 is an enlarged plan view of FIG. 19 (c).
  • the portion surrounded by the alternate long and short dash line is the unit cell 110, and two nMOS portions Qn formed on the n-type semiconductor region 11In on the surface of the p-type well region PW, and n It consists of two pMOS parts Qp formed on the p-type semiconductor region 11 lp on the surface of the type well region NW.
  • FIGS. 21 (a) to (f) In order to fabricate this structure, pattern transfer by ordinary optical lithography was repeatedly used by sequentially using six types of masks M1 to M6 as shown in FIGS. 21 (a) to (f). Of these, masks M1 to M3 have a relatively large pattern, so the pattern OP C treatment was not performed.
  • reference numerals 101a, 101b, and 101c denote light transmitting portions
  • reference numerals 102a, 102b, and 102c denote light shielding portions made of a chromium film.
  • the pattern design method of the present embodiment was used to appropriately change the outline and size of the pattern figure and optimize it.
  • reference numerals 101d, 101e, and 101f denote light transmitting portions
  • reference numerals 102d, 102e, and 102f denote light shielding portions.
  • FIG. 20 showing the same layout as FIG. 19 (c)
  • the process up to the formation of the channels Qp and Qn using the cross-sectional view assuming the cross-section along the broken line is shown in FIG. 22 (a). This will be explained in sequence using ⁇ (e) and Figs. 23 (a)-(e).
  • An insulating film 115 made of, for example, a silicon oxide film is formed on the wafer S (W) made of P-type silicon single crystal by an oxidation method, and then, for example, a silicon nitride film 116 is formed thereon by CVD (Chemical Vapor). Then, a resist film 117 is formed thereon (FIG. 22 (a)). Next, an exposure and development process is performed using the mask Ml to form a resist pattern 117a (FIG. 22 (b)).
  • the insulating film 115 and the silicon nitride film 116 exposed from the resist pattern 117a are sequentially removed, and the resist pattern 117a is further removed to form a groove 118 on the surface of the wafer S (W).
  • Figure 22 (c) Next, after depositing an insulating film 119 made of, for example, silicon oxide by a CVD method or the like (FIG. 22 (d)), a planarization process is performed by, for example, a chemical mechanical polishing (CMP) method or the like. As a result, an element isolation structure SG is finally formed (FIG. 22 (e)).
  • the element isolation structure SG is a groove type isolation structure, but the present invention is not limited to this.
  • a field insulating film by a LOCOS (Local Oxidization of Silicon) method may be used.
  • a resist pattern 117b is formed by the mask M2 to form a resist pattern 117b. Since the region where the n-type well region is to be formed is exposed, phosphorus or arsenic is ion-implanted to form the n-type well region NW (Fig. 23 (a)). Similarly, after a resist pattern 117c is formed by the mask M3, for example, boron or the like is ion-implanted to form a p-type well region PW (FIG. 23 (b)).
  • a gate insulating film 120 made of a silicon oxide film is formed to a thickness of 3 nm by a thermal oxidation method, and a polycrystalline silicon film 112 is further deposited thereon by a CVD method or the like (FIG. 23 (c)).
  • a resist pattern 117d is formed using a mask M4, and a gate insulating film 120 and a gate electrode 112A are formed by etching and removing the polycrystalline silicon layer 112 (FIG. 23 (d) )).
  • channel Qp and channel Qn are formed in a self-aligned manner with respect to the gate electrode 112A (Fig. 23 (e)).
  • a 2-input NAND gate group is manufactured by appropriately selecting the wiring. Needless to say, if the shape of the wiring is changed, other circuits such as a NOR gate circuit can be formed.
  • a NOR gate circuit can be formed.
  • FIGS. 24 (a) to 24 (e) are cross-sectional views taken along the broken line shown in FIG. 20, and show a wiring formation process.
  • an interlayer insulating film 12 la made of a silicon oxide film doped with phosphorus is deposited by the CVD method (FIG. 24 (a)).
  • a resist is applied, a resist pattern 117e is formed using the mask M5, and contact holes CNT are formed by etching (FIG. 24 (b)).
  • a metal such as tungsten, tungsten alloy, or copper is embedded, and at the same time, these metal layers 113 are formed (FIG.
  • the light shielding portion 102d in the mask M4 in particular constitutes the gate pattern with the shortest dimension, and the required accuracy of the dimension of the transfer pattern is the strictest. Therefore, the cell library pattern shown in mask M4 (Fig. 21 (d)) is placed on the entire mask surface. In this case, the method of this examination example 2 was adopted.
  • the entire mask pattern is composed of a plurality of cells, and each cell has a line of I-type graphic power (see FIG. 25). As shown in the figure, each cell has 10 cells up to p-force,
  • the shaded figure is a mask pattern with OPC, and the upper and lower horizontal bars of one "I" figure are vertically symmetrical with respect to the design target indicated by the dashed line.
  • each element X of the variable vector X may be expressed as an n-ary number by determining an upper limit value and a lower limit value and a quantization step number that are not expressed as real values.
  • the optimal length search is not performed for all the variable vectors of all cells, and the lengths of chromosomes are set. It can be reduced to facilitate optimization.
  • Fig. 27 assuming that all the cells are composed of the same kind of figure pattern and the figure is bilaterally symmetric and vertically symmetric, all the variable vectors of all cells are targeted for optimization.
  • Thailand Optimize the variable vector (X 1 X 2 ... X 4 ) that defines the shape of the four cells, and classify the results into all cells by type. By applying, it is the power to obtain the same result as adjusting the entire mask.
  • cell 81 has no upper five cells on the left and eight left cells, and three cells (82, 83, 84) on the right and lower sides. .
  • cell 90 and its surrounding senores (89, 92, 91) are arranged symmetrically with respect to cell 81 and its surrounding cells (82, 83, 84), and cell 87 and its surrounding cells (88) 85, 86) are arranged vertically symmetrically. Therefore, the optimization result of the cell 81 can be used for the cell 90 and the cell 87. In this way, the adjustment adjustment process can be omitted.
  • step (3) As a method for obtaining the fitness of the chromosome, the same procedure as in the examination example 1 is adopted here. However, the dimensions in step (3) are measured at four locations (a to a) shown in Fig.
  • step (4) of fitness calculation the force that employs the reciprocal of the sum of errors as fitness may be a value subtracted from a predetermined constant. Furthermore, fitness calculation In step (2), the acid diffusion simulation is also performed, so that the resist pattern can be predicted more accurately, so that the optimization accuracy can be improved.
  • the roulette selection method is used.
  • Crossover methods such as tournament selection method and rank selection method, and generational change models such as MGG (Minimal Generation Gap) method may be used (reference: Sato et al., “Proposal of generational change models in genetic algorithms”). And Evaluation, ”Journal of Artificial Intelligence, Vol.12, No.5, 1997).
  • UNDX Unimodal Normal Distribution Crossover
  • simplet crossover EDX (Extrapolation-directed Crossover)
  • EDX Extrapolation-directed Crossover
  • the search is terminated when the error from the design value is 0 or below a certain value, or when the number of chromosome evaluations exceeds a certain value.
  • a semiconductor chip is created using a cell library that has been subjected to OPC processing in advance, and the influence of surrounding cell libraries is optimized using a genetic algorithm capable of high-speed processing. Compared to the conventional method of performing OPC processing on patterns, the processing time can be reduced to one-tenth or less.
  • This system LSI has a minimum gate width of 40 nm and a minimum pitch of 160 nm.
  • the logic circuit section allows arbitrary pitch wiring, and there is no placement restriction other than minimum spacing between cells. For this reason, it is a layout rule that can be applied to a wide variety of products that can inherit the conventional IP and have high expandability as a platform.
  • That period is the lifeline, and the value of the device, and the marketability of the product that incorporates it is also affected. If processing is preferentially performed in single wafer processing, the wafer process period is a minimum of two weeks, and the mask supply is quick. Conventionally, in order to make the generation period of the mask creation pattern to be about a practical day, it was necessary to apply rule-based OPC partially, causing problems such as a decrease in yield as described above.
  • the time required for mask pattern creation is one day, and the same force as when applying model-based OPC to the entire surface is used. Characteristics and yield could be obtained.
  • the wafer process waiting time can be reduced, and the balance with the mask supply speed can be obtained, resulting in an accelerated system LSI shipment timing.
  • FIG. Figure 30 shows the mask pattern data preparation, mask fabrication, and wafer process steps of the system LSI in the form of a flowchart.
  • the mask pattern data preparation process is shown on the left, the mask production is shown in the center, and the wafer process and timing are shown on the right.
  • the wafer process flow includes film formation, lithography, etching, insulating film filling for element isolation (isolation between active regions), CMP dummy pattern for planarization, lithography, etching, CMP Subsequently, an element isolation structure is formed. After that, lithography for ion implantation and ion implantation are performed to form a well layer, film formation for gate, lithography, etching, lithography for ion implantation separation, ion implantation, film formation for LDD, and LDD processing Then, ion implantation is performed to form a gate.
  • interlayer wiring is formed by forming an interlayer insulating film, forming an opening, depositing a conductive film, and CMP.
  • Typical critical layers are isolation, gate, contact, and first and second wiring.
  • the mask pattern OPC data is first determined whether or not it is a critical layer, and then enters a production procedure. First, preparation for necessary element isolation is performed. Next, a suitable one is extracted from an already created OPE (Optical Proximity Effect) correction cell library, and these patterns are combined to assemble the 0th-order OPC pattern. Then, based on the genetic algorithm method of Study Example 1, correction is performed in consideration of the influence of adjacent patterns to create a final OPC pattern, and a mask is manufactured based on that data. Next, pattern data and masks for the gate layer, contact layer, and wiring layer are prepared using the same method. Here, the force indicating the procedure of preparing each layer in series may be prepared in parallel.
  • OPE Optical Proximity Effect
  • the mask pattern data is prepared for the non-critical layer using another path.
  • the isolation layer which is a critical layer, is a cueing layer
  • wafer delivery is also directly delayed.
  • the completion period of mask pattern data for the isolation layer is very important.
  • the mask could be prepared in one day, together with mask production, and halved compared to the normal two days.
  • the manufacturing method of the present embodiment is particularly effective for creating a gate pattern.
  • Reference numeral 1001 in FIG. 31 denotes a cell of the target cell library, and the pattern formed in this cell has been subjected to OPC processing in advance for the single cell.
  • the peripheral area (first area) indicated by hatching is the area containing the pattern that is subject to OPC correction due to the influence of the cells arranged in the periphery
  • its width 1002 is the exposure wavelength of the exposure apparatus. It depends on ⁇ , the numerical aperture of the lens used, the acid diffusion constant of the resist used, and the standard dimensional accuracy.
  • the peripheral region is a region for correcting the influence of interference caused by the diffracted light from the patterns constituting the adjacent cells overlapping. Therefore, in order to determine the range of the peripheral area, the diffraction image intensity indicating the point image intensity distribution of the exposure optical system that projects the mask pattern is considered.
  • the influence of interference by the third-order diffraction image is negligibly small.
  • the range of influence of the change in the OPC pattern on the periphery is up to the third-order diffraction image, and it was found that sufficient accuracy can be obtained even if the peripheral region is 1.62 / NA from the edge of the cell.
  • wavelength ⁇ is 193 nm
  • NA is 0 ⁇ 7
  • average cell size is 5 X 5 m 2
  • chip Assuming that the size is 81.92 X 81.92 m 2 , the calculation area required to obtain the simulation results can be reduced to about 1/3 compared to the entire chip calculation.
  • the calculation amount is proportional to the square of the calculation area because a two-dimensional projection image on the wafer is calculated. Therefore, when the calculation area is reduced to about 1/3, the calculation amount is reduced to about 1/9.
  • force S with a width of 1.62 ⁇ / ⁇ where sufficient accuracy is obtained. If this value does not lie on the mask design grid, a grid near 1.62 ⁇ / ⁇ The value on board is good.
  • FIG. 32 shows a pattern layout example in the peripheral area.
  • reference numeral 1003 denotes a cell boundary region
  • 1004 denotes an active region (diffusion layer region)
  • 1005 denotes a gate and a gate wiring
  • 1006 denotes a conduction hole (usually called a contact).
  • the outside of the active region 1004 is a region called a field, which is an insulating region from the semiconductor substrate, and is a region called isolation (element isolation).
  • isolation layer isolation
  • Gate width wl, contact diffusion layer alignment margin dl, d2, resolution failure between adjacent cells (pattern connection failure) avoidance margin si, gate wiring rise to diffusion layer Failure avoidance margin s2 is re-OPC It is an adjustment site. If the gate width wl is not within the accuracy of the standard, the transistor characteristics deteriorate due to the narrow channel effect. If the contact diffusion layer alignment margins dl and d2 cannot be obtained, conduction failure due to increased contact resistance occurs.
  • FIG. 33 shows an example of the adjustment variable for the gate width wl.
  • the width mwl is calculated using the genetic algorithm method described above.
  • Fig. 34 shows examples of adjustment variables for contact-diffusion interlayer alignment margins dl and d2.
  • the end of the diffusion layer is deformed into a hammerhead shape with width hi and length h2 and adjusted using the genetic algorithm method described above.
  • FIG. 35 shows an example of avoiding a resolution failure (pattern connection failure) between adjacent cells.
  • the amount of retreat at the tip of the active area 1004 is set as a variable il.
  • Fig. 36 shows an example of avoiding failure of the gate wiring on the diffusion layer.
  • the length i3 and width i2 of the receding region of the portion facing the gate wiring 1005 are variables. These variables are adjusted using the genetic algorithm method described above.
  • the gate length 11 shown in Fig. 37, the resolution avoidance failure (pattern connection failure) between adjacent cells (s4), the avoidance margin s3 for preventing the gate wiring from reaching the diffusion layer, and the protrusion amount pi from the active area are re-established OPC adjustment site. If the gate length 11 is not within the accuracy of the standard, the threshold voltage control of the transistor will not remain and the transistor characteristics will vary greatly, resulting in unstable circuit operation.
  • FIGS. 38 (a) and (b) are examples of adjustment variables with a gate length of 11. Since the gate length is the dimension that most sensitively affects the transistor characteristics, particularly high dimensional accuracy is required. Usually, since a pad for establishing electrical connection with the wiring layer is formed on a part of the gate wiring, the transfer pattern is deformed by the influence of the diffracted light from the part. In order to prevent the deformation at least on the active area, a complicated OPC as shown by 1005a in Fig. 38 (a) is applied. First, apply OPC so that the desired dimensional accuracy can be obtained in the case of a single cell. After that, referring to another cell pattern arranged on the outer circumference, as shown in Fig. 38 (b), the above-described genetic algorithm method is used with the line width mil as a variable while maintaining the outer shape of the OPC. Adjusted.
  • FIG. 39 is an example of avoiding a resolution failure (pattern connection failure) between adjacent cells.
  • the amount of retraction at the tip mhl of the gate wiring pattern 1005a which is the force of OPC in the case of a cell alone, is a variable.
  • Figure 40 shows an example of avoiding failure of the gate wiring on the diffusion layer.
  • the variables in this case are the width i4 and depth i 5 of the receding part of the gate wiring facing the diffusion layer region (active region) 1004. .
  • FIGS. 41A to 41C are examples of correction of protrusion from the active area.
  • the design layout is a rectangular layout as shown in Fig. 41 (a), with force S. When pattern transfer is actually performed, the pattern edges are shown in Fig.
  • Figure 42 shows an example of the contact layer layout.
  • Patterns for correcting OPC under the influence of external cells are patterns related to interaction regions 1009a to 1009e from external cell patterns 1008a to 1008e, and are indicated by reference numerals 1006a to 1006e in the figure.
  • the radius of these interaction regions 1009a to 1009e is a force of 1.62 / NA depending on the acid diffusion constant of the resist and the standard dimensional accuracy.
  • the variable of the pattern 1006f to which this re-OPC is applied is the height h5 and the width h6, and the center position 1020 is also used as a variable to correct the positional deviation.
  • the various variables in the above-mentioned Study Example 4 described above include blind search methods such as evolution strategies, genetic programming, insect search, EDA, stochastic search methods, It can also be adjusted by deterministic search methods including the hill-climbing method, the iterative golden section method, and the Powell method.
  • FIG. 52 is a schematic diagram showing the data structure of a cell designed based on Study Example 4.
  • the cell data structure consists of the following four elements: the design pattern shown in Fig. (A), the OPC pattern shown in Fig. (B), the adjustable area (first area), and the evaluation points. Has the same data structure as the conventional standard cell. So Therefore, compatibility with existing EDA tools can be easily maintained.
  • the OPC graphic pattern is generated using the method described in Study Example 1.
  • the adjustable region is synonymous with the peripheral region described in Study Example 4.
  • the part of the cell other than the adjustable area is called the fixed area.
  • the adjustable area is used to indicate that the OPC figure contained in it is to be adjusted. Judgment in the adjustable area eliminates the need to classify all OPC figures contained in a cell as being subject to adjustment, thus simplifying the data structure and simplifying cell design Can be.
  • the evaluation point which is the last element, is arranged at a location where an error should be calculated by comparing the dimension of the exposure pattern obtained by the optical simulation with the dimension of the design pattern.
  • the error information measured at the evaluation point is used in the evaluation of the chromosome in the genetic algorithm as the evaluation function described in Example 1 above.
  • stochastic search methods including annealing method, insect type search, EDA, etc.
  • deterministic search methods including hill climbing method, iterative golden section method, Powell method, etc. But it is obvious that it can be used in the same way.
  • Patent Document 6 Japanese Patent Laid-Open No. 2006-058413
  • Patent Document 7 Japanese Patent Laid-Open No. 2005-156606
  • Pattern A has 107 evaluation points, and each evaluation point was set at a point where the line width of the exposure pattern or the dimension of the exposure pattern tip was evaluated.
  • Fig. 47 shows the evaluation areas set as A1 to A8 and F1 to F4 in Fig. 46, and the maximum, minimum, and average values of line width variation in each evaluation area are shown in percentage (%). become.
  • the line width variation is expressed as an error indicating how much the exposure pattern has fluctuated with respect to the design pattern width.
  • Figure 47 shows that the error of all evaluation points is within 3%.
  • Figure 51 shows the measurement results of line width variation in Pattern B after adjustment. From this result, it can be seen that the maximum line width variation of 12.33% that occurred before adjustment was suppressed to within 3%. Furthermore, it can be confirmed that the adjustment of evaluation area A5 affects other areas.
  • OPC can be executed with local correction even if a part of the circuit is modified after layout.
  • FIG. 53 to FIG. 56 show the semiconductor device of the present embodiment that is most suitable for the above EDA tool.
  • the schematic diagram of an example of the structure of the data structure of the Sesucc is shown ! //. .
  • Fig. 5533 shows an example of the design pattern pattern LLPP of cecellul cceellll already processed by OOPPCC processing.
  • Cesellll is formed into, for example, a flat plane surface long rectangular shape.
  • a plurality of design and design pattern patterns LLPP forming the integrated circuit circuit pattern pattern pattern are arranged. . .
  • the design pattern Patter Turn LLPP has the same data structure as that of the conventional standard cell. .
  • the code sign CCLL is a cell outer periphery line ((cell boundary boundary)) indicating the outer periphery of the cecell cceellll. .
  • FIG. 5544 shows the above-mentioned Acejiyasu stabble ((AAddjjuussttaabbllee)) region area ((periphery peripheral region region, eleventh region) of the above-mentioned cesellll ), And the above-mentioned area (FFiixxeedd)). It is shown. .
  • the Ajijiya Yasutabururu territory is around the circumference of one ceserul cceellll, in the case where there are other ceserul cceelllls present. Ah, cerulel cceellll, and other cesul cceellll can be affected by the effect of the near light effect ((shape change))
  • the OOPPCC diagram that is included in this area is the target area for adjustment adjustment. It can be used for the purpose of showing here and here. .
  • the Ajijiya Yasutaburu region area here is based on the outer peripheral circumference CCLL (each of the four sides) as a reference criterion. This force can also be shown in the territory area, the directional force force only by the width WW11 on the inner inner side of the cceellll (the middle center)
  • the fixed region area was enclosed in the above-mentioned Ajijiyasu stabble region area within the cceellll.
  • the region of the territory which is caused by the effect of the near-light effect ((change in shape and shape)) of light from other cecellles cceellll
  • the change in dew exposure light pattern in the area does not affect the circuit characteristics of cceellll. It is an area. . Therefore, the OOPPCC figure figure contained in the fixed region is not the target of adjustment adjustment. Show me !! //, Ruru. .
  • Fig. 5555 shows the above-mentioned range of the influence of the outward-facing shadow of the cecellle cceellll ((the left hatched diagonal line of the hatched line (the spacing interval)). Is narrow and narrow VV, including Mononoto and Hirohiro ! //, including Mononoto)))))))) is shown !) //, Ruru . .
  • the outward impact influence range here is the design pattern Patter Turn LLPP ((Patter Turn Turn Outer / Outer Circumference Line) located on the outermost outer side in the Cceellll.
  • Patter Turn LLPP (Patter Turn Turn Outer / Outer Circumference Line) located on the outermost outer side in the Cceellll.
  • the width of the above-mentioned Ajiya Yasuta stabble area is from the center toward the outer and outer sides of the cesellll. Width is shown in the same area as WW11, with the same width as WW22.
  • the outer circumference of the outer circumference of the cell extends beyond the width of the CCLL, and only the width WW33, WW44 protrudes.
  • the territory area ((( The territory area that should not overlap the territory area of the Ajijiya Yasutabubururu)) (the 22nd territory) ((SSuurrrorouunnddiinngg)) Area, Outward outward shadow influence range, Phase, Phase [0122]
  • the surrounding area when there is another cell around a certain cell, it is possible that a certain cell has an optical proximity effect (shape change) on other surrounding cells. This is an area that shows a certain range, and is used to indicate that the OPC figure contained in it is an adjustment target.
  • Fig. 56 shows the adjustable region of the cell cell and the outward influence range in an overlapping manner.
  • the width W1 of the adjustable region is the same as the width W2 of the outward influence range.
  • the width S3 and W4 of the surrounding region (second region) are smaller than the width W1 of the adjustable region. This is for the following reason.
  • FIG. 57 shows that the widths W3 and W4 of the surrounding area are smaller than the width W1 of the adjustable area.
  • the broken line in FIG. 57 shows a state where the same width as the width W1 of the adjustable region is secured from the cell outer peripheral line CL to the outside of the cell cell.
  • the influence from the outside of the cell cell needs to be based on the cell peripheral line CL so that it can correspond to an adjacent cell cell of an arbitrary pattern.
  • the adjustable region needs to have a width W1 inside the cell cell from the cell outer periphery CL as a reference.
  • the influence on the cell cell outside itself is based on the design pattern LP (pattern outer perimeter line PU located on the outermost side inside the cell cell. That is, the outward influence range is From the pattern outer peripheral line PL on the inner side of the cell outer peripheral line CL, a width equal to the width W 1 of the adjustable region may be secured outside the cell cell from there.
  • the design pattern LP pattern outer perimeter line PU located on the outermost side inside the cell cell. That is, the outward influence range is From the pattern outer peripheral line PL on the inner side of the cell outer peripheral line CL, a width equal to the width W 1 of the adjustable region may be secured outside the cell cell from there.
  • the outward influence range is shifted inward by the amount moved to the inner side of the cell outer peripheral line CL.
  • the outer periphery of the affected area recedes inward from the broken line in FIG. Therefore, the widths W3 and W4 of the surrounding area are smaller than the width W1 of the adjustable area.
  • OPC graphic information and evaluation points are the same as those described with reference to FIG.
  • FIGS. Fig. 58 is a layout plan view of the mask pattern during the mask pattern design process
  • Fig. 59 is the above-mentioned
  • FIG. 60 shows an enlarged layout plan view of the main part of FIG.
  • the design pattern LP is omitted for easy viewing of the drawings.
  • the pattern outer peripheral line is omitted for easy understanding of the drawing.
  • the OPC process for correcting the shape change that occurs when the mask pattern is exposed to transfer the pattern is performed for each of the plurality of cells included in the cell library. Subsequently, as shown in FIG. 58, a plurality of OPC-treated cells are arranged on the mask layout plane.
  • each senor cell has its own adjustable region and its cell as shown in region RA of FIG. Make fine adjustments only for areas where the surrounding areas of other cells adjacent to the cell overlap (areas indicated by hatching with shaded areas) (only areas with upper-right inclination and areas with upper-left inclination only)! /, Don't make any adjustments! /,).
  • calculation for fine-tuning an OPC figure is performed only for an area where an adjustable area of a certain cell cell overlaps a surrounding area of another cell cell adjacent to the certain cell cell. good.
  • the range for fine-tuning the OPC figure (that is, the area of the area requiring calculation) can be reduced.
  • the widths W3 and W4 of the surrounding area are smaller than the width W2 of the adjustable area, so that the area to be calculated for fine adjustment of the OPC figure is made smaller. That power S. Therefore, in this embodiment, the OPC process can be performed efficiently, and the mask pattern can be generated in a practical time. This significantly reduces the processing time and processing costs for mask manufacturing.
  • the OPC processing time for mask pattern design is as follows. Therefore, the manufacturing device manufacturing TAT can be shortened. As a result, the manufacturing cost of the semiconductor device can be reduced.
  • the force described in the case where the created mask is applied to a semiconductor device manufacturing process is not limited to this.
  • a liquid crystal device, a micromachine, a magnetic head, etc. The present invention can be applied to a step of reducing projection exposure of a desired pattern.
  • the present invention can be used for a mask pattern design method using a cell library pattern subjected to optical proximity correction (OPC) processing.
  • OPC optical proximity correction

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

Dans la présente invention, le temps requis pour un traitement de correction de proximité optique (CPO) dans le cadre de la conception d'un modèle de masque est réduit. Un modèle de masque est formé en déposant des couches de cellules ayant subi un traitement CPO préalable, puis, au moment d'ajuster finement une quantité de correction pour le CPO, pour chaque cellule, on effectue le calcul pour l'ajustement fin destiné uniquement à une région dans laquelle une région ajustable de la cellule elle-même et des parties voisines d'autres cellules adjacentes à la région ajustable se chevauchent les unes les autres. De cette manière, on peut réduire un intervalle de réalisation de l'ajustement fin d'un modèle CPO (une zone d'une région pour laquelle le calcul est nécessaire). Étant donné que le modèle de masque peut être conçu de manière efficace, le temps et le coût de traitement nécessaires à la conception du modèle de masque peuvent être remarquablement réduits.
PCT/JP2007/066108 2006-08-25 2007-08-20 Procédé de conception d'un modèle de masque et procédé de fabrication d'un dispositif semi-conducteur comprenant ce dernier WO2008023660A1 (fr)

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JP2009216936A (ja) * 2008-03-10 2009-09-24 Fujitsu Microelectronics Ltd 階層構造を用いたフォトマスクデータの処理方法、フォトマスクデータ処理システム、および、製造方法
JP2010079184A (ja) * 2008-09-29 2010-04-08 Toshiba Corp パタンデータの作成方法およびパタンデータ作成プログラム
CN102147567A (zh) * 2011-04-01 2011-08-10 中国科学院微电子研究所 一种基于Cell的层次化光学邻近效应校正方法
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